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EE241 - Spring 2007Advanced Digital Integrated Circuits

Lecture 22: SRAM

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AnnouncementsHomework #4 due todayFinal exam on May 8 in classProject presentations on May 3, 1-5pm

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Class MaterialLast lecture

Technology and environment variabilityToday’s lecture

SRAM

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700 600 500 400 300 200 10010090 80 70 60 50 40 30

0.1

1

10

ITRS Single Cell Reported Individual Cell Reported Cell in Array

SR

AM C

ell S

ize

(um

2 )

Technology Node (nm)

SRAM Scaling Trends

Individual SRAM cell area able to track ITRS guidelineArray area deviates from ITRS guideline at 90nmMemory design no longer sits on the 0.5x area scaling trend!

300 200 100 90 80 70 60 50 40 30

0.1

1

10

100

ITRS Effective Cell Reported Effective Cell

SRAM

Cel

l Siz

e (u

m2 )

Technology Node (nm)

0.5x effective cell area scaling difficult

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5

Memory Scaling

• Memory latency demands larger last level cache (LLC)• Memory is more energy-efficient than logic• LLC approaches 50% chip area for desktop and mobile processors• LLC approaches 80% chip area for server processors

Vivek De, Intel 2006

180 160 140 120 100 80 60

1

10

On-

Die

L3

Cac

he s

ize

(MB

)

Technology Node (nm)

Server processors

Itanium®Processors

Xeon®Processors

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6-T SRAM Cell

• Improve CD control by unidirectional poly• Relax critical layer patterning requirements• Optimizing design rules is key

Vivek De, Intel 2006

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SRAM cell design trends

•• Improve CD control by unidirectional polyImprove CD control by unidirectional poly

•• Relax critical layer patterning requirementsRelax critical layer patterning requirements

•• Optimizing design rules is keyOptimizing design rules is key

•• Shorter bitline enables better cycle time and/or array efficienShorter bitline enables better cycle time and/or array efficiencycy

•• Full metal wordline with wider pitch achieves better RCFull metal wordline with wider pitch achieves better RC

Cell in 90nm(1μm2)

Cell in 65nm(0.57μm2)

0.46x1.24μmIEDM

’

02

VDD

GNDWL

BL BLB

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Ion/Ioff: Cell Read and Leakage

H. Pilo, IEDM 2006

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9

SRAM Cell/ArrayRead stabilityWrite stabilityRead current

WL

BL

VDD

M5 M6

M4

M1

M2

M3

BL

QQ

Access Transistor

Pull down Pull up

10

WL

BL

AXL

NPD

Access‘1’ ‘0’

Load

AXR

NRNL

PRPL

BL

VDD

Data RetentionLeakage

Scaling trend: Increased gate leakage + degraded ION/IOFF ratio

Lower VDD during standby

PMOS load devices must compensate for leakage

SRAM Design – Hold (Retention) Stability

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The Data-Retention Voltage (DRV) of SRAM

DRVV when , DDinverterRight 2

1

inverterLeft 2

1 =∂∂

=∂∂

VV

VV

VDD

V1

M4

M3

M6M5

M2

M1

Leakagecurrent

V2

Leakagecurrent

VDDVDD

0 0

0 0.1 0.2 0.3 0.40

0.1

0.2

0.3

0.4

V1 (V)

2

VTC1VTC2

VDD=0.18V

VDD=0.4V

VTC of SRAM cell inverters

V2

(V)

When Vdd scales down to DRV, the Voltage Transfer Curves (VTC) of the internal inverters degrade to such a level that Static Noise Margin (SNM) of the SRAM cell reduces to zero.

DRV Condition:

Qin, ISQED’04

120 50 100 150 200 250 300

0

50

100

150

200

250

300

Simulated DRV of 1500 SRAM cells (mV)

His

togr

am o

f cel

l #

Monte-Carlo Simulation of DRV Distribution

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13H. Pilo, IEDM 2006

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Read Stability – Static Noise Margin (SNM)

• Read SNM is typically the most stringent constraint• SNM shrinks with each generation

0 0.5 10

0.5

1

VL (V)

VR (V

)

90nm simulation

Read SNM[1]

[1] E. Seevinck, JSSC 1987

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SRAM Design – Read StabilityWL

BL

AXL

NPD

Access

‘1’ V>0

Load

AXR

NRNL

PRPL

BL

VDD

Read margin and retention margin

[Bhavnagarwala, IEDM’05]

Retention fluctuations

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Read Stability – N-Curve

[1] E. Seevinck, JSSC 1987

• A, B, and C correspond to the two stable points A and C and the meta-stable point B of the SNM curve

• When points A and B coincide, the cell is at the edge of stability and a destructive read can easily occur

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17H. Pilo, IEDM 2006

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Write Stability – Write Noise Margin (WNM)

0 0.5 10

0.5

1

VL (V)

VR (V

)

90nm simulation

WNM[1]

• Write stability is becoming more stringent with scaling• Optimizing read and write stability at the same time is difficult

[1] A. Bhavnagarwala, IEDM 2005

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-0.20

0.20.40.60.8

11.2

0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07

Time (s)

Volta

ge (V

)

WM

-0.20

0.20.40.60.8

11.2

0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07

Time (s)

Volta

ge (V

) WM

Highest BL voltage under which write is possible when BLC is kept precharged (left)

Difference between VDD and lowest WL voltage under which write is possible when both bit-lines are kept precharged (right)

Can be directly measured in large memory arrays via BL currents

BLWL

Write Stability – Traditional Write Margin (TWM)

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Write Stability – Write Current (N-Curve)

[1] C. Wann et al, IEEE VLSI-TSA 2005

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21H. Pilo, IEDM 2006

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SRAM Design – Read/Write StabilityWL

BL

AXL

NPD

Access

‘1’ V>0

Load

AXR

NRNL

PRPL

BL

VDD

Read margin is typically the most stringent constraint

Cell read voltage must stay below cell trip voltageHarder to achieve with process induced variations

Noise margin degraded with technology scaling

Cell Trip Voltage

Cell Read Voltage

Cell Stability

Read Upset Occurs

Technology Scaling

Volta

ge

H. Pilo, ISSCC’2005

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23H. Pilo, IEDM 2006

24H. Pilo, IEDM 2006

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25H. Pilo, IEDM 2006

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Multi-Voltage SRAM

VminVminVminPeriphery

VmaxVmaxVmaxCell well

VminVminVmaxCell VDD

N/AVmaxVminWL

VminVminVminBL Precharge

RetentionWriteRead

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Dynamic VDD Implementation

VCC selection is along column direction to decouple the Read & Write

VCC_lo

cell cell cell cell cellWL

cell cell cell cell cellWL

MUX (8:1)W R R R

cellcell cellcell cellcell cellcell cellcellWL

cellcell cellcell cellcell cellcell

VCC_hiMUX MUX MUX MUX MUX

BI MUX

VCC MUX

Zhang, ISSCC’05

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The Rest in Class PresentationsRead/Write assist circuitsAlternate cells for subthreshold operationFinFET/double-gate designsColumn design techniquesLeakage suppressionSense amps…

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SRAM ScalingApproaching fundamental limits:

Don’t scale cell sizeIncrease transistor count (from 6)Change technology (e.g. double-gate FETs)eDRAMOr something else…

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Other SRAM Alternatives

[1] L. Chang, VLSI Circuits 2005

• Dual-port read/write capability (register file like cells)

• N0, N1 separates read and write• No Read SNM constraint• Half-selected cells still undergo read stress – no single cell write capability

• Stacked transistors reduce leakage

8-T SRAM [1]

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eDRAMProcess cost: Added trench capacitor

Barth, ISSCC’07, Wang, IEDM’06

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