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EE241 - Spring 2005Advanced Digital Integrated Circuits

Lecture 18:Timing

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Announcements

No lecture on Wednesday (Family Emergency)

Make-up lecture on Friday at 3pm by Dejan Markovic(to be confirmed)

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Timing Overview

Synchronization Approaches

Synchronous SystemsTiming methodologies

Latching elements

Clock distribution

Clock generation

Asynchronous Systems

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References

Chapter 11 – Clocked storage elements, by H. Partovi

High-speed CMOS design styles, Bernstein, et al, Kluwer 1998.

Unger/Tan IEEE Trans. Comp. 10/86

Harris/Horowitz JSSC 11/97

Messerschmitt JSAC 10/90Stojanović/Oklobdžija JSSC 4/99

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Issues in Timing

D. Messerschmitt, Oct 1990

Boolean signal - stream of 0’s and 1’s, generated by saturating circuits and bistable memory elements

but …finite rise and fall times inter-symbol interference

metastability leads to non-deterministic behavior

signal transitions are crucialtypically defined with respect to slicer/sampler

associated clock with uniformly spaced transitions

0 1 0 0 0 0 0 01 1 1 1 1 1 1 1 1

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Boolean signalBoolean signal

Isochronousf + Δf = constant

Anisochronousf + Δf ≠ constant

SingleSingle

Clock signal :

f + Δf average frequency

dφ/dt instantaneous frequency deviation

Issues in Timing

“equal” “not equal”

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Issues in Timing

Synchronousf + Δf identicalΔφ(t) = 0 (or known)

Asynchronous

MesochronousΔφ(t) variable (but bounded)

PlesiochronousAverage Frequencyalmost the same

HeterochronousNominallyDifferent freq

“together” “not together”

“near”

“middle” “different”

Two Boolean SignalsTwo Boolean Signals

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Some Definitions

Signals that can only transition at predetermined times with respect to a signal clock are called “{syn,meso,plesio}chronous”

An asynchronous signal can transition at any arbitrary time.

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Some Definitions (contd)

Synchronous Signal: exactly the same frequency as local clock, and fixed phase offset to that clock.

Mesochronous Signal: exactly the same frequency as local clock, but unknown phase offset.

Plesiochronous Signal: frequency nominally the same as local clock, but slightly different

Mesochronous and plesiochronous concepts are very useful for thedesign of systems with long interconnections, and/or multipleclock domains

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Some other definitions

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Synchronous Computation

ts

tp ts

to + T + tp ≥ to+ts

orT ≥ ts-tp

Length of uncertainty is a fundamental property of the computational blockLength of certainty period is function of clock period

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Clocking Requirements

T > ts - tp

or T can be smallerthan ts (or tpmax)

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Synchronous Computation

Adding extra uncertainty:- Clock skew (random but bounded) δmax- interconnect delay (random but bounded) dmax

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The Timing Uncertainty

Tgate,nom

t

Tclock, worst

Due to data dependenciesand device variations

To clock skew and jitterand fab. variations

Tclock, nom

Uncertainty

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The Timing Uncertainty – Spooling Forward

Tgate,nom

t

Tclock

Uncertainty!!!!

Larger fraction of clock period devoted to uncertainty,negating speed gate of scaled technologies

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Mesochronous Interconnect

clock

synchronous

islandData synchronous

island

Phase Generator

Select

PhaseDetect

DataR1 R2

Clock

Local Synchronization

samples in certainty period of signal

(local)

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Mesochronous Communication

R1Interconnect R2

ClkA

D2

Block ADelay

Block B

ClkB

D4

Control

D1

D3

VariableDelay Line

Timing Recovery

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Plesiochronous Communication

Originating ReceivingFIFO

TimingClock C1

Clock C 2

Module Module

Recovery

C3

Does only marginally deal with fast variations in data delay

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Anisochronous Interconnect

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Synchronous Pipelined Datapath

In

tpd,reg tpd1

DR1

Q

CLK

LogicBlock #1

tpd2

DR2

QLogic

Block #2

tpd3

DR3

Q DR4

QLogic

Block #3

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Latch versus Flip-Flop

Latchstores data when clock is low (high)

D

Clk

Q D

Clk

Q

Flip-Flop (or Register)

stores data when clock rises (falls)

Clk Clk

D D

Q Q

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Latch Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWmTSU

TD-Q

Delays can be different for rising and falling data transitions

Unger and TanTrans. on Comp.10/86

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Flip-Flop (Register) Parameters

D

Clk

Q

D

Q

Clk

TClk-Q

TH

PWm

TSU

Delays can be different for rising and falling data transitions

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Example Clock System

Courtesy of IEEE Press, New York. © 2000

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Clock Nonidealities

Clock skewSpatial variation in temporally equivalent clock edges; deterministic + random, tSK

Clock jitterTemporal variations in consecutive edges of the clock signal; modulation + random noise

Cycle-to-cycle (short-term) tJSLong term tJL

Variation of the pulse width for level sensitive clocking

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Clock Skew and Jitter

Both skew and jitter affect the effective cycle time

Only skew affects the race margin

Clk

Clk

tSK

tJS

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Clock Uncertainties

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4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty

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Clock Skew

# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal – δ/2

Latest occurrenceof Clk edge

Nominal + δ /2

δ

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Positive and Negative Skew

R1In

(a) Positive skew

CombinationalLogicD Q

tCLK1CLK

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay

R1In

(b) Negative skew

CombinationalLogicD Q

tCLK1

delay

tCLK2

R2

D Q CombinationalLogic

tCLK3

R3• • •D Q

delay CLK

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Positive Skew

CLK1

CLK2

TCLK

δ

TCLK + δ

+ thδ

2

1

4

3

Launching edge arrives before the receiving edge

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Negative Skew

CLK1

CLK2

TCLK

δ

TCLK + δ

2

1

4

3

Receiving edge arrives before the launching edge

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Longest Logic Path in Edge-Triggered Systems

Clk

P

TSU + Tsk + TJS

TClk-QTLM

Latest point of launching

Earliest arrivalof next cycle

Unger and TanTrans. on Comp.10/86

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Clock Constraints in Edge-Triggered Systems

JSskSULMQMclk TTTTTP ++++≥ −

LMQMclkSUJSsk TTTTTP +≥−+− −

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

‘Double-sided’ definitions of setup and jitter

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Shortest Path

ClkTClk-Q TLm

Earliest point of launching

Data must not arrivebefore this time

ClkTH

Nominalclock edge

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Clock Constraints in Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

HskLmQmclk TTTT +≥+−

QmclkHskLm TTTT −−+≥

Jitter does not really play as this concerns the same clock edge

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Clock Constraints in Edge-Triggered Systems

Courtesy of IEEE Press, New York. © 2000

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Flip-Flop – Based Timing

Flip-flop

Logic

φ

φ = 1φ = 0

Flip-flopdelay

Skew

Logic delay

TSU

TClk-Q

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Flip-Flops and Dynamic Logic

φ = 1φ = 0

Logic delay

TSU

TClk-Q

φ = 1φ = 0

Logic delay

TSU

TClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logicNo way to hide the precharge overhead

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Latch timing

D

Clk

Q

tD-Q

tClk-Q

When data arrives to transparent latch

When data arrives to closed latch

Data has to be ‘re-launched’

Latch is a ‘soft’ barrier

Latch insensitive to skew/jitter in transparent zone

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Single-Phase Clock with Latches

Latch

Logic

φ

Clk

P

PW

Tskl Tskl TsktTskt

Unger and TanTrans. on Comp.10/86

sktsklsk TTT +=In Chapter 11:

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Preventing Late Arrivals

Clk

P PW

TSU Datamustarrive

Clk

TClk-Q TLM

TSU

Clk

TD-Q TLM

TSUPW

TSU

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Preventing Late Arrivals

LMQMD

QMclkSUsktsklT

T

PWTTTTP +

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧ −+++

≥−

− ,max

PWTTTTTP sktsklSULMQMclk −++++≥ −

LMQMD TTP +≥ −

Or:

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Preventing Premature Arrivals

ClkTHPW

QmClkHsktsklLm TPWTTTT −−+++≥

TClk-Q TLm

Two cases, reduce to one:

QmClkHsktsklLm TPWTTTT −−+++≥

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Single-Latch Timing

Latch

Logic

φ LMQMD

QMclkSUsktsklT

T

PWTTTTP +

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧ −+++

≥−

− ,max

QmClkHsktsklLm TPWTTTT −−+++≥

Bounds on logic delay:

Either balance logic delaysor make PW short

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Latch-Based Design

L1Latch

Logic

Logic

L2Latch

f

L1 latch is transparentwhen f = 0

L2 latch is transparent when f = 1

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Latch-Based Timing

As long as transitions are within the assertion period of the latch,no impact of position of clock edges

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Latch Design and Hold Times

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Latch-Based Timing

Longest path

LLMLHMQMD TTTP ++≥ −2

Short paths

QmClkHSKCLLm TTTT −−+≥

QmClkHSKCLHm TTTT −−+≥

Same as register-based design but holdsfor both clock edges

Independent of skew

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Latch-Based Timing

L1Latch

Logic

Logic

L2Latch

φ

φ = 1

φ = 0

L1 latch

L2 latch

Skew

Can tolerate skew!

Longpath

Shortpath

Static logic

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Soft-Edge Properties of Latches

Slack passing – logical partition uses left over time (slack) from the previous partitionTime borrowing – logical partition utilizes a portion of time allotted to the next partitionMakes most impact in unbalanced pipelines

Bernstein et al, Chapter 8, Partovi, Chap 11

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Slack-Passing and Cycle Borrowing

For N stage pipeline, overall logic delay should be < N Tcl

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Slack Passing Example

Edge Triggered:T = 125 nsec

Latch-based:T = 100 nsec

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Domino Logic with Latches

Time available to logic is P – 2TD-Q

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Latches with Dynamic Logic

φ = 0

φ = 1

L2 latchL1 latch

Shortpath

Clock evaluates logicand opens subsequent latch:

Static signals driving dynamiclogic must be eithernon-inverting orstable before evaluation

Phase1-dominoprecharges

Phase2-dominoevaluates

Phase1-dominoevaluates

Phase2-dominoprecharges

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Clock Skew in Dynamic

Time penalty: TL = P – (2TD-Q + 2Tsk)

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Non-Balanced Phase Delays

Time penalty: TL = P – (2TD-Q + 2Tsk) - Timbal

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Skew-Tolerant Domino

General Reference:Harris, Horowitz, “Skew-tolerant domino circuits”

ISSCC’97, JSSC 11/97

Also slides from D. Harris’s Web site:

http://www3.hmc.edu/~harris/index.html

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Skew-Tolerant Domino

Overlap clocks:• x evaluates before y precharges• implicit latch between φ1 and φ2• no need for latch between domino phases

From [Harris]

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Multiple Phases

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Precharge Phase

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Evaluation Phase

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Skew Tolerance

From [Harris]

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Time Borrowing