1
EE241 Spring 2010EE241 - Spring 2010Advanced Digital Integrated Circuits
Lecture 11: SRAM scalingTi iTiming
Announcements
Please create project web pages and send me a link to them
Homework #2 posted this week
2
2
Outline
Last lectureSRAM options
This lectureTiming
3
SRAMSRAM
Redundancy and ECC
3
ECC
5Kawahara, ISSCC’07 tutorial
Multi-bit Errors
6Kawahara, ISSCC’07 tutorial
4
Multi-bit Errors
7Kawahara, ISSCC’07 tutorial
Multi-bit Errors
8
5
Multi-bit Errors: Interleaving
9
SRAMSRAM
Options for scaling
6
SRAM Scaling
Approaching fundamental limits:Don’t scale cell size
Increase transistor count (from 6)
Change technology (e.g. double-gate FETs)
eDRAM
Or something else…
11
SRAM Alternatives
8-T SRAM
• Dual-port read/write capability (register file-like cells)
12L. Chang, VLSI Circuits 2005
• Dual-port read/write capability (register file-like cells)
• N0, N1 separates read and write• No Read SNM constraint
• Half-selected cells still undergo read stress – no single cell write capability
• Stacked transistors reduce leakage
7
Alternatives: Thin-Body MOSFETs
Thin body suppresses short channel effectsChannel lightly doped higher carrier mobility
TOX scaling not needed less reliability issues
• Double-gate structure is scalable to Lg<10nm
GateGate
Lg
13
Double-Gate (DG)
Gate
Source Drain TSi
Ultra-Thin Body (UTB)
Buried Oxide
Substrate
Source Drain TSi
Double-Gate “FinFET”
Gate
Drain
Gate
DrainGate
Lg
Lg
PlanarDouble gate FET
Gate
Source DrainTSiSource
Gate
(90o rotation)
Fin Width = TSi
FinFET
Source
Fin Height HFIN
14
Double-gate FET
• FinFET layout is similar to that of a planar FET• Rotation allows for self-aligned gate electrodes
( )D. Hisamoto et al., IEDM, 1998
N. Lindert et al., IEEE EDL, 2001
8
Double-Gate vs. Tri-Gate
Drain
GateLg Drain
GateLg
Isolation
Fin Width = TSiFin Width = TSi
Source
Fin Height HFIN = W/2
Source
15
High device currents per area/layout density
• Requires contacts to fins and narrow fin pitch
Double-gateW = 2HFIN
B. Doyle et al., VLSI, 2003
Tri-gateW= 2HFIN + TSi
1FIN = 175mV
2FIN 240 V1
1FIN 175mV
6-FinFET SRAM Cell
2FIN = 240mV
High VT NPD
Vs
n2
(V)
Vs
n2
(V)
Vs
n2
(V)
.
.
.
.
.
.
.
.
0 2
0.4
0.6
0.8
2FIN - 240mV
1FIN - 175mV
475n
m
ΦGATE, N/P = 4.75eV
16
0 0.5 1
Vsn1 (V)0 0.5 1
Vsn1 (V)0 0.5 1
Vsn1 (V)
0
175mV SNM w/ 0.36m2 cell area
Cell Area = 0.36m2
GATE, N/P
9
1FIN = 175mV2FIN 240 V
1
1FIN 175 V
Access LoadNPD
6-FinFET SRAM Cell: 2 Fins
2FIN = 240mV
High VT NPD
Vs
n2
(V)
Vs
n2
(V)
Vs
n2
(V)
.
.
.
.
.
.
.
.
0 2
0.4
0.6
0.8
2FIN - 240mV
1FIN - 175mV
880nm
475
nm
ΦGATE, N/P = 4.75eV
17
240mV SNM w/ 0.42m2 cell area36% SNM improvement w/ 17% area penalty
0 0.5 1
Vsn1 (V)0 0.5 1
Vsn1 (V)0 0.5 1
Vsn1 (V)
0Cell Area = 0.42m2GATE, N/P
Bulk-Si FinFETsLee, VLSI’04, Kavaleros, VLSI’06
FinFETs can be made on FinFETs can be made on bulk-Si wafers lower cost
improved thermal conduction to mitigate self-heating effects
18
g
integration with planar bulk-Si MOSFETs is possible
Process flow illustration fromLee, VLSI’04
10
eDRAM
Process cost: Added trench capacitor
19Barth, ISSCC’07, Wang, IEDM’06
TimingTiming
11
Synchronous Pipelined Datapath
In
tpd,reg tpd1
D
R1
Q
CLK
LogicBlock #1
tpd2
D
R2
QLogic
Block #2
tpd3
D
R3
Q D
R4
QLogic
Block #3
21
Latch Parameters
D QUnger and TanTrans. on Comp.
Clk
D
Clk
T
PWmTSU
Trans. on Comp.10/86
22
QTCQ
TH
TDQ
Delays can be different for rising and falling data transitions
12
Flip-Flop (Register) Parameters
D Q
Clk
D
Clk
TH
PWm
23
QTCQ
TSU
Delays can be different for rising and falling data transitions
Example Clock System
24Courtesy of IEEE Press, New York. 2000
13
Clock Nonidealities
Clock skewSpatial variation in temporally equivalent clock edges; deterministic + random, tSKSK
Clock jitterTemporal variations in consecutive edges of the clock signal; modulation + random noise
Cycle-to-cycle (short-term) tJSLong term tJL
Variation of the pulse width
25
Variation of the pulse width for level sensitive clocking
Clock Skew and Jitter
Clk1
tSK
Both skew and jitter affect the effective cycle time
Clk2
tSK
tJS
26
Only skew affects the race margin, if jitter is from the sourceDistribution jitter affects both
14
Clock Uncertainties
4
3
Power Supply
I t t2
3 Interconnect
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Devices
27
Sources of clock uncertainty
Next Lecture
Timing
28