EE365 Adv. Digital Circuit Design Clarkson University Lecture #5

EE365Adv. Digital Circuit Design

Clarkson University

Lecture #5

Electrical Behavior of Logic Circuits

Topics• Electrical Characteristics

– Noise & Noise Margins– Voltage Levels– Fan-in– Fan-out– Output Types

• Timing Characteristics– Transition Delay

Rissacher EE365Lect #5

Logic levels

• Undefined regionis inherent– digital, not analog

• Switching threshold varies with voltage, temp, process, phase of the moon– need “noise margin”

• The more you push the technology, the more “analog” it becomes.• Logic voltage levels decreasing with process

– 5 -> 3.3 -> 2.5 -> 1.8 V


Electrical Characteristics

• Digital analysis works only if circuits are operated in spec:– Power supply voltage– Temperature– Input-signal quality– Output loading

• Must do some “analog” analysis to prove that circuits are operated in spec.


Output Specifications• Voltage:

– VOLmax and VOHmin

• Current:– Output sinks current when current flows

into the output - max low state output current: IOLmax

– Output sources current when current flow out of the output - max high state output current: IOHmax


DC Loading• An output must

sink current from a load when the output is in the LOW state.

• An output must source current to a load when the output is in the HIGH state.


Output-voltage drops

• Resistance of “off” transistor is > 1 Megohm, but resistance of “on” transistor is nonzero,– Voltage drops across “on” transistor, V = IR

• For “CMOS” loads, current and voltage drop are negligible.

• For TTL inputs, LEDs, terminations, or other resistive loads, current and voltage drop are significant and must be calculated.


Output-drive specs

• VOLmax and VOHmin are specified for certain

output-current values, IOLmax and IOHmax

– No need to know details about the output circuit, only the load.

– CMOS devices typically have two sets of output drive specs:

• CMOS loads• TTL or other resistive loads


Manufacturer’s data sheet


Driving Non-Ideals Loads

• Many typical loads may be represented by a resistive network

• Find the Thevenin equivalent circuit (review from ES 250) of the load

• Compute the output current and voltages to determine if they are within specification


Example loading calculation

• Need to know “on” and “off” resistances of output transistors, and know the characteristics of the load.


Estimating Values for Internal Resistances

• Estimate the value of the internal resistances from the specification for maximum output current.– Effective p-channel on resistance is

Rp = [ VDD - VOHmin ] / | IOHmax |

– Effective n-channel on resistance is

Rn = VOLmax / IOLmax


Example Using Estimated Values

+ 5 v

1 k

2 k

=>

667

DC3.3 v

Thevenin equivalentcircuit

Output Specifications for CMOS (HC) driving TTL loadsVOHmin = 4.3 v VOLmax = 0.33 vIOHmax = - 4.0 ma IOLmax = 4.0 ma

Rp = [5 - 4.3] v / 4 ma = 175. ohmsRn = 0.33 v / 4 ma = 82.5 ohms

High State: Iout = - [5 - 3.3] / [175 + 667] = - 2 ma

Vout = 5 - ( 0.002 x 175) = 4.65 v

667

DC3.3 v

Rp

+ 5 v

High State Model


Limitation on DC load• If too much load, output voltage will go outside of

valid logic-voltage range.

• VOHmin, VIHmin

• VOLmax, VILmax


Input-loading specs

• Each gate input requires a certain amount of current to drive it in the LOW state and in the HIGH state.– IIL and IIH

– These amounts are specified by the manufacturer.


Fan-out

The fan-out of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specs.

1

N

Fan-out


Computing Fan-out• General fan-out is the minimum of

– high state fan-out– low state fan-out

• In each case, determine max input current of each expected load and max output current of the driving device

• Fan-out = max outputDEVICE / max inputLOAD

• Fan-outL = IOLmax/IILmax

(for high state L H)


In-Class Practice Problem• Find the fan-out of the following device when

connected to identical devicesIOLmax

0.02 mA

IOHmax-0.03 mA

VOLmax0.1 V

VOHmax4.4 V

IILmax±1.0 μA

IIHmax±1.0 μA


In-Class Practice Problem• Find the fan-out of the following device when

connected to identical devicesIOLmax

0.02 mA

IOHmax-0.03 mA

VOLmax0.1 V

VOHmax4.4 V

IILmax±1.0 μA

IIHmax±1.0 μA

-20 μA / ±1.0 μA = 20 (minimum of two states)


Fan-out Note• Generally, when driving CMOS devices, fanout is nearly

unlimited because CMOS inputs require almost no current• When driving TTL devices, this is not the case


Fan-inFor a given logic family, the maximum number

of inputs available on any one gate is called the fan-in.

1

N

Fan-in


Fan-in• Limited in practice by the characteristics of a

particular technology.• For CMOS, limited by the additive “on”

resistance of series transistors in either the PUN or PDN.

• Typical values are 4 for NOR gates and 6 for NAND gates.

• No need to calculate


Fan-in

• Cascade Structure for Large Inputs works around the fan-in limitation– 8-input CMOS NAND:

Rissacher EE365Lect #4 Rissacher EE365Lect #5

Non-Ideal Inputs

• What happens if the gate input is not nearly zero or nearly +5 v ?– Can occur if driven by devices of another

logic family (e.g. TTL drives CMOS)

– Inputs may still meet VIHmin or VILmax


Non-Ideal Inputs

T

V out

p-channel

n-channel

V in

V DD Output High StateIf Vin = 0 v. =>

p-channel device conductsn-channel device is off

As Vin increases n-channel device begins to turn-on

Output Low StateIf Vin = 5 v =>

p-channel device is offn-channel device conducts

As Vin decreasesp-channel device begins to turn-on


Non-Ideal Inputs• Example: suppose input voltage is ~ 1.3 v

instead of 0 v.– The p-transistors will have increased resistance– The n-transistors will have decreased resistance

• Result: output voltage will be reduced, but still above VOHmin

• Also increased current flow from VDD to ground

• Result: increased power consumption


Unused Inputs

• A three NAND is available, but you only need a two input NAND - what about the unused input?

• Logically, an unused input should be:– a constant logic 1 for a NAND gate– a constant logic 0 for a NOR gate– identical to any one of the other inputs


Unused Inputs

A

B (A B)'

+ 5 v

A

B (A B)'


Unused Inputs - CMOS• Electrically, must NOT be left unconnected• Very high input impedance => any noise can

cause the apparent input value to change between a logic 0 and a logic 1.

• Highly susceptible to electrostatic discharge (ESD)

• Loose devices easily destroyed on a winter’s day in Potsdam !


Unused Inputs - TTL

• May be left “open” (appears as logic 1)

• Can be changed by noise

• If pulled high or low by resistor, must carefully compute resistor value since input current not negligible


Dynamics

• Fanout also limited by dynamic considerations

• Switching from low to high state or high to low cannot happen instantly - why not ?

• If the load has any capacitive effects, what do you know about voltage across a capacitor?


Dynamics

Vout

0 v

+ 5 v

Vout = VDD e -t/ Rn C


AC Loading

• AC loading has become a critical design factor as industry has moved to pure CMOS systems.– CMOS inputs have very high impedance,

DC loading is negligible.– CMOS inputs and related packaging and

wiring have significant capacitance.– Time to charge and discharge capacitance

is a major component of delay.


Transition times


Circuit for transition-time analysis


HIGH-to-LOW transition


Exponential rise time


LOW-to-HIGH transition


Exponential fall time

t = RC time constantexponential formulas, e-t/RC


Transition-time considerations• Higher capacitance ==> more delay• Higher on-resistance ==> more delay• Lower on-resistance requires bigger transistors• Slower transition times ==> more power

dissipation (output stage partially shorted)• Faster transition times ==> worse

transmission-line effects (Chapter 11)• Higher capacitance ==> more power

dissipation (CV2f power), regardless of rise and fall time


Open-drain outputs

• No PMOS transistor, use resistor pull-up


Open-drain transition times• Pull-up resistance is larger than a PMOS transistor’s

“on” resistance.

• Can reduce rise time by reducing pull-up resistor value– But not too much


Power Consumption

• Static power dissipation - no signal transitions

• Dynamic power dissipation - signal transitions– P = [ CPD + CL ] VDD

2 f , where f is the frequency of signal transitions


Comparison of Signal LevelsCMOS

(HC, AC)

0 v

5 v

TTL (S, LS, AL, ALS, F)

0 v

5 v

CMOS (HCT, ACT)

0 v

5 v

0.5 v

1.5 v

3.5 v

4.4 v

VOL

VIL

VIH

VOH

VOL VOL

VIL VIL

VIH VIH

VOH VOH

0.4 v0.8 v

2.0 v

2.4 v

0.4 v0.8 v

2.0 v

2.4 v


TTL Input Specifications

• Unlike CMOS, TTL gates sink or source current at the input

• Fanout must examine input currents and output currents

• Low state input sources current ( it flows out of the device)

• High state input sinks current• LS-TTL: IILmax= -0.4 mA; IIHmax= 20 A


TTL Output Specifications

• Similar to CMOS

• LS-TTL: IOLmax = 8 mA; IOHmax = -400 A

• High state fanout = low state fanout = 20• But note that TTL has very asymmetric output

drive capability– low state output can sink much more than high

state output– moderate current loads only in low state


TTL differences from CMOS• Asymmetric input and output characteristics.• Inputs source significant current in the LOW

state, leakage current in the HIGH state.• Output can handle much more current in the

LOW state (saturated transistor).• Output can source only limited current in the

HIGH state (resistor plus partially-on transistor).

• TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS).


Next Class• Timing Considerations

• Propagation Delay

• Hazards


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EE365 Adv. Digital Circuit Design Clarkson University Lecture #5

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