EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung

Slide 1EE40 Fall 2009 Prof. Cheung

EE40 Lec 15

Logic Synthesis and

Sequential Logic Circuits

Prof. Nathan Cheung10/20/2009

Reading: Hambley Chapters 7.4-7.6Karnaugh Maps: Read following before reading textbookhttp://www.facstaff.bucknell.edu/mastascu/eLessonsHTML/Logic/Logic3.html


Suppose we are given a truth table for a logic function.

Is there a method to implement the logic function using basic logic gates?

Answer: There are lots of ways, but one way is the “sum of products” (SOP) method:

1) Write the sum of products expression based on the truth table for the logic function

2) Implement this expression using standard logic gates.

• An alternative way is the “product of sums” (POS) method.

Synthesis of Logic Circuits


Logic Synthesis Example: Adder

A B C S1 S0

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

S1= carry, So=sum

Truth Table of Adding Three Inputs : A, B, and C


Sum-of-products method for S1

1) Find rows where S1 is 1

2) Write down each product of inputs which create a 1 (invert logic variables that are 0 in that row)

1) Sum all of the products

2) Draw the logic circuit


A B C S1 S0

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Input Output

A B C + A B C + A B C + A B C

A B C A B C

A B C A B C



A BC

B CA

AB

A B C + A B C + A B C + A B C

SOP Logic Circuit

AB

C

C


Creating a Better Circuit

What makes a digital circuit better?• Fewer number of gates• Fewer inputs on each gate

– multi-input gates are slower

• Let’s see how we can simplify the sum-of-products expression for S1, to make a better circuit…– Use the Boolean algebra relations


Can we simplify this digital circuit further?


A BC

B CA

AB

SOP Simplification

ABCBABCA)CC(ABCBABCA

ABCCABCBABCA



Add in two inversions (signal stays the same)

A BC

B CA

AB



Apply DeMorgan’s Theorem, i.e. “bubble pushing”

A BC

B CA

AB

This becomes a NAND

XYZZYX


NAND Gate Implementation

• De Morgan’s law tells us that

is the same as

• By definition,

is the same as

All sum-of-products expressions can be implemented with only NAND gates.


Product-of-sums method for S1

1) Find rows where S1 is 0

2) Write down each sum of inputs which create a 0 (invert logic variables that are 1 in that row)

3) Product of the sums

4) Draw the logic circuit


A B C S1 S0

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Input Output

)CBA( )CBA(

)CBA( )CBA(

)CBA)(CBA)(CBA)(CBA(


SOP or POS ?

The Boolean Expression will appear shorter • If the Truth table has less 1’s, SOP• If the Truth Table has less 0’s, POS

• After Minimization, both methods should give same results , unless there are “don’t care” rows in the Truth Table.


Notations of Hambley Textbook

Row # A B C D0 0 0 0 11 0 0 1 02 0 1 0 13 0 1 1 04 1 0 0 05 1 0 1 06 1 1 0 17 1 1 1 1

Sum of Products (SOP)

)7,6,2,0(mD

Product of Sums (POS)

)5,4,3,1(MD


Another Logic Synthesis Example: XOR

A B F0 0 00 1 11 0 11 1 0

Sum of Products (SOP)

BABAF

)2,1(mF Product of Sums (POS)

)BA)(BA(F

)3,0(MF


Karnaugh Maps

2-variableKarnaugh Map

3-variableKarnaugh Map

4-variable Karnaugh Map

* Arrows show example locations of logic PRODUCTS


Comments on Karnaugh Maps• Required reading• http://www.facstaff.bucknell.edu/mastascu/

eLessonsHTML/Logic/Logic3.html

• You may find more details there than the textbook.

• As the number of variables increases (say >4) it becomes more difficult to see patterns, and computer methods start to become more attractive.

• EE40 will focus only on 3 variables and 4 variables Karnaugh Maps


Comments on Karnaugh MapsFor a 4-variables map

1-cube: 1 square by itself ( logic product of 4 variables)

2-cube: 2 squares that have a common edge

( logic product of 3 variables)

8-cube: 8 squares with common edges ( logic product of 1 variable)

4-cube: 4 squares with common edges ( logic product of 2 variables)


Comments on Karnaugh Maps• In locating cubes on a Karnaugh map, the map should be considered

to fold around from top to bottom, and from left to right.

– Squares on the right-hand side are considered to be adjacent to those on the left-hand side.

– Squares on the top of the map are considered to be adjacent to those on the bottom.

– Example:The four squares in the map corners form a 4-cube

1 1

1 1

CD00 01 11 10

AB

00011110


4-Variables Example• From Truth Table and Sum of Products F= m(1,3,4,5,7,10,12,13)• Converting the row numbers to binary yields 0001,0011, 0100 etc..• Place 1’s into the Karnaugh Map

CBDADCBAF


A B C S1 S0

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Input Output

00 01 11 100 0 0 1 01 0 1 1 1

A

BC

BC AC AB

S1 = AB + BC + AC

Simplification of expression for S1:

3-Variables Example: Adder

B

C


Miscellaneous Examples


4-Variable Exercise


Exercise with “Don’t Cares”


Sequential Logic Circuits• Sequential logic circuits that possess memory

because their present output value depends on previous as well as present input values.


Clock Signals• Often, the operation of a sequential circuit is

synchronized by a clock signal :

• The clock signal regulates when the circuits respond to new inputs, so that operations occur in proper sequence.

• Sequential circuits that are regulated by a clock signal are said to be synchronous.

time

vC(t)

VOH

0TC 2TC

positive-going edge(leading edge)

negative-going edge(trailing edge)


Flip-Flops• One of the basic building blocks for sequential

circuits is the flip-flop:– A simple flip-flop can be constructed using two

inverters:

Q

Q

Two possible states:

1Q,0Q0Q,1Q

* Circuit can remain in either state indefinitely


• Rule 1:– If S = 0 and R = 0, Q does not change.

• Rule 2: – If S = 0 and R = 1, then Q = 0

• Rule 3:– If S = 1 and R = 0, then Q = 1

• Rule 4:– S = 1 and R = 1 should never occur.

The S-R (“Set”-“Reset”) Flip-Flop

S

R

QS-R Flip-Flop Symbol:Q


Realization of the S-R Flip-Flop

S

R

Q

Q

R S Qn

0 0 Qn-1

0 1 11 0 01 1 (not allowed)


XOR and NAND Implementation


Exercise: Timing Diagram of SR flip-flop

R S Qn

0 0 Qn-1

0 1 11 0 01 1 (not allowed)

Q


Clocked S-R Flip-Flop

• When CK = 0, disables the inputs R and S• When CK = 1, enables inputs R and S


• The output terminals Q and Q behave just as in the S-R flip-flop.

• Q changes only when the clock signal CK makes a positive transition.

The D (“Delay”) Flip-Flop

D

CK

QD Flip-Flop Symbol:Q

CK D Qn

0 Qn-1

1 Qn-1

0 0 1 1


D Flip-Flop Example (Timing Diagram)

t

CK

t

D

Q

t


Registers• A register is an array of flip-flops that is used to

store or manipulate the bits of a digital word.• Example: Serial-In, Parallel-Out Shift Register using D

Flipflops

D0

CK

Q0Data input

Clock input

D1

CK

Q1 D2

CK

Q2

Q0 Q1 Q2Parallel outputs


Shift Register Timing Diagram


J-K Flip Flop


Ripple Counter


Conclusion (Logic Circuits)

• Complex combinational logic functions can be achieved simply by interconnecting NAND gates (or NOR gates).

• Logic gates can be interconnected to form flip-flops.

• Interconnections of flip-flops form registers.• A complex digital system such as a computer

consists of many gates, flip-flops, and registers. Thus, logic gates are the basic building blocks for complex digital systems.

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EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung

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