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EE415 VLSI Design
COMBINATIONAL LOGIC DYNAMICS
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
Fast Complex Gates:Design Technique 1
Transistor sizing» as long as fan-out capacitance dominates
Progressive sizing
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest)
Can reduce delay by more than 20%;
EE415 VLSI Design
Fast Complex Gates:Design Technique 2
Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
01charged
charged1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
01 charged
discharged
discharged
EE415 VLSI Design
Fast Complex Gates:Design Technique 3
Alternative logic structures
F = ABCDEFGH
EE415 VLSI Design
Fast Complex Gates:Design Technique 4
Isolating fan-in from fan-out using buffer insertion
CLCL
EE415 VLSI Design
Fast Complex Gates:Design Technique 5
Reducing the voltage swing
» linear reduction in delay» also reduces power consumption
But the following gate is much slower! Or requires use of “sense amplifiers” to
restore the signal level (memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
EE415 VLSI Design
Sizing Logic Paths for Speed
Frequently, input capacitance of a logic path is constrained
Logic also has to drive some capacitance Example: ALU load in an Intel’s
microprocessor is 0.5pF How do we size the ALU datapath to achieve
maximum speed? We have already solved this for the inverter
chain – can we generalize it for any type of logic?
EE415 VLSI Design
Buffer Example
N
iiii fgpDelay
1
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4How to generalize this to any logic path?
CL
In Out
1 2 N
(in units of inv)
EE415 VLSI Design
Logical Effort
fgp
C
CCRkDelay
in
Lunitunit
1
p – intrinsic delay (3kRunitCunit) - gate parameter f(W)g – logical effort (kRunitCunit) – gate parameter f(W)f – effective fanout
Normalize everything to an inverter:ginv =1, pinv = 1
Divide everything by inv
(everything is measured in unit delays inv)Assume = 1.
EE415 VLSI Design
Delay in a Logic Gate
Gate delay:
d = h + p
effort delay intrinsic delay
Effort delay:
h = g f
logical effort effective fanout = Cout/Cin
Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size
EE415 VLSI Design
Logical Effort
Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current
Logical effort increases with the gate complexity
EE415 VLSI Design
Intrinsic Delay
Inverter has the smallest intrinsic delay and of all static CMOS gates
Intrinsic delay of a gate presents the ratio of its output capacitance to the inverter output capacitance when sized to deliver the same current
Intrinsic delay increases with the gate complexity
EE415 VLSI Design
Logical EffortLogical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g =p= 1 g = 4/3, p=2 g = 5/3, p=2
B
A
A B
F
VDDVDD
A B
A
B
F
VDD
A
A
F
1
2 2 2
2
2
1 1
4
4
Inverter 2-input NAND 2-input NOR
EE415 VLSI Design
Logical Effort of Gates
Fan-out (f)
Nor
mal
ized
del
ay (
d)
t
1 2 3 4 5 6 7
pINV
t pNAND
F(Fan-in)
g = 1p = 1d = f+1
g = 4/3p = 2d = (4/3)f+2
h = g f
d = h+p
g – logical effortf - effective fan outp – intrinsic delay
IntrinsicDelay
EffortDelay
EE415 VLSI Design
Add Branching Effort
Branching effort: Coff-path is the branch capacitance
pathon
pathoffpathon
C
CCb
EE415 VLSI Design
Multistage Networks
Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = di = pi + hi
N
iiii fgpDelay
1
EE415 VLSI Design
Optimum Effort per Stage
HhN
When each stage bears the same effort:
N Hh
PNHpfgD Niii /1ˆ
Minimum path delay
Effective fanout of each stage: ii ghf
Stage efforts: g1f1 = g2f2 = … = gNfN
EE415 VLSI Design
Logical Effort
From Sutherland, Sproull
EE415 VLSI Design
Example – 8-input AND
Logical effortsIntrinsic delays
Fan out is not known here
g=10/3 g=1p=8 p=1
g=2 g=5/3p=4 p=2
g=4/3 g=5/3 g=4/3 g=1p=2 p=2 p=2 p=1
EE415 VLSI Design
Example: Optimize Path
1a
b c
5
g1 = 1f1 = ag2/g1
g2 = 5/3f2 = bg3/ag2
g3 = 5/3f3 = cg4/bg3
g4 = 1f 4= 5/cg4=
Effective fanout, F = 5 Path electrical effort: F = Cout/CinG = Path logical effort : G = g1g2…gNH = Path effort: H = GFBh = Stage effort: hi = gifia =b =c =
Stage fan-out is fi and a,b,c are scale factors comparing a gate size to the minimum size gate with the same speed as inverter
Output loadInput load
EE415 VLSI Design
Example: Optimize Path
1a
b c
5
g1 = 1f1 = ag2/g1
g2 = 5/3f2 = bg3/ag2
g3 = 5/3f3 = cg4/bg3
g4 = 1f 4= 5/cg4
Effective fanout, F = 5G = 25/9H = 125/9 = 13.9 (since no branching here then B=1, H=GFB)h = 1.93 (this is the optimum effort for each gate h=H1/4)a = h/g2=1.16 (from h=f1g1=1.93 and f1=ag2/g1)b = ha/g3 = 1.34 (same as h=f2g2=1.93 and f2= bg3/ag2)c = hb/g4 = 2.59 (same as h=f3g3=1.93 and f3=cg4/bg3)
Stage fan-out is fi and a,b,c are scale factors comparing a gate size to the minimum size gate with the same speed as inverter
EE415 VLSI Design
Method of Logical Effort
Compute the path effort: H = GBF Find the best number of stages N ~ log4H Compute the stage effort h= H1/N
Sketch the path with this number of stages Work from either end, find sizes:
Cin = Cout*g/h
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
EE415 VLSI Design
Ratio Based Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
EE415 VLSI Design
Ratio Based Logic
VDD
VSS
PDN
In1
In2
In3
F
RLLoad
ResistiveN transistors + Load
• VOH = VDD
• VOL = RDN
RDN + RL
• Asymmetrical response
• Static power consumption
•
• tpLH= 0.69 RL
CL
VDD
LPDNLpHL CRRt ||69.0
EE415 VLSI Design
Ratio Based Logic Problems
Problems with Resistive Load
•IL = (VDD – Vout )/ RL
•Charging current drops rapidly once Vout
starts to rise
Solution: Use a current source!
•Available current is independent of voltage
•Reduces tpLH by 25%
EE415 VLSI Design
Active Loads
VDD
VSS
In1In2In3
F
VDD
VSS
PDN
In1In2In3
F
VSS
PDN
Depletion
LoadPMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
EE415 VLSI Design
Active Loads
Depletion mode NMOS load
•VGS = 0
•IL ~ (kn, load / 2) (|VTn|)2
•Deviates from ideal current source
•Channel length modulation
•Body effect
•VSB varies with Vout
•reduces |VTn|, hence IL gets smaller for increasing Vout
EE415 VLSI Design
Active Loads
Pseudo-NMOS load
•No body effect, VSB = 0V
•VGS = - VDD , higher load current
•IL = (kp / 2) (VDD - |VTn|)2
•Larger VGS causes pseudo-NMOS load to leave
saturation mode sooner than NMOS
EE415 VLSI Design
Load Lines of Ratioed Gates
0.0 1.0 2.0 3.0 4.0 5.0Vout (V)
0
0.25
0.5
0.75
1
I L(N
orm
aliz
ed)
Resistive load
Pseudo-NMOS
Depletion load
Current source
EE415 VLSI Design
Pseudo-NMOS
VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn– VOL
VOL2
2-------------–
kp
2------ VDD VTp– 2=
VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
EE415 VLSI Design
Pseudo-NMOS VTC
Noise margin low is significantlyreduced comparing to CMOS
0.0 0.5 1.0 1.5 2.0 2.50.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin [V]
Vou
t [V
]
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = 0.25
W/Lp = 0.5
NL
Vin_low
Vin_highVin_low
EE415 VLSI Design
Pseudo-NMOS NAND Gate
VDD
GND
Out
EE415 VLSI Design
Improved Loads (1)
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
For fast low-to-high transition in standby circuits
EE415 VLSI Design
Improved Loads (2)
•Differential Cascode Voltage Switch Logic (DCVSL)•Have no static current•Requires that each gate generates both Out and its complement
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
EE415 VLSI Design
DCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate
EE415 VLSI Design
DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0-0.5
0.5
1.5
2.5
Time [ns]
Vol
tage
[V] A B
A B
A,BA,B
DCVSL transient response of AND/NAND gate
EE415 VLSI Design
Pass-Transistor LogicIn
puts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumption
EE415 VLSI Design
Example: AND Gate
B
B
A
F = AB
0
EE415 VLSI Design
NMOS-Only Logic
VDD
In
Outx
0.5m/0.25m0.5m/0.25m
1.5m/0.25m
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time [ns]
Vo
ltage
[V]
xOut
In
EE415 VLSI Design
NMOS-only Switch
A = 2.5 V
B
C = 2.5 V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 2.5V, but 2.5V - VTN
NMOS has higher threshold than PMOS (body effect)
EE415 VLSI Design
Pass-Transistor Logic- Solution 1: Level Restoring Transistor
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
weak transistor
X
• Advantages: Full Swing, No static power dissipation
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
EE415 VLSI Design
Restorer Transistor Sizing
0 100 200 300 400 5000.0
1.0
2.0
W/ Lr =1.0/0.25 W /L
r =1.25/0.25
W /Lr =1.50/0.25
W /Lr =1.75/0.25
Vo
lta
ge
[V]
Time [ps]
3.0•Level restoring transistor cannot be too strong otherwise it will prevent output from reaching VDD value•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stack
EE415 VLSI Design
Pass-Transistor Logic - Solution 2: Single Transistor Pass Gate with
VT=0
Out
VDD
VDD
2.5V
VDD
0V 2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
If pass transistors have VT=0 the outputdoes not require level restorer but there is a leakagecurrent
EE415 VLSI Design
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=AÝ
F=AÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
EE415 VLSI Design
Pass-Transistor Logic Solution 3: Transmission Gate
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5 V
C = 2.5 V
EE415 VLSI Design
Resistance of Transmission Gate
Vout
0 V
2.5 V
2.5 VRn
Rp
0.0 1.0 2.00
10
20
30
Vout, V
Res
ista
nce
, oh
ms
Rn
Rp
Rn || Rp
EE415 VLSI Design
Transmission Gate Based Multiplexer
AM2
M1
B
S
S
S F
VDD
GND
VDD
In1
In2
S S
S S
EE415 VLSI Design
Transmission Gate Based XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
EE415 VLSI Design
Transmission Gate Full Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
Similar delays for sum and carry24 transistors
Propagate signal
EE415 VLSI Design
Example: Full Adder
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
Co = AB + Ci(A+B)
28 transistors
EE415 VLSI Design
A Revised Adder Circuit
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
EE415 VLSI Design
Delay in Transmission Gate Networks
V1 Vi-1
C
2.5 2.5
0 0
Vi Vi+1
CC
2.5
0
Vn-1 Vn
CC
2.5
0
In
V1 Vi Vi+1
C
Vn-1 Vn
CC
In
ReqReq Req Req
CC
(a)
(b)
C
Req Req
C C
Req
C C
Req Req
C C
Req
C
In
m
(c)
EE415 VLSI Design
Delay Optimization