EE42/100, Spring 2006Week 14a, Prof. White1 Week 14a Propagation delay of logic gates CMOS...

EE42/100, Spring 2006 Week 14a, Prof. White 1

Week 14a

Propagation delay of logic gates

CMOS (complementary MOS) logic gates

Pull-down and pull-up

The basic CMOS inverter

Current flow and power dissipation in CMOS circuits

Equation for power dissipated in N logic circuits clocked at frequency f


WHAT IS THE ORIGIN OF GATE DELAY?Logic gates are electronic circuits that process electrical signals

Most common signal for logic variable: voltage

Note that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with succeeding logic generations

Specific voltage ranges correspond to “0” or “1”

Thus delay in voltage rise or fall (because of delay in charging

internal capacitances) will translate to a delay in signal timing

3

2

1

0

Volts

Range “0”

Range “1”

“Gray area” . . . not allowed


INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS)

Inverter input is vIN(t), output is vOUT(t)

Inverter inside a large system

)t(v IN )t(vOUT

t

Vin(t)


Approximation

D

GATE DELAY (PROPAGATION DELAY)

Define as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V.Inverters are designed so that the gate delay is symmetrical (rise and fall)

Vin(t)

t

1.5

Vout(t)

t

1.5

D D


EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED

Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations

Implication: if clock frequency = 500 MHz clock period = (5108 s1)1

Period = 2 10 9s = 2 ns (nanoseconds)

Gate delay must be D = (1/35) Period = (2 ns)/35 = 57 ps (picoseconds)

How fast is this? Speed of light: c = 3 108 m/s

Distance traveled in 57 ps is:

c X D = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cm


WHAT DETERMINES GATE DELAY?

)t(v IN )t(vOUT

The delay is mostly simply the charging of the capacitors at internal nodes.

Logic gates consist of just “CMOS” transistor circuits (CMOS =complementary metal-oxide-semiconductor = NMOS and PMOS FETs together).Let’s recall the FET


Modern Field Effect Transistor (FET)

• An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying “gate” electrode), to modulate the conductance of the semiconductor

Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode

N-channel metal-oxide- semiconductor field-effect transistor (NMOSFET)


Pull-Down and Pull-Up Devices• In CMOS logic gates, NMOSFETs are used to connect

the output to GND, whereas PMOSFETs are used to connect the output to VDD.– An NMOSFET functions as a pull-down device when it is

turned on (gate voltage = VDD)– A PMOSFET functions as a pull-up device when it is

turned on (gate voltage = GND)

F(A1, A2, …, AN)

PMOSFETs only

NMOSFETs only…

…

Pull-upnetwork

Pull-downnetwork

VDD

A1

A2

AN

A1

A2

AN

input signals


Controlled Switch Model

Now lets combine these switches to make an inverter.

-

Type N controlled switch” means switch is closed if input is high. (VG > VS)

Type P controlled switch” means switch is closed if input is low. (VG < VS)

Output

S

Input

RP

-

++

-

+

-G

Input

OutputRN +

+

-

+

-G

S


The CMOS Inverter: Current Flow during Switching

VIN

VOUT

VDD

VDD00

N: offP: lin

N: linP: off

N: linP: sat

N: satP: lin

N: satP: sat

A B D E

C

ii

i

S

D

G

GS

D

VDD

VOUTVIN


CMOS Inverter Power Dissipation due to Direct-Path Current

VDD-VT

VT

time

vIN:

i:

Ipeak

VDD

0

0

i

S

D

G

GS

D

VDD

vOUTvIN

peakDDscdp IVtE Energy consumed per switching period:

tscNote: once the CMOS circuit reaches a steady state there’s no more current flow and hence no more power dissipation!


Controlled Switch Model of Inverter

So if VIN is 2V then SN is closed and SP is open. Hence VOUT is zero.

Input OutputRN

-

+

SP is closed if VIN < VDD

RP

-

+

+

-

+

-

VDD = 2V

VSS = 0V

SN

SP

SN is closed if VIN > VSS

VIN VOUT

But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V.


Controlled Switch Model of Inverter

IF VIN is 2V then SN is closed and SP is open. Hence VOUT is zero (but driven through resistance RN).

RN

+

--

VDD = 2V

VSS = 0V

VIN =2V

VOUT

But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V (but driven through resistance RP).

+

--

VDD = 2V

VSS = 0V

VIN =0V RP

VOUT


VIN jumps from 0V to 2V

Controlled Switch Model of Inverter – load capacitor charging and discharging takes time

IF there is a capacitance at the output node (there always is) then VOUT responds to a change in VIN with our usual exponential form.

VOUT

t

VIN jumps from 2V to 0V

RN

+

--

VDD = 2V

VSS = 0V

VIN =2V

VOUT

+

--

VDD = 2V

VSS = 0V

VIN =0V RP

VOUT


Model the MOSFET in the ON state as a resistive switch:

Case 1: Vout changing from High to Low

(input signal changed from Low to High)

NMOSFET(s) connect Vout to GND

tpHL= 0.69RnCL

Calculating the Propagation Delay

VDD

Pull-down network is modeled as a resistor

Pull-up network is modeled as an open switch

CL

+

vOUT

vIN = VDD

Rn


Calculating the Propagation Delay (cont’d)

Case 2: Vout changing from Low to High

(input signal changed from High to Low)

PMOSFET(s) connect Vout to VDD

tpLH = 0.69RpCLVDD

Rp

Pull-down network is modeled as an open switch

Pull-up network is modeled as a resistor

CL

+

vOUT

vIN = 0 V


Output Capacitance of a Logic Gate

• The output capacitance of a logic gate is comprised of several components:

• pn-junction and gate-drain capacitance– both NMOS and PMOS transistors

• capacitance of connecting wires• input capacitances of the fan-out gates

“extrinsiccapacitance”

“intrinsiccapacitance”


Reminder: Fan-Out• Typically, the output of a logic gate is connected

to the input(s) of one or more logic gates• The fan-out is the number of gates that are

connected to the output of the driving gate:

•••

fan-out =N

driving gate

1

2

N

• Fanout leads to increased capacitive load on the driving gate, and therefore more propagation delay

– The input capacitances of the driven gates sum, and must be charged through the equivalent resistance of the driver


Minimizing Propagation Delay

• A fast gate is built by

1. Keeping the output capacitance CL small– Minimize the area of drain pn junctions.– Lay out devices to minimize interconnect

capacitance.– Avoid large fan-out.

2. Decreasing the equivalent resistance of the transistors– Decrease L (gate length source to drain)– Increase W (other dimension of gate)

… but this increases pn junction area and hence CL

3. Increasing VDD

→ trade-off with power consumption & reliability


• A GATE electrode is placed above (electrically insulated from) the silicon surface, and is used to control the resistance between the SOURCE and DRAIN regions

• NMOS: N-channel Metal Oxide Semiconductor

np-type silicon

oxide insulator n

L

• L = channel length

“Metal” (heavily doped poly-Si)

W• W = channel width

MOSFET

SOURCE

DRAIN

GATE


Transistor Sizing for Performance

• Widening the transistors reduces resistance – current paths in parallel -- but increases gate capacitance

• In order to have the on-state resistance of the PMOS transistor match that of the NMOS transistor (e.g. to achieve a symmetric voltage transfer curve), its W/L ratio must be larger by a factor of ~3 (because holes move about 3 times slower than electrons in a given electric field).

VDD

VIN VOUT

S

D

G

GS

D


Other CMOS logic examples


CMOS NAND GateA B F0 0 10 1 11 0 11 1 0

A

F

B

A B

VDD


CMOS NOR Gate

A

F

B

A

B

VDD A B F0 0 10 1 01 0 01 1 0


Column Drivers and Sense Amplifiers

Column AddressDecoder/Selector

Row

Add

ress

Dec

oder

+Vdd

Word Line

Bit

Line

Bit

Line

Figure 0.1 SRAM circuit diagram and cell schematic

Static Random-Access Memory (SRAM) with CMOS Circuit in each cell


Power consumption in CMOS circuits


ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEW

Capacitor initially uncharged (Q=CVDD at end)

Switch moves @ t=0

Energy out of "battery"

DDV)t(iP

2DD

DD0

DD

CV

QVdtiVE

This must be difference

of E and EC, i.e.

2DDCV

21

CASE 1-Charging

iVDD

t=0R

CRD

R)t(iP 2R

Energy into R (heat)

Power out of "battery" Power into RPower into C

)t(V)t(iP CC

0CC dtiVE

2DDCV

21

Energy into C


ENERGY AND POWER IN CHARGING

Capacitor initially uncharged (Q=CVDD at end)

Switch moves @ t=0

Energy out of "battery"

2DDCV 2

DDCV21

Energy into R (heat)

2DDCV

21

Energy into C

VDD

t=0R

CRD

In charging a capacitor from a fixed voltage source VDD half the energy from the source is delivered to the capacitor, and

half is lost to the charging resistance, independent of the value of R.


ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS

Capacitor initially charged (Q=CVDD) and discharges.

Switch moves @ t=0

Energy out of battery

This must be energy initially in C, i.e.

2DDCV

21

CASE 2-discharging

iVDD

t=0R

CRD

R)t(iP 2R

Energy into RD (heat)

Power out of battery Power into RDPower out of C

)t(V)t(iP CC

0CC dtiVE

2DDCV

21

Energy out of C

=0

=0

Power in/out of R

=0


ENERGY IN DISCHARGING CAPACITORS

Capacitor initially charged (Q=CVDD) and discharges.

Switch moves @ t=0

2DDCV

21

VDD

t=0R

CRD

Energy into RD (heat)

2DDCV

21

Energy out of C

When a capacitor is discharged into a resistor the energy originally stored in the capacitor (1/2 CVDD

2) is dissipated as heat in the resistor


CMOS Power Consumption• The total power consumed by a CMOS circuit is

comprised of several components:

1. Dynamic power consumption due to charging and discharging capacitances*:

f01 = frequency of 01 transitions (“switching activity”)

f = clock rate (maximum possible event rate)

Effective capacitance CEFF = average capacitance charged every

clock cycle

* This is typically by far the dominant component!

fVCfVCP DDEFFDDLdyn2

102

Other components of power dissipation are direct current flow during part ofthe CMOS switching cycle and leakage in the transistor junctions.


Each node transition (i.e. charging or discharging) results in a loss of (1/2)(C)(VDD

2) How many transitions occur per second? Well if the node is pulsed up then down at a frequency f (like a clock frequency)

then we have 2f dissipation events.

POWER DISSIPATION in DIGITAL CIRCUITS

A system of N nodes being pulsed at a frequency f to a signal voltage VDD will dissipate energy equal to (N) (2f )(½CVDD

2) each second

Therefore the average power dissipation is (N) (f )(CVDD2)


LOGIC POWER DISSIPATION EXAMPLE

Power = (Number of gates) x (Energy per cycle) x (frequency)

N = 107; VDD = 2 V; node capacitance = 10 fF; f = 109 s-1 (1GHz)

P = 400 W! -- a toaster!

Pretty high but realistic

What to do? (N increases, f increases, hmm) 1) Lower VDD

2) Turn off the clock to the inactive nodes

Clever architecture and design!

Let’s define as the fraction of nodes that are clocked (active). Then we have a new formula for power.

P = (N) (CVDD2) (f )


LOGIC POWER DISSIPATION with power mitigation

Power = (Energy per transition) x (Number of gates) x (frequency) x fraction of gates that are active ().

In the last 5 years VDD has been lowered from 5V to about 1.5V. It cannot go very much lower. But with clever design, we can make as low as 1 or 10%. That is we do not clock those parts of the chip where there is no computation being made at the moment.

Thus the 400W example becomes 4 to 40W, a manageable range (4W with heat sink, 40W with heat sink plus fan on the chip).

P = N CVDD2 f


Low-Power Design Techniques

1. Reduce VDD

→ quadratic effect on Pdyn

Example: Reducing VDD from 2.5 V to 1.25 V reduces power dissipation by factor of 4

– Lower bound is set by VT: VDD should be >2VT

2. Reduce load capacitance→ Use minimum-sized transistors whenever possible

3. Reduce the switching activity– involves design considerations at the architecture

level (beyond the scope of this class!)

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EE42/100, Spring 2006Week 14a, Prof. White1 Week 14a Propagation delay of logic gates CMOS...

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