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Beginning of Presentation IIT Bombay VLSI Technology (EE 669) CDEEP Autumn 2010 Prof. V. Ramgopal Rao
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Beginning of Presentation IIT Bombay
VLSI Technology (EE 669)
CDEEP
Autumn 2010 Prof. V. Ramgopal Rao
OVERVIEW
• Environment for VLSI Technology • Impurity Incorporation • Oxidation • Lithography • CVD Techniques • Metal Film Deposition • Plasma and Rapid Thermal Processing • Process Integration
Slide 2 IIT Bombay
Autumn 2010 Prof. V. Ramgopal Rao
IIT Bombay IIT Bombay
PRE-REQUISITES
Bachelors degree in any branch of engineering
Slide 3
Autumn 2010 Prof. V. Ramgopal Rao
IIT Bombay
REFERENCES
Slide 4
Autumn 2010 Prof. V. Ramgopal Rao
1. James D.Plummer, Michael D.Deal, Peter B.Griffin, Silicon VLSI Technology:
Fundamentals, Practice & Modeling, Prentice Hall.
2. The Sc ience and Eng ineer ing o f Microelectronic Fabrication, Stephen A. Campbell, Oxford University Press.
3. C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc, 1996.
IIT Bombay
REFERENCES
Slide 5
Autumn 2010 Prof. V. Ramgopal Rao
1.S.M. Sze (Ed), VLSI Technology, 2nd Edition,McGraw Hill, 1988.
2.Research Papers.
IIT Bombay
VLSI Technology
Course Code : EE 669
Department : Electrical Engg.
Instructor : Prof. V. Ramgopal Rao
E-Mail ID/ Website : [email protected]
www.ee.iitb.ac.in/~rrao/
Slide 6
Autumn 2010 Prof. V. Ramgopal Rao
IIT Bombay
Module #1
Sub-Topics:
•World Semiconductor Industry
• MOS Transistor Basics
• Technology Scaling
• IC Fabrication Overview
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 7
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 8
World Semiconductor Industry
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 9
G.Moore, Intel
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 10
MOS Transistors-Enhancement Mode
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 11
MOS Transistor - Saturation
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 12
I-V Characteristics
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 13
Short-Channel Effects
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 14
Inverter
(a) Multiplexer System
(b) Addressable array (Memory or Display)
Applications of Transistors
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 15
Applications of Transistors
Amplifier Oscillator
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 16
Impedance
Transformation Variable attenuator Variable phase
shifter
Applications of Transistors
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 17
MOS Capacitors • “Metal” : metal, or
more frequently heavily doped poly-
Si
• “Oxide” : silicon dioxide, or some
other high k dielectric
• “Semiconductor” :
Si , but can also be SiGe, SiC
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 18
Basic MOS Structure
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 19
MOSFET Operation – Linear Region
VDS < VGS-VT
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 20
MOSFET Operation – Saturation
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 21
NMOS Transistor Equations
Linear Region:
Saturation Region: For VDS > VGS-VT
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 22
MOS Transistor Output Characteristics
( S. M. Sze, Physics of Semiconductor Devices, John Wiley ,1981)
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 23
MOS Transistor Subthreshold Characteristics
Subthreshold Swing:
60 – 100 mV/decade
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 24
MOS Transistor Subthreshold Characteristics
Subthreshold Swing:
60 – 100 mV/decade
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 25
Scaling W=0.7, L=0.7, Tox=0.7
L a t e r a l a n d v e r t i c a l dimensions reduce 30 %
Area Cap = C = (0.7 X 0.7)/0.7 = 0.7
Capacitance reduces by 30 %
Die Area = X x Y = 0.7x0.7 = 0.72 => Die area reduces by 50 %
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 26
Scaling Vdd=0.7, Vt=0.7, T ox=0.7,
= 0.7
T= (C x Vdd )/I = 0.7, Power = CV2f = 0.7 x 0.72
0.7 = 0.72
=> Delay reduces by 30 % and Power reduces by 50 %
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 27
Exercise
Assuming a constant scaling factor of 0.5 for various critical MOSFET parameters, calculate the performance improvement in terms of package density, power and speed for an ideal CMOS process as one scales the technologies from one generation to the next. Compare the results for the case where the scaling factor is 0.7.
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 28
With a scaling factor of 0.5, the package density increases by 4X, Capacitance decreases by a factor: 0.5 (50% reduction) , Drive current I decreases by 0.5 (50% reduction), Delay decreases by 0.5 (or 50% ), Dynamic power: CV2f = 0.25 (decreases by 4 times)
Solution
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 29
IC Fabrication
•Clean Room •Wafer Cleaning Technology •Oxidation •Lithography •Etching •Epitaxy •Dielectric and Polysil icon Film Deposition
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 30
IC Fabrication…
•Diffusion and Ion Implantation Processes •Conventional and Rapid Thermal Annealing •Metallization •Planarization Techniques -Chemical-Mechanical Polishing (CMP) •Salicidation •Process Integration
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 31
Vt Control MOSFET –poly gate process
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 32
Fabrication-NMOSFET (1)
(2)
(3)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 33
Fabrication-NMOSFET…
(4)
(5)
(6)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 34
Fabrication-NMOSFET (cont’d) (7)
(8)
(9)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 35
Fabrication-NMOSFET (cont’d)
(10)
(11)
IIT Bombay
VLSI Technology Module No.1 Prof. V. Ramgopal Rao
Slide 36
(Stephen A. Campbell, “The science and engineering of microelectronic fabrication,” Oxford Univ. Press.)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 37
(Stephen A. Campbell, “The science and engineering of microelectronic fabrication,” Oxford Univ. Press.)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 38
(Stephen A. Campbell, “The science and engineering of microelectronic fabrication,” Oxford Univ. Press.)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 39
(Stephen A. Campbell, “The science and engineering of microelectronic fabrication,” Oxford Univ. Press.)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 40
NMOS Inverter with Depletion Load
Inverter in IC form
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 41
Fabrication-NMOS inverter
Bird’s beak,
limitation in LOCOS
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 42
Fabrication-NMOS inverter…
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 43
Inverter Fabrication (Cont’d)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 44
Inverter Fabrication (Cont’d)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 45
Inverter Fabrication (Cont’d)
IIT Bombay
VLSI Technology Module No. 1 Prof. V. Ramgopal Rao
Slide 46
Process Integration - Exercise
