EECE488: Analog CMOS Integrated Circuit Design
Set 7
Opamp Design
1SMEECE488 Set 7 - Opamp Design
Opamp DesignReferences: “Analog Integrated Circuit Design” by D. Johns and K. Martin
and “Design of Analog CMOS Integrated Circuits” by B. Razavi
All figures in this set of slides are taken from the above books
Shahriar MirabbasiDepartment of Electrical and Computer Engineering
University of British [email protected]
General Considerations
• Gain• Small-signal bandwidth• Large-signal performance• Output swing• Input common-mode range• Linearity
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• Noise/offset• Supply rejection
One-Stage Op Amps
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One-Stage Op Amp in Unity Gain Configuration
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Cascode Op Amps
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Unity Gain One Stage Cascode
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Folded Cascode Op Amps
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Folded Cascode Stages
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Folded Cascode (cont.)
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Folded Cascode (cont.)
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| Av |≈ gm1{[( gm 3 + gmb3)ro3(ro1 ||ro5)] ||[( gm7 + gmb 7)ro7ro9 ]}
Telescopic versus Folded Cascode
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Example Folded-Cascode Op Amp
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Single-Ended Output Cascode Op Amps
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Triple Cascode
Av app. (gmro)3/2
Limited Output Swing
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Limited Output Swing
Complex biasing
Output Impedance Enhancement
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1221 oomout rrgAR =
Gain Boosting in Cascode Stage
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Differential Gain Boosting
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Differential Gain Boosting
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Differential Gain Boosting
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Two-Stage Op Amps
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Single-Ended Output Two-Stage Op Amp
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Two-Stage CMOS Opamp
• Popular opamp design approach• A good example to review many important design concepts• Output buffer is typically used to drive resistive loads• For capacitive loads (typical case in CMOS) buffer is not
required.
Cc
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A1 –A2 1
Differentialinput stage
Secondgain stage
Outputbuffer
VoutVin
Cc
Two-Stage CMOS Opamp Example
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Gain of the Opamp
• First Stage
Differential to single-ended
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• Second Stage
Common-source stage
• Output buffer is not required when driving capacitive loads
Gain of the Opamp
Third Stage
• Source follower
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• Typical gain: between 0.7 to1• Note: go=1/ro and GL=1/RL
• gmb is body-effect conductance (is zero if source can be tied tosubstrate)
Frequency Response
Q5
Q2Q1
300
300300vin–
vin+
Vbias
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Q3 Q4
150
150–A2 A3 vout
CCv1
i = gm1 vin
v2
Ceq CC 1 A2+( )=
A3 1≅
Frequency Response
Simplifying assumptions:• CC dominates• Ignore Q16 for the time being (it is used for lead compensation)
Miller effect results in
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• At midband frequencies
Frequency Response
• Overall gain (assuming A3 ≈1)
which results in a unity-gain frequency of
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• Note: ωta is directly proportional to gm1 and inverselyproportional to CC.
Frequency Response
• First-order model
20 A1A2( )log
Gain
(dB)
0 Freq
ω ta gm1 CC⁄≅
20– dB/decade
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0 Freq
ωta
Phase
(degrees)
0 Freqωta
180–
90–
ωp1
ωp1
(log)
(log)
Slew Rate
• Maximum rate of output change when input signal is large.Q5
Q2Q1
300
300300vin–
vin+
Vbias
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• All the bias current of Q5 goes either into Q1 or Q2.Q3 Q4
150
150
in–
–A2 A3 vout
CCv1
i = gm1 vin
v2
A3 1≅
Slew Rate
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Slew Rate
• Normally, the designer has not much control over ωta
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• Slew-rate can be increased by increasing Veff1
• This is one of the reasons for using p-channel input stage:higher slew-rate
Systematic Offset Voltage
• To ensure inherent (systematic) offset voltage does not exist,nominal current through Q7 should equal to that of Q6 when thedifferential input is zero.
Q5 Q6VDD300
300Ibias
Vbias
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Q3 Q4
Q2Q1
Q7
300300
150 150
300
Vin– Vin+
Vout
VSS
Systematic Offset Voltage
• Avoid systematic offset by choosing:
• Found by noting
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and
then setting
N-Channel versus P-Channel Input Stage
• Complimentary opamp can be designed with an n-channel inputdifferential pair and p-channel second-stage
• Overall gain would be roughly the same in both designsP-channel Advantages• Higher slew-rate: for fixed bias current, Veff is larger (assuming
similar widths used for maximum gain)• Higher frequency of operation: higher transconductance of
second stage which results in higher unity-gain frequency
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second stage which results in higher unity-gain frequency• Lower 1/f noise: holes less likely to be trapped; p-channel
transistors have lower 1/f noise• N-channel source follower is preferable (less voltage drop and
higher gm)N-channel Advantage• Lower thermal noise — thermal noise is lowered by high
transconductance of first stage
Feedback and Opamp Compensation
)(1
)()(
sH
sHs
X
Y
β+=
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• Feedback systems may oscillate
• The following two are the oscillation conditions:
180)(
1|)(|
−=∠=
ωβωβ
jH
jH
Stable and Unstable Systems
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Time-domain response of a feedback system
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One-pole system
0
0
1)(
ωs
AsH
+=
0
1 A
A
Y β+
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Bode plot of the Loop gain
( )00
0
11
1)(
A
sA
sX
Y
βω
β
++
+=
( )00 1 AS p βω +−=
Multi-pole system
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Bode plot of the Loop gain
12 101.0 pp ωω >
Phase Margin
20 LG jω( )( )log
Loop Gain
(dB)
0ωt
-20 dB/decade
ωp1
Freq(log)
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Phase
(degrees)
0Freq
ωt
180–
90–
ωp1
(log)Loop Gain
PM
GM(gain margin)
(phase margin)
Phase Margin
1751 1 je)(H −×=ωβ
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Closed loop frequency response
β5.11
)( =sX
Y
Phase Margin (Cont.)
)(HPM GXωβ∠+=180
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Phase Margin = 45°
Phase Margin (Cont.)
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Phase Margin = 45°
Phase Margin (Cont.)
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• At PM = 60o results in a small overshoot in the step response.• If we increase PM, the system will be more stable but the time
response slows down.
Frequency Compensation
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• Push phase crossing point out• Push gain crossing point in
Telescopic Opamp (single-ended) -example
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Compensation (Cont.)
• Assume we need a phase margin of 45 o (usually inadequate) and other non-dominant poles are at hig h frequency.
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Compensation of a two-stage opamp
Miller Effect Ceq = CE + (1+ Av2)CC
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Miller Effect Ceq = CE + (1+ Av2)CC
f pE = 1
2πRout[CE + (1+ Av2)CC ]
Compensating Two-Stage Opamps
Q5
Q2Q1
Q6VDD300
300300
300
Vin-Vin+ Vout2
Vbias1
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Q3 Q4 Q7
150 150300
in-
CcQ16
Vbias2
Compensating Two-Stage Opamps
gm1vin
gm7v1
v1
R1 C1
RC CC
R2 C2
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• Q16 has VDS16 = 0 therefore it is hard in the triode region.
• Small signal analysis: without RC, a right-half plane zero occursand worsens the phase-margin.
Compensating Two-Stage Opamps
• Using RC (through Q16) places zero at
• Zero moved to left-half plane to aid compensation• Good practical choice is
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• satisfied by letting
Design Procedure
Design example: Find CC with RC=0 for a 55o phase margin– Arbitrarily choose C’C=1pF and set RC=0
– Using SPICE, find frequency ωt where a –125° phase shiftexists, define gain as A’
– Choose new C so ω becomes unity-gain frequency of the
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– Choose new CC so ωt becomes unity-gain frequency of theloop gain, resulting in a 55o phase margin.
Achieved by setting CC=CCA’
– Might need to iterate on CC a couple of times using SPICE
Design Procedure
Next: Choose RC according to
– Increasing ωt by about 20 percent, leaves zero near final ωt
– Check that gain continues to decrease at frequencies above thenew ω
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new ωt
Next: If phase margin is not adequate, increase CC while leavingRC constant.
Design Procedure
Next: Replace RC by a transistor
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SPICE can be used for iteration to fine-tune the devicedimensions and optimize the phase margin.
Process and Temperature Independence
• Can show non-dominant pole is roughly given by
• Recall zero given by
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• If RC tracks inverse of gm7 then zero will track ωp2:
Process and Temperature Independence
• Need to ensure Veff16/Veff7 is independent of process andtemperature variations
Q11
Q12
Q625
25
300Vbias
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• First set Veff13=Veff7 which makes Va=Vb
Q13
CC
25
25
300
Q16Va
VbQ7
Vb
Process and Temperature Independence
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Stable Transconductance Biasing
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Stable Transconductance Biasing
• Transconductance of Q13 (to the first order) is determined bygeometric ratios only.
• Independent of power-supply voltages, process parameters,temperature, etc.
• For special case (W/L)15=4(W/L)13
g =1/R
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gm13=1/RB
• Note that high-temperature will decrease mobility and henceincrease effective gate-source voltages.
• Roughly 25% increase for 100 degree increase• Requires a start-up circuit (might have all 0 currents)