9/21/04 EECS150 F04 Culler 1
EECS 150 - Components and Design Techniques for Digital Systems
Lec 07 – PLAs and FSMs9/21-04
David CullerElectrical Engineering and Computer Sciences
University of California, Berkeley
http://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150
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Review: minimum sum-of-products expression from a Karnaugh map
• Step 1: choose an element of the ON-set
• Step 2: find "maximal" groupings of 1s and Xs adjacent to that element
– consider top/bottom row, left/right column, and corner adjacencies
– this forms prime implicants (number of elements always a power of 2)
• Repeat Steps 1 and 2 to find all prime implicants
• Step 3: revisit the 1s in the K-map– if covered by single prime implicant, it is essential, and participates in final
cover
– 1s covered by essential prime implicant do not need to be revisited
• Step 4: if there remain 1s not covered by essential prime implicants
– select the smallest number of prime implicants that cover the remaining 1s
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Big Idea: boolean functions <> gates
• 22^n boolean functions of n inputs– Each represented uniquely by a Truth Table
– Describes the mapping of inputs to outputs
• Each boolean function represented by many boolean expressions
– Axioms establish equivalence
– Transform expressions to optimize
• Each boolean expression has many implementations in logic gates
– Canonical: Sum of Products, Product of Sums
– Minimal
– K-maps as a systematic means of reducing Sum of Products
• Any acyclic network of gates implements a boolean function
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Outline
• Programmable Logic to Implement Sum of Products
• Designing with PLAs
• Announcements
• FSM Concept
• Example: history sensitive computation
• Example: Combo lock
• Encodings and implementations
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How to quickly implement SofPs?
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One Answer: Xilinx 4000 CLB
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Two 4-input functions, registered output
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5-input function, combinational output
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Programmable Logic
• Regular logic– Programmable Logic Arrays
– Multiplexers/Decoders
– ROMs
• Field Programmable Gate Arrays (FPGAs)– Xilinx
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• • •
inputs
ANDarray
• • •
outputs
ORarrayproduct
terms
Programmable Logic Arrays (PLAs)
• Pre-fabricated building block of many AND/OR gates
– Actually NOR or NAND
– ”Personalized" by making or breaking connections among gates
– Programmable array block diagram for sum of products form
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example:
F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
personality matrix 1 = uncomplemented in term0 = complemented in term– = does not participate
1 = term connected to output0 = no connection to output
input side:
output side:
product inputs outputsterm A B C F0 F1 F2 F3
AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1
reuse of terms
Shared Product Terms
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Before Programming
• All possible connections available before "programming"– In reality, all AND and OR gates are NANDs
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A B C
F1 F2 F3F0
AB
B'C
AC'
B'C'
A
After Programming
• Unwanted connections are "blown"– Fuse (normally connected, break unwanted ones)
– Anti-fuse (normally disconnected, make wanted connections)
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notation for implementingF0 = A B + A' B'F1 = C D' + C' D
AB+A'B'CD'+C'D
AB
A'B'
CD'
C'D
A B C D
Alternate Representation for High Fan-in Structures
• Short-hand notation--don't have to draw all the wires
– Signifies a connection is present and perpendicular signal is an input to gate
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A B C F1 F2 F3 F4 F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
A B C
F1 F2 F3 F4 F5F6
full decoder as for memory address
bits stored in memory
Programmable Logic Array Example
• Multiple functions of A, B, C– F1 = A B C
– F2 = A + B + C
– F3 = A' B' C'
– F4 = A' + B' + C'
– F5 = A xor B xor C
– F6 = A xnor B xnor C
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLAs Design Example
• BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
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not a particularly goodcandidate for PLA
implementation since no terms are shared among outputs
however, much more compact and regular implementation
when compared with discrete AND and OR gates
A B C D
W X Y Z
A
BD
BC
BC'
B
C
A'B'C'D
BCD
AD'
BCD'
minimized functions:
W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
PLAs Design Example (cont’d)
• Code converter: programmed PLA
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W =X = Y = Z =
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLAs Design Example (revisited)
• BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
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0 1 X 0
0 1 X 0
0 0 X X
0 0 X X
D
A
B
C
minimized functions:
W =X = Y = Z =
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
0 0 X 1
0 1 X 1
0 1 X X
0 1 X X
D
A
B
C
K-map for W K-map for X
0 1 X 0
0 1 X 0
1 1 X X
1 1 X X
D
A
B
C
K-map for Y
PLAs Design Example
• BCD to Gray code converter
K-map for Z
0 0 X 1
1 0 X 0
0 1 X X
1 0 X X
D
A
B
C
BC’
9/21/04 EECS150 F04 Culler 20EQ NE LT GT
A'B'C'D'
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
A B C D
PLA Second Design Example
• Magnitude comparator
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
D
A
B
C
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
D
A
B
C
0 0 0 0
1 0 0 0
1 1 0 1
1 1 0 0
D
A
B
C
0 1 1 1
0 0 1 1
0 0 0 0
0 0 1 0
D
A
B
C
K-map for EQ K-map for NE
K-map for GTK-map for LT
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Other Options
• Muxes
• DeMuxes
• ROMs
• LUTs
• We will return to these later
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Announcements
• Reading: Katz 1.4.2 (again), 7.1-3, pp 174-186
• Mid term th 10/7
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Recall: What makes Digital Systems tick?
Combinational
Logic
time
clk
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Recall 61C: Single-Cycle MIPS
PC
inst
ruct
ion
me
mor
y
+4
regi
ste
rs
ALU
Da
tam
em
ory
imm
3
1
x
LW
r3
, 17
(r1
)17
reg[1]
reg[1]+17
ME
M[r
1+1
7]
1. InstructionFetch
2. RegisterRead
3. Execute 4. Memory5. Reg.Write
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Recall 61C: 5-cycle Datapath - pipeline
PC
inst
ruct
ion
me
mor
y
+4
regi
ste
rs
ALU
Da
tam
em
ory
imm
3
1
x
LW
r3
, 17
(r1
)
1. InstructionFetch
17
reg[1]
2. RegisterRead
reg[1]+17
3. Execute
ME
M[r
1+1
7]
4. Memory5. Reg.Write
IR
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Typical Controller: state
Combinational
Logic
state
state(t+1) = F ( state(t) )
state Next state
i2 i1 i0 o2 o1 o0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 1 1
1 1 1 1 0 1
Example: Gray Code
Sequence
000 001 011 010 110 111 101 100
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Typical Controller: state + output
Combinational
Logic
state
state(t+1) = F ( state(t) )
state Next state
i2 i1 i0 o2 o1 o0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 1 1
1 1 1 1 0 1
Output (t) = G( state(t) )
0
1
1
0
1
0
0
1
odd
000/0 001/1 011/0 010/1 110/0 111/1 101/0 100/1
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Typical Controller: state + output + input
Combinational
Logic
state
state(t+1) = F ( state(t), input (t) )
state Next state
i2 i1 i0 o2 o1 o0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 1 1
1 1 1 1 0 1
Output (t) = G( state(t) )
0
0
0
0
0
0
0
0
1 x x x 0 0 0
clr
000/0 001/1 011/0 010/1 110/0 111/1 101/0 100/1
Input
0
1
1
0
1
0
0
1
odd
clr=1
clr=0
clr=?
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Two Kinds of FSMs
• Moore Machine vs Mealy Machine
Combinational
Logicstate
state(t+1) = F ( state(t), input)
Output (t) =
G( state(t), Input )
Input
state
state(t+1) = F ( state(t), input(t))
Output (t) = G( state(t))
Input
State / outInput State
Input / Out
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Parity Checker ExampleA string of bits has “even parity” if the number of 1’s in the string is even.• Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd:
• Can you guess a circuit that performs this function?
ParityChecker
IN OUTbit stream
0 if even parity1 if odd parity
example: 0 0 1 1 1 0 1 even even odd even odd odd even
CLK
time
CLK
IN
OUT
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Formal Design Process
• “State Transition Diagram”– circuit is in one of two states.
– transition on each cycle with each new input, over exactly one arc (edge).
– Output depends on which state the circuit is in.
ParityChecker
IN OUTbit stream
0 if even parity1 if odd parity
example: 0 0 1 1 1 0 1 even even odd even odd odd even
CLK
time
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Formal Design Process• State Transition Table:
• Invent a code to represent states:Let 0 = EVEN state, 1 = ODD state
present nextstate OUT IN state
EVEN 0 0 EVEN EVEN 0 1 ODD ODD 1 0 ODD ODD 1 1 EVEN
present state (ps) OUT IN next state (ns) 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0
Derive logic equations from table (how?):
OUT = PS
NS = PS xor IN
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Formal Design Process
• Circuit Diagram:
– XOR gate for ns calculation
– DFF to hold present state
– no logic needed for output
Logic equations from table:
OUT = PS
NS = PS xor IN
nsps
• Review of Design Steps:
1. Circuit functional specification
2. State Transition Diagram
3. Symbolic State Transition Table
4. Encoded State Transition Table
5. Derive Logic Equations
6. Circuit DiagramFFs for state
CL for NS and OUT
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Finite State Machines (FSMs)
• FSM circuits are a type of sequential circuit:– output depends on present and
past inputs
» effect of past inputs is represented by the current state
• Behavior is represented by State Transition Diagram:– traverse one edge per clock cycle.
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FSM Implementation
• FFs form state register
• number of states 2number of flip-flops
• CL (combinational logic) calculates next state and output
• Remember: The FSM follows exactly one edge per cycle.
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Another example
• Door combination lock:– punch in 3 values in sequence and the door opens; if there is
an error the lock must be reset; once the door opens the lock must be reset
– inputs: sequence of input values, reset
– outputs: door open/close
– memory: must remember combinationor always have it available as an input
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Implementation in softwareinteger combination_lock ( ) {
integer v1, v2, v3;integer error = 0;static integer c[3] = 3, 4, 2;
while (!new_value( ));v1 = read_value( );if (v1 != c[1]) then error = 1;
while (!new_value( ));v2 = read_value( );if (v2 != c[2]) then error = 1;
while (!new_value( ));v3 = read_value( );if (v2 != c[3]) then error = 1;
if (error == 1) then return(0); else return (1);
}
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Implementation as a sequential digital system
• Encoding:– how many bits per input value?
– how many values in sequence?
– how do we know a new input value is entered?
– how do we represent the states of the system?
• Behavior:– clock wire tells us when it’s ok to look at inputs
(i.e., they have settled after change)
– sequential: sequence of values must be entered
– sequential: remember if an error occurred
– finite-state specification
resetvalue
open/closed
new
clockstate
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closed closedclosedC1=value
& newC2=value
& newC3=value
& new
C1!=value& new
C2!=value& new
C3!=value& new
closed
reset
not newnot newnot new
S1 S2 S3 OPEN
ERR
open
Sequential example: abstract control• Finite-state diagram
– States: 5 states
» represent point in execution of machine
» each state has outputs
– Transitions: 6 from state to state, 5 self transitions, 1 global
» changes of state occur when clock says it’s ok
» based on value of inputs
– Inputs: reset, new, results of comparisons
– Output: open/closed
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reset
open/closed
new
C1 C2 C3
comparator
value
equal
multiplexer
equal
controllermux control
clock
data-path vs. control
• Internal structure– data-path
» storage for combination
» comparators
– control
» finite-state machine controller
» control for data-path
» state changes controlled by clock
datapath
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closed
closedmux=C1reset equal
& new
not equal& new
not equal& new
not equal& new
not newnot newnot new
S1 S2 S3 OPEN
ERR
closedmux=C2 equal
& new
closedmux=C3 equal
& new
open
Sequential example (cont’d):finite-state machine• Finite-state machine
– refine state diagram to include internal structure
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reset new equal state state mux open/closed1 – – – S1 C1 closed0 0 – S1 S1 C1 closed0 1 0 S1 ERR – closed0 1 1 S1 S2 C2 closed0 0 – S2 S2 C2 closed0 1 0 S2 ERR – closed0 1 1 S2 S3 C3 closed0 0 – S3 S3 C3 closed0 1 0 S3 ERR – closed0 1 1 S3 OPEN – closed 0 – – OPEN OPEN – open0 – – ERR ERR – closed
next
Sequential example (cont’d):finite-state machine• Finite-state machine
– generate state table (much like a truth-table)
closed
closedmux=C1
reset equal& new
not equal& new
not equal& new
not equal& new
not newnot newnot new
S1 S2 S3 OPEN
ERR
closedmux=C2 equal
& new
closedmux=C3 equal
& new
open
Symbolic states
Encoding?
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Sequential example: encoding
• Encode state table– state can be: S1, S2, S3, OPEN, or ERR
» needs at least 3 bits to encode: 000, 001, 010, 011, 100
» and as many as 5: 00001, 00010, 00100, 01000, 10000
» choose 4 bits: 0001, 0010, 0100, 1000, 0000
• Encode outputs– output mux can be: C1, C2, or C3
» needs 2 to 3 bits to encode
» choose 3 bits: 001, 010, 100
– output open/closed can be: open or closed
» needs 1 or 2 bits to encode
» choose 1 bits: 1, 0
binary
One-hot
hybrid
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good choice of encoding!
mux is identical to last 3 bits of next state
open/closed isidentical to first bitof state
Sequential example (cont’d):encoding• Encode state table
– state can be: S1, S2, S3, OPEN, or ERR
» choose 4 bits: 0001, 0010, 0100, 1000, 0000
– output mux can be: C1, C2, or C3
» choose 3 bits: 001, 010, 100
– output open/closed can be: open or closed
» choose 1 bits: 1, 0
reset new equal state state mux open/closed1 – – – 0001 001 0 0 0 – 0001 0001 001 00 1 0 0001 0000 – 00 1 1 0001 0010 010 0 0 0 – 0010 0010 010 00 1 0 0010 0000 – 00 1 1 0010 0100 100 0 0 0 – 0100 0100 100 00 1 0 0100 0000 – 00 1 1 0100 1000 – 1 0 – – 1000 1000 – 10 – – 0000 0000 – 0
next
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reset
open/closed
new equal
controllermux control
clock
reset
open/closed
new equal
mux control
clock
comb. logic
state
special circuit element, called a register, for remembering inputswhen told to by clock
Sequential example (cont’d):controller implementation• Implementation of the controller
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One-hot encoded FSM
• Even Parity Checker Circuit:
• In General:
• FFs must be initialized for correct operation (only one 1)
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FSM Implementation Notes• General FSM form:
• All examples so far generate output based only on the present state:
• Commonly called Moore Machine
(If output functions include both present state and input then called a Mealy Machine)
Often PLAs
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system
data-path control
stateregisters
combinationallogic
multiplexer comparatorcode
registers
register logic
switchingnetworks
Design hierarchy