EET 252 Unit 5 Programmable Logic: FPGAs & HDLs Read Floyd, Sections 11-5 to 11-10. Study Unit 5...

EET 252 Unit 5Programmable Logic: FPGAs & HDLs

Read Floyd, Sections 11-5 to 11-10. Study Unit 5 e-Lesson. Do Lab #5.

Lab #5a due next week. Homework #5 and Lab #5b due in two

weeks. Midterm exam next week.

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

Review

SPLD: (Simple PLDs) are the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates. (The PAL and GAL are both SPLDs).

CPLD: (Complex PLDs) are multiple SPLDs arrays and inter-connection arrays on a single chip.

FPGA: (Field Programmable Gate Array) are a more flexible arrangement than CPLDs, with much larger capacity.

Programmable Logic Devices (PLDs) are ICs with a large number of gates and flip flops that can be configured to perform a specific logic function or perform the logic for a complex circuit. Major types of PLDs are:

FPGAs compared to CPLDs

CPLDs FPGAs

Based on programmable AND array and fixed OR

array.

Based on look-up table (LUT), which is basically a truth table. (Results

in higher density.)

Usually EEPROM technology, so non-

volatile.

Usually SRAM technology, so volatile.

Both are programmed using the same software, using either schematic entry or text entry.

Copyright ©2009 by Pearson Higher Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

Digital Fundamentals, Tenth EditionThomas L. Floyd

Figure 11.34 The basic concept of an LUT programmed for a particular SOP output.


FPGAs

An FPGA uses a different architecture than a CPLD. The configurable logic block (CLB) or logic array block (LAB) is the basic element which is replicated many times.

CLB

Logic module

Localinterconnect

Global columninterconnect

Logic module

Logic module

Logic module

CLB

Logic module

Localinterconnect

Logic module

Logic module

Logic module

Global rowinterconnect

CLBs are arranged in a row and column structure. Within the CLBs are logic modules joined by local interconnects. Generally, the logic modules are composed of a look-up table (LUT), a flip-flop, and a MUX that can be used to bypass the flip-flop for strictly combinational logic.


FPGAs

Logic modules can be configured for combinational logic, registered logic, or a combination of both. The global interconnects distribute signals (including the clock) to various CLBs.FPGAs may also have a “hard core” portion of logic that is put in by the manufacturer and cannot be reprogrammed by the user. These FPGAs are useful in commonly used functions such as I/O interfaces.

CLB

Logic module

Localinterconnect

Global columninterconnect

Logic module

Logic module

Logic module

CLB

Logic module

Localinterconnect

Logic module

Logic module

Logic module

Global rowinterconnect

FPGA Cores

Most SPLDs and CPLDs are completely blank when you buy them.

Because FPGAs are so dense, many chip-makers give the option of manufacturing some of the circuitry to perform a specific function, such as a microprocessor or a RAM.

Such pre-programmed circuitry is called a core.

Example Showing FPGA Cores (Fig. 11-43)

Hard Core, Soft Core, IP

A hard core is a core that cannot be reprogrammed by the user.

A soft core is a core that the user can reprogram to some extent.

Cores are also referred to as intellectual property (IP), since the chip-maker retains ownership of the core design.

Example on Altera’s website.

http://www.altera.com/products/ip/ipm-index.html




Review: Programmable Logic Software

All manufacturers of programmable logic provide software to support their products. The process is illustrated in the flowchart.

Design entry

Synthesis

Deviceprogramming(downloading)

TimingsimulationFunctional

simulation

Implementation

SchematicHDL

The first step is to enter the logic design into a computer. It is done in one of two ways:

1) Schematic entry2) Hardware description

language (HDL).


Review: Programmable Logic Software

In schematic entry, the design is drawn on a computer screen by placing components and connecting then with simulated wires. After drawing the schematic, it can be reduced to a single block symbol:

Design entry

SchematicHDL


Programmable Logic Software

In text entry, the design is entered via a hardware description language such as VHDL or Verilog.

Design entry

SchematicHDL

Hardware Description Languages (HDLs)

Many hardware description languages (HDLs) exist for text entry of PLD designs.

Learning an HDL takes longer than learning to do schematic entry. But for complex designs it can provide a more powerful and simpler way to enter designs.

Some Popular HDLs

Open-standard HDLs VHDL (IEEE 1076) Verilog (IEEE 1364)

Proprietary HDLs CUPL ABEL (Advanced Boolean Expression

Language, now owned by Xilinx) AHDL (Altera HDL)

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

A VHDL Sample

One way of writing VHDL programs is to use Boolean-type statements. There are two parts to such a program: the entity and the architecture. The entity portion describes the I/O. The architecture portion describes the logic. Following is a short VHDL program showing the two parts.

entity Example is

port (B,C,D: in bit; X: out bit);

end entity Example;

architecture Behavior of Example isbegin X <= (B or C) and D;

end architecture Behavior;


A Verilog Sample

Another standard HDL is Verilog. In Verilog, the I/O and the logic is described in one unit called a module. Verilog uses specific symbols to stand for the Boolean logical operators.

The following is the same program as in the previous slide, written for Verilog:

module Example (X, B, C, D);input B, C, D;output X;

assign X = (B | C)&D;endmodule


Boundary Scan Logic

Boundary scan logic is circuitry on a PLD whose purpose is to let users test and program the chip. The JTAG standard (IEEE 1149.1) is a widely used open standard that defines four internal registers and five I/O signals for this purpose.

Under normal operation, the boundary scan logic is “invisible”.

JTAG (IEEE 1149.1) Registers and I/O Signals

Registers Boundary scan register Bypass register Instruction register Optional: Identification register

I/O Signals TDI (Test Data In) TDO (Test Data Out) TMS (Test Mode Select) TCK (Test Clock) Optional: TRST (Test Reset)

See pp. 4-5 of Altera UP1 Board manual (on course website).

http://people.sinclair.edu/nickreeder/manuals/AlteraUP1EducationKit.pdf






Figure 11.62 Greatly simplified diagram of a JTAG compliant (IEEE Std. 1149.1) programmable logic device (CPLD or FPGA). The BSCs (boundary scan cells) form the boundary scan register. Only a small number of BSCs are shown for illustration.




Figure 11.63 Boundary scan logic diagram.


Selected Key Terms

PAL

GAL

Macrocell

CPLD

A type of one-time programmable SPLD that consists of a programmable array of AND gates that connects to a fixed array of OR gates.

A reprogrammable type of SPLD that that is similar to a PAL except it uses a reprogrammable process technology, such as EEPROM instead of fuses.

Part of a PAL, GAL, or CPLD that generally consists of one OR gate and some associated output logic.

A complex reprogrammable logic device that consists basically of multiple SPLD arrays with programmable interconnections.


Selected Key Terms

FPGA

Design flow

Schematic entry

Text entry

Boundary scan

Field programmable gate array; a programmable logic device that uses the LUT as the basic logic element and generally employs either the antifuse or SRAM-based process technology

The process or sequence carried out to program a target device.A method of placing a logic design into software using schematic symbols.

A method of placing a logic design into software using a hardware description language (HDL).

A method for internally testing a PLD based on the JTAG standard (IEEE Std. 1149.1).

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EET 252 Unit 5 Programmable Logic: FPGAs & HDLs Read Floyd, Sections 11-5 to 11-10. Study Unit 5...

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