EEWeb Pulse - Volume 15

PULSE EEWeb.comIssue 15

October 11, 2011

Eric HollandDesign Engineer

Electrical Engineering Community

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EEWeb | Electrical Engineering Community Visit www.eeweb.com 3

TABLE O

F CO

NTEN

TSTABLE OF CONTENTS

Eric Holland 4SENIOR ELECTRONICS DESIGN ENGINEER, HACKER, AND BLOGGERInterview with Eric Holland, Avery Weigh-Tronix

Touchstone Semiconductor TS1001 Coolest Opamp DesignContest BY ERIC HOLLAND

Featured Products 10Control Synthesis Output with 11Combinatorial Logic in ProceduralCodeBY RAY SALEMI

All Storage Not Engineered Equally 16BY GARY DROSSEL WITH WESTERN DIGITAL

RTZ - Return to Zero Comic 21

9

Holland describes the details of his contest-winning Opamp design.

An explanation of various coding styles and their effects on synthesis results.

A careful look into the technology of various storage products to compare the quality of their operations.


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Eric HollandSenior Electronics Design Engineer What are you working on?I design embedded electronics for the weighing industry when I am not working on my latest electronics-related blog post. These scales range from small postal scales to larger tank weighers, all the way up to huge truck and rail scales. It is a fun industry, because I get to work on precision test and measurement equipment. Unlike voltmeters and oscilloscopes, these scales do not just need to function in a pristine lab environment; these scales have to weigh accurately when mounted outside in a desert heat or buried in a pile of snow on the frozen tundra. Most of the products I work on could be used in the food industry as well, so we need to seal up my electronics in a stainless steel water tight box.

Weigh Scale electronics are really not much different than DC voltmeters. A Fluke 87 Multimeter has a DC voltage measurement accuracy of +/- 0.1mV. Our weigh scales need to measure down to +/- 50nV accurately over a -20 to +60 Degrees celsius range in order to meet our certified weighing specifications. Weigh scales, like multimeters, have the benefit of only having to make measurements 100 times per second or less. This

means we can make use of 20 or 24-bit Delta Sigma analog to digital converters that Texas Instruments, Analog Devices, Linear Technology, and many other semiconductor manufacturers provide.

What are some challenges in the weigh scale market today?Time. Most industrial weigh scale companies have product lines that I would call high mix, low volume. I design and maintain hundreds of different embedded scale products, but if we sell 10 thousand of one particular model, we are doing

really well. This high mix of products makes keeping them updated with the latest and greatest electronic components challenging, and needless to say, we fight End-of-Life and Last-Time-Buy issues daily.

Getting data out of the box is another interesting challenge. Just providing a product that has the most elegant A-to-D section and weighs better than anything else on the market is not good enough. We need to have means of getting the weight, time, and other entered information out of the box and to the customer’s PLC or central computer server. We are moving to many Ethernet based field bus standards like EthernetIP and ProfiNet, but also use USB, RS232, and RS422/485 as a communication medium.

The other challenge I’ve noticed that isn’t so obvious is the green/low power movement. Now it isn’t our customers that are asking for Low Power Scales, because 99 percent of our products just plug into an AC

Eric Holland - Designer of Embedded Electronics for the Weighing Industry


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outlet. What is challenging about the low power movement is the fact that many of the precision analog components we rely on (opamps, comparators, and analog-to-digital convertors) are moving to lower and lower supply voltages. This trend is not just because of the green movement, smaller silicon feature geometries are also pushing this trend as well. Weigh scale loadcells are ratiometric, so the voltage signal you get out of them is directly proportional to the supply voltage you feed them. Historically, 15V and 10V excitation voltage levels were common, but due to the shrinking supply voltages on our analog parts, we’ve had to either get a bit creative and add cost to our designs or move to lower 5V and 3.3V loadcell excitation voltages. Now, on bench or even floor scales this isn’t that big of a deal, but on truck and rail scales that have 1,000 feet or more of cabling between the loadcells and the analog-to-digital converter, +3.3V excitation is a problem.

How did you get into electronics?My younger brother and I loved LEGOs and we built some pretty elaborate castles. We would always make them without roofs, so you could move the minifigs from room to room. We also had all kinds of secret passageways and trap doors built into the castles as well. I remember going to Radio Shack and buying a pack of LEDs and stringing them all together and using them as torches that lit up our castles. I also remember wiring up a 555 timer to blink a couple LEDs for my LEGO fireplace. I had no idea how LEDs worked but I knew

if you wired them up to a battery pack they would only light up when hooked up a certain way.

From Radio Shack, The Forrest Mims Engineer’s Mini-Notebooks and a 50-in-One electronics kit was probably my first taste at real electronics. I was also very lucky to go to a high school that had a couple of electronics electives. We wired up a three-way switch and etched our own PCBs to make an AC-DC power supply with a LM317. I actually still have this PSU and use it to power all my guitar effects stomp boxes.

Probably the biggest influence I had was in high school. I took a several BASIC, Visual BASIC, and C/C++ courses, and the regular teacher was on medical leave, so a local engineer came in and taught the C/C++ course. You could tell he loved being an electrical engineer and he encouraged me to go to college and get an electrical engineering degree.

What are your favorite hardware tools that you use?I am in love with my Agilent Infiniium 4-Channel 1 GHz MSO. The mega zoom feature is awesome. I can zoom out to 1 sec per division, see the I2C or SPI lines toggling, press the stop button and zoom right into each byte being transmitted. No need for fancy triggering when you can zoom in so far. I am also a huge fan of Metcal soldering irons; they are what I learned on when I was a technician soldering SMT components and I haven’t found anything I like better.

What are your favorite software tools that you use? We use Altium at work, and even though it has its quirks I think it is one of the best PCB CAD tools on the market. I’ve used Orcad and Mentor’s PADs as well but I think Altium is still better. Linear Tech’s LTSPICE is my go-to SPICE simulation tool. My favorite website is http://www.oemstrade.com; it enables me to search for parts at 33 different distributors with one button click. I use it to find parts or just simply validate P/N’s before I load them on an AVL.

What is the hardest/trickiest bug you have ever fixed? Almost five years ago I was hired as a contract engineer to help a local medical company redesign and update its 100 Watt, 900 MHz, microwave generator. The microwave generator consisted of a microcontroller PLL-based frequency synthesizer and a RF power amplifier.

The 50 dB Power Amplifier consisted of three RF amplification stages and was in need of a complete redesign as it was based around several parts that are now obsolete. My problems started in the lab after my first Power Amplifier prototypes showed up. The output stage of my amplifier was continuing to “burst into flames.” These made exploding tantalum capacitors look like child’s play in comparison. Every time the output stage blew up it would take a chunk of the Arlon PCB with it. Embarrassingly, this happened often enough with this project that I got quite good at repairing the burnt traces with copper tape,


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some solder, and some patience. Needless to say I was stressed out. This was my first high-power RF design and I needed a “grey beard” to help me out. I got a hold of an older RF engineer named John, who like most good RF engineers was a HAM Radio nut and had more electronic equipment in his basement than the Pentagon.

John and I hooked up my RF power amplifier to a signal generator and slowly cranked up the output power until we noticed the frequency spectrum of the output started going unstable and multiple frequencies popped up. We quickly backed the power off. This was my first clue as to what I was doing wrong. Before, I was never monitoring the output of the RF amplifier with a spectrum analyzer, I was just using a RF power meter; it was equivalent to using a multimeter to measure a voltage when you really should use a scope, so you can see more than just the “average” information. My amplifier was turning into an oscillator due to some unwanted positive feedback. A few cuts to our GND plane, isolating each stage a bit better, and retuning each stage’s gain down a little, our amplifier stayed an amplifier. I am over simplifying the process we went through, but a few weeks later we had a non-oscillating RF amplifier.

What is on your bookshelf? • The Circuit Designers

Companion by Tim Williams• Texas Instruments’ OpAmps for

Everyone Design Reference• Analog Devices’ OpAmp

Applications Handbook

• Home Brewing for Dummies by Marty Nachel.

No, my day job isn’t driving me to drink, but I believe combining hobbies is fun. I see a bunch of Arduino-based Electronic Brew monitoring devices in my future.

Do you have any tricks up your sleeve? My tricks are pretty simple. When you get in a brand new prototype, always measure the continuity between ground and all the power supply rails before even thinking about hooking up power to the board. Then hook the board up to a bench supply with the current limit down as far as it will go.

Companies are going to continue to “do more with less” in

terms of the number of engineers they have on staff, and this isn’t necessarily because of economic reasons.

I strongly believe it just takes fewer

engineers to bring a product to market than

it did 20 years ago.

That way, when you turn on the bench supply, if your prototype is a heater you shouldn’t damage anything too bad. You need a little bit of give and take on the current limit because some designs have a bit of an inherent inrush surge current on power up, and you need to make sure the bench supply can supply that before the limiting happens.When SMT soldering, always use a medium to large chisel tip and plenty of no-clean flux to drag the solder across the pins. I have seen way too many people grab extremely small conical tips and expect to solder each pin individually. Let the flux do the work for you.

What has been your favorite project?A few years ago I designed a starter interrupt device to enable a local non-profit to sell donated cars to people with less-than-perfect credit. It was a neat project because I did everything from the hardware design to the embedded firmware, the PCB Layout, and wrote a Visual Studio PC application to configure the device. You can check out the complete project on my blog: http://embeddederic.blogspot.com/

What direction do you see the electronics industry heading in the next few years?Companies are going to continue to “do more with less” in terms of the number of engineers they have on staff, and this isn’t necessarily because of economic reasons. I strongly believe it just takes fewer engineers to bring a product to market than it did 20 years ago. This is because of all the CAD tools and integration semiconductor


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suppliers are now providing OEMs. For example, three years ago if you needed an ECG frontend circuit, you had to do it all discretely with instrumentation amps, op amps, and an ADC. Now you can just slap down a Texas Instruments ADS1298 and get a jump start on your design. Now these integrated solutions don’t always have all the “special sauce” type features that help differentiate one OEMs product from another, but it does get you started quickly.

One of my favorite things to do when I have a bit of down time at work is to flip through the old retired engineers’ lab notebooks from the

late 70s through the 90s. The first thing I notice is that I feel bad for the new generation of engineers reading through my lab notebooks because they are not nearly as pristine as these old ones are. The next thing I notice is how much of their time they spent designing DC/DC converter controllers, chopper stabilized opamps, and single/dual slope ADCs. These, for the most part, are components I can just buy from semiconductor manufacturers and I spent a lot more of my time at work solving the “How do I get data in/out of my box?” type problems. But this just goes back to my point: Because semiconductor

manufacturers are delivering so much application-specific hardware to the OEMs, we only have to focus on the “Special Sauce” instead of all the individual pieces.

I also think social media like Twitter, Forums, Blogs, and websites like EEWeb are going to become much more important in knowledge sharing and mentoring the next generation of engineers. With fewer engineers doing the same work in shorter timelines, these online social media outlets can provide so much quick information to help solve the day-to-day problems. ■

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Touchstone Semiconductor TS1001 Coolest Opamp Design Contest By Eric Holland

Can you describe how you heard about the contest and some details about your project?I actually heard about the contest while listening to a weekly electron-ics radio show, TheAmpHour (www.theamphour.com). Chris and Dave, the two radio hosts, were ranting about how strict the design contest rules were. Each entry had to use one or more Touchstone Semicon-ductor TS1001 low power opamps and the total circuit had to run off 2.5V or less supply voltage and draw 5uA or less current. I actually got pretty excited when I heard about the strict rules because I knew the contest entries would have to be more minimalist in nature and really show off the low power aspect of the TS1001.

I thought it would be fun to redesign the 555 timer discretely using two TS1001 low power opamps as comparators. The goal was to make the 555 timer run on supply voltages below 1V and less than 5uA, so I could use an orange to power the 555 timer in astable mode. I remember quite a few years ago Xilinx had those CoolRunner CPLD ads with the CPLD being powered off a lemon; I always thought that was cool and I wanted to do that same thing on this project. It actually worked out well because I had just

finished helping my wife’s younger brother with a science project where we built up a bunch of batteries from various fruits. This past summer I had 555 timers on the brain as well, because I was kicking myself for not entering Chris Gammell & Jeri Ellsworth’s 555 Timer Design Contest (www.555contest.com/) a few months earlier. They had some awesome entries.

The 555 timer I designed used two TS1001’s as the comparators and a Texas Instruments SN74AUC2G02 dual-NOR gate for the SR latch. I then dialed the frequency of the circuit down to 18Hz, so I could meet the 1V at 4.4uA power limit. The idea of a Low Power 555 timer

isn’t an original idea by any means. Diodes Inc. has a ZSCT1555 that runs up to 330KHz at 75uA. My 555 timer circuit is bit lower power, but my max operating astable frequency at a 1V supply voltage is 525Hz, engineering is all about tradeoffs.

Thanks again Touchstone Semicon-ductor and Future Electronics for putting on the competition, I had a lot of fun. If you are interested in reading more on my 555 timer con-test entry check out this blog post on EEWeb.■

Congratulations on your winning entry in the Touchstone Semiconductor TS1001 Coolest Opamp design contest

www.theamphour.com

www.theamphour.com

www.eeweb.com/blog/eric_holland/3-ics-a-bjt-a-few-resistors-and-an-orange

www.eeweb.com/blog/eric_holland/3-ics-a-bjt-a-few-resistors-and-an-orange


FEATURED

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Low Noise 24-bit ADCIntersil Corporation introduced the ISL26132 and ISL26134, 24-bit delta-sigma ADCs containing an ultra-low noise programmable gain amplifier (PGA) with gains of 1x, 2x, 64x and 128x. Designed for weigh scales, precision sensors and industrial process control systems, the new ADCs provide direct connection to sensors without the need for additional circuitry. Their industry-leading noise performance at both 10Sps (samples per second) and 80Sps conversion rates assure excellent accuracy in high-resolution measurement applications. Both devices

are drop-in improved replacements for the ADS1232 and ADS1234, providing designers with an easy upgrade path where ultra-low noise performance is desired (up to one additional bit of noise-free measurement accuracy compared to alternative solutions). For more information, please click here.

Ultra-Low-Power Smart RadioFreescale Semiconductor is expanding its broad portfolio of wireless connectivity solutions with the new ultra-low-power, sub-1 gigahertz (GHz) MC12311 smart radio. The feature-rich, cost-effective MC12311 includes software and development tool support, making it a ready-to-go wireless networking solution ideal for smart metering, medical, building and home automation applications. Pike Research predicts 535 million smart meters will be deployed worldwide by 2015, of which approximately

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Control SynthesisOutput with

Combinatorial Logicin Procedural Code

Ray SalemiVerification ConsultantRay SalemiVerification Consultant

In one of my previous articles (“Creating Combinatorial Logic (Part 1)”) we created combinatorial logic using the continuous assignment in SystemVerilog and the concurrent assignment in VHDL. These are simple ways to create simple combinatorial logic. This month, we are going to up the ante.

We are also going to dispel the notion that designing hardware with a synthesis tool is the same thing as writing software with a compiler. It is not. The difference is that most software developers give little thought to how the compiler is implementing their code. After all, if you are thinking in terms of objects, linked lists, and data structures, it’s hard to also think in terms of assembly language instructions.

Hardware engineers don’t have this luxury. A sure sign that you’re talking to a new hardware engineer is when the person shrugs at the question, “What kind of hardware did you expect this to create?” We need to be conscious of how the synthesis tool will interpret their logic, and what kind of design they’ll see at the other end. For example let’s look at a simple adder written in SystemVerilog:

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module adder #(length=4) (input wire signed [length-1:0] a, b, output logic [length-1:0] sum, output logic overflow);

bit signed[length+1:0] max_numb = (2**(length-1))-1; bit signed[length+1:0] max_numb = (2**(length-1));

logic signed [length:0] internal_sum;

assign internal_sum = a + b; assign sum = internal_sum; assign overflow = (internal_sum > max_numb) || (internal_sum < min_numb);

endmodule : adder

Figure 1: Inferred Adder.

The adder module creates an parameterized adder with an overflow bit. The adder uses two’s complement math, so it can store a value in the range of 2**(length-1)-1 to -2**(length-1). For example, a 3-bit adder can range from 2**(3-1)-1 = 3 down to -2**(2) = -4. The adder uses continuous assignments to create the addition and check for the overflow.


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This is all well and good until we start to wonder about the adder being inferred. Is this adder being optimized for speed or for area? Probably for speed. It probably has a carry look-ahead capability that calculates all the carries at once so it can run with a fast clock cycle. But, what if we don’t care about speed? What if we have a slow clock and not much space? How can we take control of this design without resorting to hand-instantiating gates on a schematic? The key is to write procedural code in our combinatorial logic.

SystemVerilog and VHDL uses always blocks and processes to create combinatorial logic. We do this by creating always blocks and processes that are sensitive to the input signals in the block rather than to a clock. We’re going to use this capability to create a ripple carry adder that trades speed for area.

We build the ripple carry adder out of a classic full adder:

figure 3. A slightly more elegant approach would be to implement the full adder and then instantiate them using a generate statement. This second approach allows your adder to be parameterized by width. But, once again, we are doing all the work.

The best approach is to put our combinatorial logic into a process or an always block and then let the synthesis tool create our ripple carry adder. We do that by writing our code this way:

The SystemVerilog Ripple Carry Adder

Here is the SystemVerilog code that creates our ripple carry adder without hand-instantiating any components. This code demonstrates how to create combinatorial logic with an always block:

Cout

SCinBA

Figure 2: Full Adder.

The full adder has three inputs and two outputs. The inputs are A and B with a carry in. The outputs are the sum (S) and the carry out. You create a ripple carry adder by stringing these full adders together like this:

A3

S3

C4

B3 A2

S2

C3

B2 A1

S1

C2

B1 A0

S0

C1 C0

B0

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

Adder

Figure 3: Ripple Carry Adder.

The question is, how do we implement this kind of adder in SystemVerilog or VHDL. The brute-force approach is to create a module that implements the full adder and then instantiate the full adders so that they look like

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module adder #(length=4) (input wire [length-1:0] a, b, output logic [length-1:0] sum, output logic overflow);

logic [length-1:-1] carry;

always @(a or b) begin carry[-1] = 0; for (int i=0; i<length; i = i+1) begin :addloop sum[i] = a[i] ^ b[i] ^ carry[i-1]; carry[i] = ((a[i]^b[i]) & carry[i-1] | (a[i] & b[i]); end : addloop overflow = carry[length-1] ^ carry[length-2]; endendmodule : adder

Figure 4: Verilog Adder.

Let’s examine this code line-by-line:

• Line 2: This is a parameterized piece of IP. We can modify its length when we instantiate it by setting the parameter called length.

• Lines 3-5: We declare the input signals using the parameter. The sum is the same width as the inputs. We could avoid the whole overflow issue by using a wider sum, but we’re not going to do that.

• Line 7: Carry is an internal array. It holds the carry values between the full adders. Notice that carry’s index goes from length-1 to -1 (this is easily done in SystemVerilog if not VHDL). We’ll use the -1 index to ground the first carry.


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• Line 9: This process is sensitive to changes in a or b. This means that the for loop will run whenever a or b changes.

• Line 11: If we’re here then a or b has changed and we are going to calculate a new sum and overflow.

• Lines 12-16: This for loop is the key to creating the ripple carry adder. Because we don’t have a clock, the synthesis tool will unroll this loop into combinatorial logic. We loop over all the values in the a and b inputs and calculate the sum and carry for each. Notice that we access the previous carry by using the index i-1. This loop places the bits for the sum into the sum array and the bits for the carry into the carry array one at a time. Just like a ripple carry adder.

• Line 17: You calculate overflow in a two’s complement adder by checking the last two carry bits. If they are different, then you have an overflow.

Now, let’s look at the same thing in VHDL.

VHDL Ripple Carry Adder

As is usually the case, the VHDL code is longer than the SystemVerilog code. Notice that VHDL requires that we do our combinatorial calculations on variables, and then put the results onto signals. This is good for avoiding race conditions and makes sure that we don’t confuse the signals for the intermediate variables. SystemVerilog allows us to work directly on the output signals and then “does the right thing.” See Figure 5 for the VHDL.

The VHDL code is identical to the SystemVerilog code except for some language quirks. Let’s go through it line by line:

• Line 6: This module is also parameterized. VHDL uses the word generic for this functionality.

• Lines 8-12: The inputs and outputs are declared based on the length.

• Line 16: With VHDL we could create several architectures to implement the same functionality.

• Lines 19-22: VHDL requires that we operate on variables in our process. Notice that the carry’s lowest index is 0. This is required for the natural

numbers that we’re using to index into the array. Therefore the upper end of the array is set to length, rather than length-1. I’ve used length as the upper end of the array for all the variables.

• Lines 25-26: We copy the signals into variables.

• Line 27: We “ground” the lowest carry bit.

• Lines 28-31: This loop is identical to the SystemVerilog one except that it operates with 1 as its lowest number. We are implementing the same logic.

• Line 33: Calculate the overflow with the top two carry bits.

• Line 34: Put the sum value onto the sum signal.

The Results

Both of these implementations give us the following logic. This example was done with length set to 2: You can see that the synthesis tool has implemented the logic

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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;

entity adder is generic ( length : integer := 4); -- bus length port( a : in std_logic_vector (length-1 downto 0); b : in std_logic_vector (length-1 downto 0); overflow : out std_logic; sum : out std_logic_vector (length-1 downto 0) );end adder ;

architecture ripple of adder isbegin process (a,b) variable carry :std_logic_vector( length downto 0 ); variable a_val :std_logic_vector( length downto 1 ); variable b_val :std_logic_vector( length downto 1 ); variable sum_val :std_logic_vector( length downto 1 );

begin a_val := a; b_val := b; carry(0) := ‘0’; for i in 1 to length loop sum_val(i):= (a_val(i) xor b)val(i)) xor carry(i-1); carry(i) := ((a_val(i) xor b_val(i)) and carry(i-1)) or (a_val(i) and b_val(i)); end loop; overflow <= carry(length) xor carry(length-1); sum <= sum_val; end process;end architecture rtl;

Figure 5: VHDL Adder.


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outsum

overflowout

in[0]

in[1]

ix9out

in[0]

in[1]

ix7out

in[0]

a(1:0)

in[1]

ix11out

in[0]

in[1]

carry_andBus2(2:1)out

in[0]

in[1]

sum_xorBus1(1:0)

in[0]

in[1]

ix17a(1:0)

Figure 6: Gates.

from figure 2 to create the full adder and strung two of them together. It has optimized away our grounded first carry signal.

Now we can see the results of our labor. I synthesized both adders on an Actel ProASIC 3 part and counted the tiles for different lengths of adder. Here are the results:

1. We would need to generate a different piece of IP every time we changed the width.

2. We would not have been able to easily reuse our code when we switch vendors or architectures.

Generally speaking, we are better off writing as much of our design as possible in vendor-independent RTL. This practice makes it easy to reuse our designs and gives us solid control over what we create.

Summary

We learned how to create combinatorial logic in procedural code. We also saw that our coding style can have a dramatic effect on the results we get from our synthesis. Next month we’ll look at the downside of creating combinatorial procedures when we delve into the evil of latches.

References

You can see all the figures in the description of the ripple adder at this link. The figures have been released into the public domain.

About the Author

Ray Salemi is a veteran of the EDA industry and has been working with Hardware Description Languages since he joined Gateway Design Automation—the company that invented Verilog. Over the course of his career he has worked at Cadence, Sun Microsystems, and Mentor Graphics. Ray is currently an Applications Engineer Consultant with Mentor Graphics. ■

Adder Length

Tiles

8 64564840322416

800

700

600

500

400

300

200

100

0

Infared

Ripple

Figure 7: Adder Comparison.

Notice that the inferred adder’s area goes up exponentially with the width, while the ripple carry adder goes up linearly. This is because the ripple carry adder adds the same number of gates for each added signal in its length. The carry lookahead adder has logic that explodes at higher widths.

Why do this in RTL?

The final question to answer is this: “Why did we do this in RTL?” Wouldn’t it have been easier to go to our vendor’s IP generation tool and generate an adder?

It’s true that it might have been easier to generate an adder from the vendor, but then we would have lost two important features:

80V, 500mA, 3-Phase MOSFET Driver HIP4086, HIP4086AThe HIP4086 and HIP4086A (referred to as the HIP4086/A) are three phase N-Channel MOSFET drivers. Both parts are specifically targeted for PWM motor control. These drivers have flexible input protocol for driving every possible switch combination. The user can even override the shoot-through protection for switched reluctance applications.

The HIP4086/A have a wide range of programmable dead times (0.5ms to 4.5ms) which makes them very suitable for the low frequencies (up to 100kHz) typically used for motor drives.

The only difference between the HIP4086 and the HIP4086A is that the HIP4086A has the built-in charge pumps disabled. This is useful in applications that require very quiet EMI performance (the charge pumps operate at 10MHz). The advantage of the HIP4086 is that the built-in charge pumps allow indefinitely long on times for the high-side drivers.

To insure that the high-side driver boot capacitors are fully charged prior to turning on, a programmable bootstrap refresh pulse is activated when VDD is first applied. When active, the refresh pulse turns on all three of the low-side bridge FETs while holding off the three high-side bridge FETs to charge the high-side boot capacitors. After the refresh pulse clears, normal operation begins.

Another useful feature of the HIP4086/A is the programmable undervoltage set point. The set point range varies from 6.6V to 8.5V.

Features• Independently drives 6 N-Channel MOSFETs in three phase

bridge configuration

• Bootstrap supply max voltage up to 95VDC with bias supply from 7V to 15V

• 1.25A peak turn-off current

• User programmable dead time (0.5µs to 4.5µs)

• Bootstrap and optional charge pump maintain the high-side driver bias voltage.

• Programmable bootstrap refresh time

• Drives 1000pF load with typical rise time of 20ns and Fall Time of 10ns

• Programmable undervoltage set point

Applications• Brushless Motors (BLDC)

• 3-phase AC motors

• Switched reluctance motor drives

• Battery powered vehicles

• Battery powered tools

Related LiteratureAN9642 “HIP4086 3-Phase Bridge Driver Configurations and Applications”

”HIP4086EVAL Evaluation Board Application Note” (Coming Soon)

FIGURE 1. TYPICAL APPLICATION FIGURE 2. CHARGE PUMP OUTPUT CURRENT

Controller

AHO

CLO

BLO

ALO

CHO

BHO

CLI

BLI

ALI

CHI

BHI

AHICHS

AHS

BHS

CHB

AHB

BHB

VDD

RDEL

VDD

Speed

Brake

Battery24V...48V

HIP4086/A

VSS

-60 -40 -20 0 20 40 60 80 100 120 140 160

200

150

100

50

0

JUNCTION TEMPERATURE (°C)

OU

TPU

T C

UR

RE

NT

(µA

)

VxHB - VxHS = 10V

June 1, 2011FN4220.7

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010, 2011All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

Get the Datasheet and Order Samples

http://www.intersil.com

http://bit.ly/nHxRhB


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All StorageProducts NotEngineered Equally:

Gary DrosselDirector of Product Planning, Western Digital

Advanced Storage Options

In today’s complex storage world, engineers and OEM designers

are constantly challenged when evaluating on which storage solutions they should build their products. Storage products in the same industry-standard form factor from various suppliers may have similar sounding names, such as “industrial-grade” or “enterprise-class,” and may even have similar looking datasheet specifications, but they can be significantly disparate in actual operation. To accurately determine if similar looking, labeled, or specified products are indeed the same, a careful technology comparison must be conducted.

Technology Defines Storage Products — Not Form Factors, Product Labels, or Datasheets

The technology inside a product is what ultimately determines if an OEM achieves its performance, reliability, product lifecycle management, customer satisfaction, and total cost of ownership objectives.

Looks Can Be Deceiving

Storage product form factors used to define the technology inside a product, but today that is no longer true. Two storage products in the same industry-standard form factor, such as a Solid State Drive (SSD), can look the same on the outside but in reality be very different on the inside. For example, an SSD

designed for a consumer product application such as a laptop PC looks exactly like an SSD product used by an embedded OEM in an edge router or mission-critical data recorder, but the technology inside is radically different. To further complicate the product selection process, an SSD labeled by one supplier as industrial-grade or enterprise-class is likely to use completely different technology than a similarly labeled product from another supplier.

To make the product selection process even more confusing, continuing with this same example, different SSD products may even have similar looking product specifications. Commonalities in such basic product specifications


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as form factor, interface, read/write speed, power consumption, operating temperature range, mean time between failure (MTBF), and shock and vibration tolerances might fool all but the most highly trained into thinking that all storage products are engineered equally. In fact, depending on the comprehensiveness of the storage product qualification testing performed, different SSD products may even operate the “same” during an initial test period.

It’s the Technology Inside

A thorough examination of the technology inside a product is required to separate storage products intended for use in retail or consumer applications from advanced storage technology required in embedded OEM applications, such as netcom, military, industrial, interactive kiosk, and medical.

Looking beyond form factors, product labels, and datasheet specifications to the actual technology inside a storage system, an OEM designer will discover important considerations that can dramatically affect storage performance and selection criteria:

• How is the storage system engineered to guard against drive corruption from power anomalies (the number one cause of field failures)?

• How is the storage system engineered to guarantee endurance and reliability for several years of field use?

• What technology is available to monitor storage system useable

life to guard against failures due to wear-out?

• How often is the technology inside the storage product modified? (This can result in costly and forced product re-qualification.)

• What security options are available to protect data and software IP?

• Is the technology truly scalable across multiple form factors with no loss of performance or storage product features?

From products labeled enterprise-class or industrial-grade to those appearing to have similar datasheet specifications, what separates advanced storage technology from

other products seemingly in the same form factor can be effectively distilled by answers to the questions posed above.

Advanced Storage Technology

Using the SiliconDrive from Western Digital as an example, understanding advanced storage technology can be further explored.

Specifically engineered to exceed the high performance, high reliability, and multi-year product lifecycle requirements of the embedded OEM market, SiliconDrive technology from WD defines advanced storage technology by leveraging an array of patented and patent-pending technologies from WD to deliver the

Figure 1: SiliconDrive from Western Digital


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industry’s most reliable advanced storage solutions.

When considering the right storage product, a variety of market requirements should be reviewed.

I. Power Management Technology

The number one cause of costly storage system field failures is power disturbances. In the event of an ungraceful power-down, brownout, or power spike, power management technology is required to maintain a storage system’s reliability and eliminate drive corruption.

The Solution

WD SiliconDrives come equipped with WD’s patented PowerArmor technology that prevents data corruption and loss by integrating proprietary voltage detection circuitry and logic into every SiliconDrive. PowerArmor technology reduces total cost of ownership by decreasing maintenance, warranty, and other costs associated with unscheduled downtime and field failures.

II. Enhanced Endurance and Reliability

Endurance and reliability are critical selection criteria for embedded OEMs to guarantee storage system performance during multi-year end-product use. Endurance is defined as the number of write/erase cycles that can be performed before a storage product “wears out.” Wear-leveling and Error Correction Control (ECC) are two important algorithms that affect endurance.

The Solution

Offering the industry’s highest endurance, SiliconDrives feature advanced wear-leveling over the entire drive and a robust, industry-leading error correction algorithm specifically designed to exceed the requirements of embedded OEM applications. Advanced wear-leveling is important to endurance and reliability as it allows data to be written evenly over the entire storage system. A product with no wear-leveling wears out quickly because data can be written repeatedly to the same physical block. Products with basic wear-leveling may write data across only the dynamic or free data areas, resulting in a significantly shorter useable life than storage systems that deploy static wear-leveling.

III. Forecast Storage System Useable Life

Host system uptime, the elimination of unscheduled downtime, and overall system reliability are paramount in embedded OEM applications, therefore the need to proactively manage and predict storage system useable life is extremely important.

The Solution

WD SiliconDrives are equipped with patented SiSMART technology, the first technology in the industry to self-monitor solid state storage system usage and accurately forecast useable life. SiSMART acts as an early warning system by constantly monitoring and reporting the exact amount of remaining storage system life. This technology allows OEMs to build intelligence into host systems that enables users to set

maintenance and data collection thresholds to ensure storage system life. Traditional storage products typically run until they fail with no warning to the user that the end is near, which causes unexpected downtime and emergency host system maintenance to restore the system. Storage products that run until they fail are a bit like driving a car without a gas gauge — there is no predictive measure of when the car will stop running.

IV. User-Selectable Advanced Security Options

Critical applications require enhanced security options to protect application data and software IP from theft and malicious or accidental overwrites. Sophisticated storage management technology is required to overcome the engineering obstacles of designing robust security into low-power, small mechanical footprints.

The Solution

For applications that require varying levels of advanced security, WD offers SiliconDrive Secure, a comprehensive suite of user-selectable security technologies that solve the critical need for robust storage security for embedded systems applications that have a small footprint and low-power requirement. SiliconDrive Secure protects application data and software IP from theft, falling into the wrong hands from deployments in high-risk areas, corruption, and accidental or malicious overwrites.

SiliconDrive Secure provides the following advanced security functions:


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• Application data and software IP theft prevention

• Confidential data sanitization

• Access control and permissions selection

• Multiple security zone creation

V. Multi-Year Product Lifecycles

Embedded OEMs need to have true multi-year product lifecycles for all the critical components in their host system because they deploy their end-products for five to ten years, or even longer. Suppliers who frequently change or end-of-life their products cause a tremendous financial, technological, and logistical burden for OEMs, resulting in both costly and time-consuming product re-qualification that embedded OEMs want to avoid.

The Solution

WD’s SiliconDrive architecture enables continuous technology advancements while supporting both current and previous product generations. SiliconDrive architecture allows embedded OEMs to optimize the timing of new product qualifications to be based on technology advancements, not product obsolescence. This results in tremendous cost savings for embedded OEMs.

VI. Scalable Technology Across Multiple Form Factors

To keep pace with dynamic market and standards requirements, embedded OEMs need to be able to quickly migrate existing end-

product designs efficiently and cost effectively. Embedded OEMs are only able to accomplish this if the critical components used in their end-products are scalable in terms of both form factor and technology to meet their dynamic requirements.

The Solution

WD SiliconDrives were designed from the ground up to be highly scalable and form-factor independent with no loss of performance or reliability. Regardless of form factor, all SiliconDrives use the same core technology that saves embedded OEMs engineering design and architecture time and accelerates their time-to-market with new products. SiliconDrive is a technology platform, not merely multiple form factors.

Final Analysis

The saying “looks can be deceiving” is an understatement when it comes to comparing or evaluating storage products. One can easily be fooled by products packaged in the same industry-standard form factor, labeled the “same,” and have many of the “same” data sheet specifications.

To clearly understand how seemingly “identical” storage products compare, one must conduct a thorough evaluation of the technology inside each product. In addition, in-depth product testing across a wide spectrum of parameters must be conducted to guarantee storage system compatibility and long-term reliability when deployed in a field application.

Technology defines storage products — not form factors, product labels, or data sheets.

About the Author

Gary Drossel is the director of product planning at Western Digital’s Solid State Storage Business Unit. Prior to the March 2009 acquisition of SiliconSystems by Western Digital, Drossel was the vice president of product planning at SiliconSystems. Previously, Drossel has also held various marketing, sales and field engineering management positions with SimpleTech, Motorola Computer Group’s Pro-Log division, and the industrial automation group of Parker Hannifin. Drossel graduated with a B.S. degree in Electrical and Computer Engineering from the University of Wisconsin. ■

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