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Synthetic Metals
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ffects of gate dielectric composition on the performance of organichin-film devices
ujoy Das, Junghyun Lee, Taehoon Lim, Youngill Choi, Yong Sun Park, Seungmoon Pyo ∗
epartment of Chemistry, Konkuk University, 1 Hwayang-dong, Kwangjin-Gu, Seoul 143-701, Republic of Korea
r t i c l e i n f o
rticle history:eceived 13 October 2011eceived in revised form 6 January 2012ccepted 24 January 2012vailable online 22 March 2012
a b s t r a c t
Four poly(4-vinyl phenol) based gate dielectrics were tested to optimize the performance of pentaceneorganic field-effect transistors. The dielectrics’ surface tensions, Fourier transform infrared spectra, capac-itances and leakage currents were measured. The optimal dielectric allowed the transistor to shownegligible hysteresis with high performance even in ambient conditions. A complementary inverter wasfabricated by integrating in single substrate pentacene (p-type) and F16CuPc (n-type) OFETs contain-
ing the optimized gate dielectric. Its voltage transfer curve showed almost symmetric noise margin; itshowed a logic threshold of 22.5 V and a maximum voltage gain (�Vout/�Vin) of 6.2 at Vin = 22.5 V.
Organic semiconductors are being developed for use in elec-ronic and optoelectronic devices such as organic light-emittingiodes [1], organic field-effect transistors (OFETs) [2], and organicolar cells [3]. Their main advantages over conventional inorganicemiconductors include the fine tuning of their properties by pre-ise synthesis, solution based low-cost large-area processabilitynd good compatibility with flexible substrates. OFETs employingrganic semiconductors have shown simple solution processabil-ty [4,5] and potential applicability in radiofrequency identificationRFID) tags [6], smart cards [7], active matrix liquid crystal displays8] and chemical sensors [9]. While most research has focused onhe development of high field-effect mobility organic semiconduc-ors, there has been a lack of work on polymer gate dielectrics,hich were developed as alternatives to inorganic gate dielectrics
10]. Polymer gate dielectrics could be useful in OFETs due toheir facile solution processability and compatibility with vari-us (including flexible) substrates. They can also provide smoothurfaces on transparent glass or plastic substrates. The chemicaltructure of a polymer gate dielectric can impart various surfacend bulk properties that strongly influence a device’s performance
11], making its composition an important factor affecting the fabri-ation of OFETs. Several polymer gate dielectrics have been used inigh-performance OFETs, including poly(4-vinylphenol) (PVP) [12],
poly(vinylalcohol) (PVA) [13], poly(methylmethacrylate) (PMMA)[14], polystyrene (PS) [15], and polyimide (PI) [16]. Among these,thermally [17] and photochemically [18] cross-linked polymer gatedielectric such as PVP and PVA has been widely employed becauseof its favorable dielectric and electrical properties [19–21]. Its cross-linking reaction ensures a minimal density of hydroxyl ( OH)groups that strongly interact with environmental moisture andmobile ions to form charge traps at the semiconductor/dielectricinterface. It also provides excellent insulation and solvent resis-tance [22,23]. There are few reports discussing the influence of thedegree of cross-linking in PVP gate dielectrics on the performance ofOFETs. Compositional effects of PVP gate dielectrics on the perfor-mance of n-type F16CuPc organic semiconductors have previouslybeen reported [21]. Jang et al. reported the effects of PVP’s dielectricconstant on OFETs’ performance by varying the molar ratio of thePVP/cross-linking agent [24], though their work did not focus onthe influence of the cross-linking agent on the devices’ operationalstability, i.e. hysteresis behavior. Kim et al. reported the effects ofhydroxyl groups on the hysteresis of pentacene field effect transis-tors by comparing PVP and PVP/PMMA copolymer gate dielectrics[22].
This work reports the effects of gate dielectric compositionon OFETs’ operational stability (hysteresis behavior) by compar-ing four PVP based gate dielectrics with different compositions.The OFETs were based on pentacene, one of the most promising
and widely investigated organic semiconductors [25–27], and theirperformances were measured under a variety of conditions. A com-plementary inverter based on p-type pentacene and n-type copperhexadecafluorophthalocyanine (F16CuPc) was fabricated using the
S. Das et al. / Synthetic Metals 162 (2012) 598– 604 599
F erter
o
od
2
2
plsdrfwdtpaos
2
teadIotowvtws5tpu
ig. 1. A bottom-gate top-contact pentacene based OFET (a) and complementary invf poly(4-vinylphenol) (PVP) (D1) and cross-linked PVP (D2, D3 and D4) (c).
ptimized polymer gate dielectric and its characteristics are alsoiscussed.
inker and propylene glycol monomethyl ether acetate (PGMEA)olvent were used in the preparation of the polymer gateielectrics. p-Type pentacene and n-type copper hexadecafluo-ophthalocyanine (F16CuPc) active semiconductors were used toabricate the OFETs and complementary inverter. All materialsere from Aldrich and used without further purification. Four gateielectrics with different compositions were prepared by varyinghe weight ratio of PVP and PMF: gate dielectric D1 comprisedristine PVP (10 wt%) solution in PGMEA, gate dielectrics D2, D3nd D4 were prepared by dissolving PVP with PMF at weight ratiosf 5:5, 7.5:5 and 10:5, respectively, in PGMEA with overnighttirring.
.2. OFET fabrication
Bottom-gate top-contact OFETs (Fig. 1a) were fabricated on pat-erned indium tin oxide (ITO)/glass substrates that acted as gatelectrodes. The ITO substrate was patterned by photolithographynd cleaned sequentially in an ultrasonic bath with detergent,eionized water, acetone, and isopropyl alcohol each for 15 min.
t was then dried at 80 ◦C in a drying oven and treated with UV-zone cleaner prior to use. The dielectric solution was spin-cast onhe top of the ITO/glass substrate and soft-baked at 90 ◦C for 10 minn a hot plate in air to give a thin uniform film. The soft-baked filmsere further baked at either 150 ◦C (D1) or 175 ◦C (D2, D3, D4) in a
acuum oven (10−3 Torr) for 1 h. The final thickness of the dielec-ric films was controlled to be ca. 450 nm. A 50 nm pentacene filmas thermally deposited at 0.2 A/s onto each gate dielectric at 80 ◦C
ubstrate temperature at a base pressure of 5 × 10−6 Torr. Finally,
0 nm gold (Au) source and drain electrodes were deposited byhermal evaporation under high vacuum (5.5 × 10−6 Torr) on theentacene film to obtain top contact configuration. A shadow masksed during the Au deposition, defined the channel length (L) and
with n-type F16CuPc and p-type pentacene semiconductors (b). Chemical structure
width (W) as 50 �m and 1000 �m, respectively. Fig. 1b outlinesthe complementary inverter fabricated from p-type pentacene, n-type F16CuPc and D4 gate dielectric. The dielectric solution wasspin-cast on the cleaned ITO coated glass substrate. 50 nm pen-tacene and 35 nm F16CuPc layers were vacuum-deposited at abase pressure of 5 × 10−6 Torr through a shadow mask on the gatedielectric coated substrate. The deposition rate and substrate tem-perature were 0.2 A/s and 80 ◦C for pentacene, and 0.1 A/s and 27 ◦Cfor F16CuPc, respectively. The complementary inverter was com-pleted by the deposition of 50 nm Au onto the semiconductor films.L and W were 250 and 200 �m for the pentacene OFET and 50 and4000 �m for the F16CuPc OFET, respectively.
2.3. Measurements
The surface morphologies of the pentacene layers on the gatedielectrics were characterized by atomic force microscopy (AFM;Nanoscope IIIa, Digital Instruments) in tapping mode under ambi-ent conditions. Fourier transform infrared (FT-IR) spectra wererecorded on a Thermo Scientific FTIR (Nicolet 6700) spectrome-ter in transmittance mode. The gate dielectric films’ water contactangles and surface energies were determined using distilled waterand diiodomethane probe liquids (Kruss, DSA 100). Total surfaceenergy was calculated using Fowkes and Young’s approximation as[28]:
(1 + cos �)�l = 2(�ds )
1/2(�d
l )1/2 + 2(�p
s )1/2
(�pl
)1/2
(1)
where � is the measured contact angle, � l and �s represent thesurface energies of the reference liquid and the polymer, respec-tively, and the superscripts d and p indicate the dispersion andpolar components, respectively. Devices’ electrical characteristicswere measured under ambient conditions (RH ∼ 55% at 30 ◦C) andin a vacuum chamber at ca. 5 × 10−3 Torr using a HP semiconductorparameter analyzer (HP 4145B) controlled by the Labview pro-gram. The gate dielectric films’ thicknesses were measured usingan AMBIOS XP-100 surface profiler. Their leakage currents and
capacitances (at 1 kHz, HP 4294A) were determined under ambientconditions using metal-insulator-metal (MIM; active area, 63 mm2)capacitor-type devices with bottom ITO electrodes and top gold(Au) electrodes.
600 S. Das et al. / Synthetic Metals 162 (2012) 598– 604
Table 1Gate dielectrics’ physical and electrical properties.
ig. 2. Leakage current density vs. electric field for MIM devices with pristine PVPD1) and cross-linked PVP (D2, D3 and D4) gate dielectrics. Inset: The MIM devices’tructure.
. Results and discussion
The bottom-gate, top-contact OFETs and the chemical struc-ures of the gate dielectrics are shown in Fig. 1. Gate dielectricsD2–D4) were prepared by mixing various ratios of PVP and PMFcross-linking agent) in PGMEA. Gate dielectric D1 was preparedithout PMF for comparison. The surfaces and bulk characteris-
ics of the gate dielectrics were analyzed by measuring their water
ontact angles, surface energies, capacitances and leakage currentensities. Water contact angle strongly depended on the dielectrics’hemical composition and increased with increasing PMF content.1 showed a water contact angle of 64◦, which increased to 70◦
ig. 3. Tapping mode AFM images (5 �m × 5 �m) and height profiles of 3 nm pentacenentacene.
49 1.25 × 1057 3.51 × 10−7
61 6.23 × 10−9
(D4), 73◦ (D3) and 75◦ (D2) upon addition of the cross-linker. Thesurface of D1 was more hydrophilic due to its greater presence ofhydroxyl groups. (FT-IR results; Fig. S1, Supporting Information).The peak attributable to OH groups (3400 cm−1) in D1 gradu-ally decreased with increasing PMF content, indicating that the
OH groups decreased upon cross-linking between PVP and PMF,increasing the dielectrics’ water contact angles and decreasing theirsurface energies [29]. The gate dielectrics’ water contact angles andsurface energies are plotted in Fig. S2 (Supporting Information) andare listed in Table 1.
A gate dielectric’s capacitance and leakage current densityare major issues affecting the performance of organic electronicdevices that require gate dielectrics, such as OFETs, complemen-tary inverters and ring oscillators. The dielectrics’ capacitances at1 kHz (Table 1) were measured using MIM devices (inset, Fig. 2).The 91 pF/mm2 capacitance of D1 decreased to 61 pF/mm2 in D4and to 49 pF/mm2 in D2 due to reductions of polar components.Leakage current density depended on the electric field (J–E) appliedto the MIM devices (Fig. 2), with D4 exhibiting the lowest leak-age current density (6.23 × 10−9 A/cm2 at 0.2 MV/cm). D1 showeda much higher leakage current (3.52 × 10−6 A/cm2 at 0.2 MV/cm)due to its less densely packed polymer main chains. The leakagecurrent densities of D2 (1.25 × 10−6 A/cm2 at 0.2 MV/cm) and D3(3.51 × 10−7 A/cm2 at 0.2 MV/cm) were lower than that of D1 but,higher than D4. It may be due to excess cross-linker leading to lessdense packing [21,30].
A gate dielectric’s surface properties affects the initial growthmode and morphology of the semiconductor deposited onto it;the interfacial layers influence charge transport in the resultingOFET [31]. AFM topographic images and height profiles (Fig. 3)were recorded for 3 nm thick pentacene layers deposited on
The growth of pentacene on D1 gate dielectric was based on atwo-dimensional (2D) layer-by-layer growth mode known as theFrank–Van der Merwe mode [32]; the resulting large 2D grains of
e films deposited on (a) D1, (b) D2 and (c) D4 gate dielectrics. Inset: 50 nm thick
S. Das et al. / Synthetic Metals 162 (2012) 598– 604 601
Table 2Performance parameters of pentacene OFETs with different gate dielectrics.
a Ambient conditions: relative humidity (RH) 55% and 30 ◦C.b Vacuum: 5 × 10−3 Torr.
a. 1.53 nm thickness corresponded to the size of the pentaceneolecule [1 monolayer (ML) = 1.5 nm] [33]. Pentacene growth on2 and D4 could be described by the Volmer–Weber growthode of three-dimensional (3D) island growth [34] and resulted in
maller and thicker (8.87 and 8.41 nm for D2 and D4, respectively)rains than on D1. The morphologies of 50 nm thick pentacene lay-rs on the gate dielectrics were also recorded and were almostimilar, showing typical terrace-like structures. These results indi-ate that gate dielectric composition could significantly affect thenitial growth mechanism of pentacene and subsequently deviceerformance (Table 2).
Output characteristic (IDS vs. VDS) curves of pentacene based
FETs with the various gate dielectrics were recorded at gate volt-ges (VGS) of 0 to −40 V with −10 V increments. Measurementsere carried out under ambient (RH ∼ 55%, 30 ◦C) and low-pressure
ca. 10−3 Torr) conditions. Under ambient conditions, except for
ig. 4. Output characteristics curves of pentacene OFETs fabricated with (a) pristine PVPnder ambient (RH ∼ 50% at 30 ◦C) and vacuum (∼10−3 Torr) conditions.
2.16 × 10 −12.82 −6.14 5.87 2.17
the device fabricated with D1 dielectric (no plateaus in the draincurrents in the saturation regime), all devices showed typicalp-type characteristics with clear transitions from linear to sat-uration behaviors. All the devices exhibited clearer linear andsaturation behaviors under vacuum as shown in Fig. 4. At a givennegative gate voltage (VGS), drain current (IDS) initially increasedlinearly with small negative VDS and then saturated at relativelyhigh VDS. Under ambient conditions, the OFETs exhibited higherdrain currents (IDS) at each negative gate voltage (VGS) than whenunder vacuum. The difference of the drain current (�IDS) underambient and vacuum conditions was greatest (8.79 × 10−5 A atVGS = VDS = −40 V) in the OFET using D1 gate dielectric (Fig. 4a). This
was attributed to the previously discussed presence of hydroxylgroups [35]. OFETs’ transfer characteristic (IDS vs. VGS) curves wererecorded as VGS was swept from +20 to −40 V and VDS was set at−30 V. The devices’ performance parameters with different gate
(D1) and (b, c and d) cross-linked PVP (D2, D3 and D4) gate dielectrics measured
602 S. Das et al. / Synthetic Metals 162 (2012) 598– 604
Fig. 5. Transfer characteristics curves of pentacene OFETs with various gated(
duttsctrTds
r(Oiwcgsbadvns
having longer sweep delay than fast sweep rate [38]. Under vac-
ielectrics (D1–D4) measured under (a) ambient (RH ∼ 50% at 30 ◦C) and (b) vacuum∼10−3 Torr) conditions at VDS = −30 V. Drain current is in absolute value.
ielectrics (D1, D2, D3 and D4) under both ambient and vac-um conditions are listed in Table 2. Field effect mobility (�) inhe saturation regime was determined using the following equa-ion: IDS = (WCi/2L)�(VGS − Vth)2, where IDS, W, L and Ci are theaturated drain current, the channel width and length and theapacitance per unit area of gate dielectric, respectively. Devices’hreshold voltages (Vth) were determined by plotting the squareoot of IDS and VGS by extrapolating the measured data to IDS = 0.he inverse subthreshold swing (ss), a measure of how sharply theevice changes from the off state to the on state, was calculated bys = [d log(IDS)/dVGS]−1.
The OFET with D4 gate dielectric exhibited higher on/off cur-ent ratio (ION/IOFF) than the other devices both under ambientFig. 5a) and vacuum (Fig. 5b) conditions. In ambient conditions, theFET with D1 showed the smallest ION/IOFF; the ratio significantly
ncreased when the other, cross-linked gate dielectrics (D2, D3, D4)ere used. Exposure of the OFET with D1 to air led to higher leakage
urrents due to the uptake of water by the hydroxyl groups in theate dielectric [18]. The OFET with D2 or D3 gate dielectric showedmaller on/off current ratio (ION/IOFF) than OFET with D4. This maye due to the excess amount of unreacted cross-linking agent in D2nd D3 which possibly can reduce chain packing density of the gateielectrics as previously discussed in the previous section. Under
acuum (without atmospheric water), all the devices showed sig-ificantly reduced leakage currents, with particular improvementshown by the OFET with D1, indicating that the uptake of water was
Fig. 6. Transfer characteristics curves for pentacene OFETs with (a) D1 and (b)D4 gate dielectrics measured under ambient (RH ∼ 50% at 30 ◦C and vacuum(∼10−3 Torr) conditions. Drain current is in absolute value.
a major issue affecting performance. Subthreshold swing showedsignificant improvements under vacuum for similar reasons. TheOFET with D4 gate dielectric showed the overall best performance(Fig. 5 and Table 2). IOFF and � were smaller when measured undervacuum than when measured under ambient conditions. The OFETwith D1 gate dielectric showed � drop from 0.45 cm2/V s in ambi-ent to 0.13 cm2/V s in vacuum. Negatively charged hydroxyl groupsin PVP have been reported to aid the accumulation of holes and thusincrease � [36].
Transfer characteristic curves (IDS vs. VGS) of pentacene OFETswith D1 and D4 were measured under ambient and vacuum condi-tions with both forward and reverse sweeping (Fig. 6). The devicewith D1 showed much larger hysteresis than that with D4 underambient conditions. The differences of threshold voltage (�Vth)between the forward and reverse directions were 9 V and 4 V fordevices with D1 and D4 dielectrics, respectively. The device with D1dielectric exhibited the largest hysteresis due to its large presenceof OH groups that could facilitate the slow polarization of watermolecules [18,37]. The device with D4 showed less hysteresis due tothe reduction of hydroxyl groups by cross-linking. No considerablehysteresis was shown by either device under vacuum confirm-ing that hysteresis was due to the absorption of water moleculesby hydroxyl groups. Fig. S3 (Supporting Information) shows thetransfer characteristics of the OFET with D4 measured both underambient and vacuum conditions with fast and slow gate sweepingin both forward and reverse directions. Fast and slow sweep rateshaving same hold time but different sweep delay. Slow sweep rate
uum, both fast and slow gate sweeps resulted in transfer curveswithout deviation. Under ambient conditions, slow gate sweepingresulted in greater hysteresis than fast sweeping. This is due to
S. Das et al. / Synthetic Metals 162 (2012) 598– 604 603
Fig. 7. Transfer characteristics curves of the (a) p-type and (b) n-type OFETs in a complementary inverter with D4 gate dielectric. Voltage transfer characteristics (c) of ac ) and
T .
tseddtrrO
acrimswOtos2nucimo
omplementary inverter comprising pentacene p-channel (L = 250 �m, W = 200 �mhe inverter’s circuit design and signal gain. Drain current in (a) is in absolute value
he fact that slow gate sweeping allowed sufficient time for thelow polarized species in the dielectric to respond to the appliedlectric field. This further confirms the role of hydroxyl groups inetermining the hysteresis behavior of OFETs under ambient con-itions. OFETs’ hysteresis has been reported to be strongly relatedo hydroxyl groups in the gate dielectric and has been reduced byeplacing them with cinnamoyl groups [36a]. Based on the aboveesults, the D4 gate dielectric was optimal for the high-performanceFETs.
To investigate the applicability of the D4 gate dielectric indvanced organic devices, an organic complementary inverteronsisting of p-type pentacene and n-type F16CuPc OFETs was fab-icated and analyzed. In an ideal complementary inverter, VOUTntersects VDD/2 when VIN is equal to VDD/2. This requires the perfor-
ance of each OFET to be matched. For this, the same drain currenthould flow through the n- and p-type OFETs from VDD to GNDhen the magnitudes of VGS and VDS are equal to VDD/2 in bothFETs. This can be achieved through modifying the device’s geome-
ry by considering mobility and current level [39,40]. Therefore, then-state current of each OFET was controlled by varying each tran-istor’s channel length (L) and width (W). These were respectively50 and 200 �m in the p-type OFET and 50 and 4000 �m in the-type OFET. Fig. S4 shows the output characteristics of the individ-al pentacene and F16CuPc OFETs in the inverter fabricated on ITO
oated glass substrate. Fig. 7a and b shows the transfer character-stics curves of the pentacene and F16CuPc devices. The calculated
obility (�), on/off ratio, threshold voltage (Vth) and subthresh-ld swing (ss) of the pentacene OFET were 0.45 cm2/V, 7.02 × 103,
F16CuPc n-channel (L = 50 �m, W = 4000 �m) OFETs with D4 gate dielectric. Inset:
−3.4 V and 4.79 V/dec, respectively. In the F16CuPc OFET, thesevalues were 2.34 × 10−3 cm2/V, 1.69 × 104, 3.8 V and 1.62 V/dec,respectively. These values were measured in air at VDS = 30 V (n-channel) and VDS = −30 V (p-channel). Fig. 7c shows the voltagetransfer characteristics (VIN − VOUT) of the complementary inverterfrom 0 to 40 V at a supply voltage (VDD) of 40 V. The insets outlinethe complementary inverter’s logic circuit. The swing range of VOUTwas almost similar to VDD (=40 V), indicating “zero” static powerconsumption in the digital electronic circuit. The voltage transfercurve is close to symmetric, showing symmetric noise margins of15 V and 14 V at low and high voltage, respectively. The invertergain, i.e. maximum voltage gain (�Vout/�Vin), was 6.2 at VIN = 22.5 V(inset, Fig. 7c). The logic threshold voltage (VM) of the complemen-tary inverter was greater than VDD/2 = 20 V due to the differences ofthe two OFETs’ electrical performances [41]. This difference couldbe reduced by further modification of the device’s geometry andthe additional external parameters, such as illumination [42].
4. Conclusion
Four PVP based gate dielectrics with varying concentrations ofcross-linker were tested in OFETs. The dielectrics’ surface tensions,Fourier transform infrared spectra, capacitances and leakage cur-rents were measured. The gate dielectrics showed different surface
and bulk properties that affected pentacene growth and subse-quently OFET performance. A pentacene OFET with D1 showedlarge hysteresis; one with D4 showed relatively small hystere-sis in air. Less hysteresis was shown by all the devices under
6 Metals
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[40] T.D. Anthopoulos, Appl. Phys. Lett. 91 (2007) 113513.[41] T. Ng, S. Sambandan, R. Lujan, A.C. Arias, C.R. Newman, H. Yan, A. Facchetti,
04 S. Das et al. / Synthetic
acuum, indicating that the devices’ characteristics were signif-cantly affected by OH group in the gate dielectric. Use of theptimized gate dielectric resulted in a higher performing OFET. Aomplementary inverter composed of pentacene, F16CuPc and D4ate dielectric showed good voltage transfer characteristics.
cknowledgments
This research was supported by a grant from the Nationalesearch Foundation (NRF) through Basic Science Research Pro-ram (2009-0089650). This work was also supported by Seoul&BD Program (WR090671).
ppendix A. Supplementary data
Supplementary data associated with this article can be found, inhe online version, at doi:10.1016/j.synthmet.2012.01.020.
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