IEEE TRANSAmIONS ON ELECTRON DEVICES, VOL. 41. NO. 3, MARCH 1994 341

Effects of Surface Pretreatment of Polysilicon Electrode Prior to Si3N4 Deposition on the

Electrical Characteristics of Si3N4 Dielectric Films G. W. Yoon, A. B. Joshi, and D. L. Kwong, V. K. Mathews, R. P. S . Thakur, Member, IEEE, and P. C . Fazan

Abstract-Effects of various surface pretreatments of polysili- con electrode prior to Si3N 4 deposition on leakage current, time- dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin SisN4 films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal Hz -Ar clean, and rapid thermal NHs-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H2-Ar clean.

I. INTRODUCTION

HE demanding requirements of advanced high density T DRAM's have led to the development of innovative cell structures [l] , [2] as well as modification of the surface morphology of the poly-Si storage node to increase the surface area for a given cell area [3], [4). High dielectric constant materials [5]-[7] have also been used to increase the cell capacitance. However, it is highly desirable to develop pro- cesses that do not deviate significantly from the conventional methods such as the use of an SiOz/SiSN4 (ON) dielectric film in order to retain process simplicity. Therefore, Si3N4 film still remains one of the most practical storage capacitor dielectric for 256 Mb DRAM's. A storage capacitor structure with dielectrics on rugged poly-Si has been demonstrated to have enlarged effective capacitor surface area and, therefore, is attractive for high density DRAM applications [SI-[ 101. However, for rugged poly-Si, enhanced electron trapping is observed because of the intensification of local electric field and local current density at the tips of the asperities [lo]. This induces a fast breakdown of the bottom native oxide [ll], [12], which imposes a limitation on the long- term reliability of the devices [13]. It has been reported that rapid thermal NH3-nitridation (RTN) of the polysilicon surface prior to the deposition of SisN4 films improves the

Manuscript received March 12, 1993; revised June 28, 1993. The review of this paper was arranged by Associate Editor D. A. Antoniadis. This work was supported by Semiconductor Research Corporation under Contract SRC 93-SJ-278.

G. W. Yoon and D. L. Kwong are with Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712.

A. B. Joshi was with the Dept. of Elect. & Comp. Eng., Univ. of Texas at Austin, Austin, TX, 78712; he is now with Rockwell International, Newport Beach, CA 92658.

V. K. Mathews, R. P. S. Thakur, and P. C. Fazan are with R & D, Micron Semiconductor Inc., Boise, ID 83706.

IEEE Log Number 9214405.

TABLE I

I quality of Si3N4 film and/or interface characteristics [ 141. However, a comparative and systematic study of the effects of various surface pretreatments prior to Si3N4 deposition on the electrical characteristics of the film has not been done for rugged poly-Si and smooth poly-Si. In this paper, we report the effect of various surface pretreatments, consisting of different combinations of HF clean, rapid thermal H2-Ar clean and RTN, on the electrical characteristics of Si02/Si3N4 films on rugged and smooth poly-Si. Results show that pretreatments with RTN lead to lower leakage current, reduced electron trapping, and superior time-dependent breakdown (TDDB) characteristics as compared to those with rapid thermal H2-Ar clean.

11. EXPERIMENTAL Silicon wafers @-type, 150 mm) with -2000A of Si02 were

used as substrates for depositing rugged and smooth poly-Si layers that formed the bottom electrode of the capacitors. The rugged and smooth poly-Si layers were deposited by LPCVD at 565" C, and 625OC, respectively, with deposition pressure of -80 mTorr [15]. Prior to Si3N4 film deposition, various surface pretreatments (I, 11, and 111) were performed. The secondary ion mass spectroscopy (SIMS) analysis showed that the addition of the rapid thermal H2-Ar clean to the RTN process reduces the oxygen levels at the silicon nitride/silicon dioxide interface. The rapid thermal H2-Ar clean further removes oxide present on the surface after an HF clean. Details of the pretreatments are shown in Table I. In this experiment, rapid thermal H2-Ar clean was performed to reduce the native oxide after HF clean. In addition to the elimination of low grade native oxides by HF etch, the altered bonding arrangement on the surface by rapid thermal H2-Ar clean and/or RTN may be expected to cause the homogeneous nucleation and growth of the Si3N4 film itself 1141. After these pretreatments, SisN4 films were deposited in an LPCVD fumace with deposition pressure of 200 mTorr at 680OC

0018-9383/94$04.00 0 1994 IEEE

348 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 3, MARCH 1994

using SiH2C12 and NH3 (SiH2Clz/NH3=1/3). After Si3N4 film deposition, the top oxide was formed through the wet reoxidation process at 8OOOC used for filling the pinholes in the Si3N4 films. The capacitor structures were completed by depositing top poly-Si at 625OC, doping, and patteming. Both top and bottom poly-Si layers (-1000A ) were PH3-doped at 860°C after LPCVD deposition. Wafers with the three surface pretreatments were processed together through the Si3N4 deposition with the expectation that surface modifications by the pretreatments would translate into corresponding improve- ments in the electrical characteristics of Si3N4 film capacitors. The wafers were exposed to the atmosphere between the HF clean and the rapid thermal treatments (H2/Ar or RTN) and also between the rapid thermal treatments and Si3N4 film deposition (LPCVD). The in-situ RTN was performed after the rapid thermal H2-Ar clean for the pretreatment 11.

High-frequency C-V at 100 kHz and current-voltage (I-V) measurements were measured on 6.5 x lop5 cm2 capacitors. Time-dependent dielectric breakdown (TDDB) measurements were done on 2.2 x cm2 capacitors. C-V measurements [ 161 revealed that the oxide-equivalent-thicknesses of Si3N4 stacked layers on the smooth and rugged polysilicon were -60 8, and -35 A, respectively. The equivalent oxide thickness has been calculated using the same planar area (not actual surface area) for both the smooth and rugged polysilicon capacitance. Therefore, the higher capacitance (on a given planar area) obtained for the rugged polysilicon capacitors gives rise to a smaller equivalent oxide thickness, even though the physical thickness of the silicon nitride film is the same for both capacitors.

111. RESULTS AND DISCUSSION

Fig. l(a) and (b) show the current density versus electric field (J-E) characteristics of capacitors with smooth and rugged poly-Si bottom electrodes under positive gate and negative gate biases, respectively. Capacitors on rugged poly-Si show somewhat higher leakage current than those on smooth poly-Si for all pretreatment conditions. The leakage current through the Si gNq film is limited by Frenkel-Poole conduction mechanism which is not so sensitive to the electric field and, therefore, this enhancement of leakage current is mainly attributed to the enlarged capacitor area (-73%, obtained from C-V measure- ments) [ 3 ] , [8]. Capacitors with RTN steps show a slightly lower leakage current density compared with those with rapid thermal H2-Ar steps.

The results from C-V and I-V measurements are shown in Fig. 2 in the form of capacitance per unit area vs. voltage at leakage current density of 1pA/cm2 plots. The leakage current limit of 1 pA/cm2 is based on design and operational parameters for DRAM’S [5]. For rugged poly-Si, pretreatments I and I11 result in more and less leakage current than pretreat- ment 11, respectively. For the smooth poly-Si, pretreatments I1 and I11 show comparable capacitance and leakage current while pretreatment I results in a slightly higher leakage for a fixed capacitance. The RTN treatment has been observed to be more effective in reducing the leakage current on smooth poly- Si when compared to the rugged poly-Si. The decrease in the

2 Effective Electnc Field (MV/cm)

(a)

0 2 4 6 8 1 0 1 2 Effective Electric Field (MV/cm)

(b)

Fig. 1 . Current density versus electnc field (J-E) charactenstics of smooth and rugged poly-Si for pretreatments I, 11, and 111 under (a) positive gate bias and (b) negative gate bias.

0 0 Pretreatment 11 Pretreatment 111

4 5 6 7 8 9 1 0 1 1 1 2 1 3 Capacitance (fF/pm*)

Fig. 2. Critical voltage to induce a leakage current density of 1 pA/cm2 versus capacitance per unit area for pretreatments I, 11, and 111 in both smooth and rugged poly-Si structures.

leakage current is believed to be caused by an improvement in the quality of the silicon nitride film as well as the elimination of the inferior quality silicon dioxide-silicon nitride transition layer. On the rugged poly-Si, the surface area is much larger for a given planar area and should, therefore, be expected to be more influenced by the RTN treatment. However, the observed lack of significant improvements could be due to the fact that the increase in the leakage current caused by the field enhancement at the tip of the asperities for the rugged poly-Si overwhelms the gains from the RTN process. The result shows that RTN step in pretreatment plays a crucial role in reducing the leakage current, which is affected by interfacial oxide quality and/or altered bonding arrangements

YOON et al.: EFFECTS OF SURFACE PRETREATMENT OF POLYSILICON ELECTRODE 349

between the bottom poly-Si and the Si3N4 film. It is known that the current conduction in Si3N4 is dominated by the flow of holes [17], [18] and that the carrier transport can be influenced by the presence of an oxide layer at the anode [19], [20] which impedes the injection of holes into the nitride film. Therefore, elimination of the bottom oxide by the pretreatments should lead to an increase in the leakage current [20]. Our results, however, show that the leakage current is reduced by pretreatments consisting of RTN. It is believed that RTN reduces the Frenkel-Poole trap assisted current through the Si3N4 films by the elimination of interfacial Si rich region of Si3N4 film due to the preferential reaction of nitridation species with excess Si [12].

The charge trapping characteristics for smooth poly-Si ca- pacitors were studied by measuring the change in capacitance (AC/C,lV, = OV) during constant electric field stress (IE,fff( = 10 MV/cm) for both gate polarities [13]. The decreased capacitance observed for both gate polarities indicates that the trapped electrons overwhelm the effect of trapped holes in determining capacitance change, since dominant hole trapping would increase the capacitance [13]. The capacitance loss af- fects the long term reliability of the devices because it implies the loss of charge storage and, consequently, degradation of refresh time. As shown in Fig. 3, charge trapping is strongly influenced by the pretreatment conditions. Pretreatments I and I1 show more and less electron trapping than pretreatment 11, respectively. In addition to reducing the native oxide at the interface, the RTN process provides a surface that is more conducive to the homogeneous nucleation and growth of the Si3N4 film. This improves the quality of the Si3N4 film and also eliminates the silicon dixoide-silicon nitride transition layer, both of which reduce the electron trapping in the film [21]. Due to suppressed electron trapping in Si3N4 films on RTN-treated smooth poly-Si, capacitors with RTN are believed to have smaller stress-induced loss of capacitance. This result shows that RTN is a very effective method to suppress the charge trapping in order to improve long-term reliability of ultrathin Si3N4 films. It is inferred from Fig. 3 that rapid thermal H2-Ar treatment, unlike RTN treatment, degrades the electrical properties such as leakage current and charge trapping. Even though the role of hydrogen is not clearly understood here, the degradation is speculated to be partly due to localized states related to Si-H bonds in Si3N4 film which is known to act as electron traps [22], [23]. In a process with only HF clean, the hydrogen terminated passivation layer is lost when it is exposed to temperature above 500°C. The effect of the small amount of hydrogen (10%) in the rapid thermal H2-Ar clean will be difficult to isolate from this set of tests. The improvement in the electrical characteristics is believed to be caused by the elimination of the inferior silicon dioxide-silicon nitride transition layer as well as the better quality of the silicon nitride film itself obtained through homogeneous nucleation and growth [ 121, [ 141. From this standpoint, the order of pretreatments for better electrical characteristics should be pretreatments 11, 111, and then I. However, for the hole-dominated current conduction in Si3N4 film, an oxide layer at the anode can provide a barrier to carrier injection into the film. From this standpoint, the capacitors

Solid Symbol V, Strev 1 Open Symbol +V, Stress

5 LLvLpl I L Y I

10' 1 02 1V Stress Time (s)

"

Fig. 3. Capacitance change (AC/Co) at 1; = 0 V as a function of stress time under both positive and negative gate biases for pretreatments I, 11, and 111 in smooth poly-Si structure.

with pretreatment I should be best since it will have the thickest oxide at the interface. But, its electrical characteristics are degraded by the inferior quality of Si3N4 film obtained by heterogeneous nucleation and growth. Between pretreatment I1 and 111, the pretreatment 111 (HF + RTN) would have a slightly higher oxygen level at the interface than pretreatment I1 (HF + H2-Ar + RTN) and should, therefore, give better electrical characteristics. It is not known how this small level of oxygen affects the quality of the deposited Si3N4 film, but it does not seem to be very significant.

Charge trapping characteristics for the capacitors are also studied by measuring the shift in gate voltage (AV,/V,,,) extracted from +V, I-V measurements before and after a constant electric field stress (E,E = -11 MV/cm). The results for capacitors on smooth and rugged poly-Si are shown in Fig. 4(a) and (b), respectively. Each data point represents a mean of 3 data points, distributed over a very narrow range. The missing data point in Fig. 4(b) for pretreatment I is due to short time-to-breakdown ( t ~ o ) of that sample. Capacitors with RTN show smaller negative voltage shifts than those without RTN. This trend is consistent with that observed from Fig. 3, i.e., less electron trapping in RTN-treated films. Larger electron trapping in Si3N4 films on rapid thermal H2-Ar treated poly-Si is also evident from larger magnitudes of AVg/Vq,o in Fig. 4.

TDDB characteristics under constant electric field stress (IEeffI = 1 2 MV/cm) for the smooth and rugged poly- Si were compared for both gate polarities by plotting time to 50% failure (time needed for 50% capacitors to show dielectric failures) for various pretreatments, as shown in Fig. 5. Pretreatments I and I11 give shorter and longer ~ B D than pretreatment 11. It is noted that the capacitors with less electron trapping show longer time-to-breakdown ( t ~ o ) for smooth and rugged poly-Si. It has been reported that charge trapping near the injecting electrodes during stress causes the field build-up in the bulk Si3N4 film, which eventually leads to the breakdown [24]. Thus, less electron trapping in RTN-treated films can partly explain the longer t B D . In addition, RTN is believed to reduce interface defects such as Si dangling bonds and/or Si-0-Si strained bonds [25], which, in turn, would further decrease the tendency for Si-0 bond breaking that has been postulated to result in dielectric breakdown [12], [26]. For rugged poly-Si, t g ~ under negative bias on the top poly-Si electrode is longer than that under positive bias, unlike the case of smooth poly-Si. This reversal of trend is believed to be due

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41. NO. 3, MARCH 1994 350

3 I a 2 5 . Smooth Poly S I 1

n i n 0 zoo 300 400 so0 600

Stress Time (s)

(a)

125

- 100

7 5

- 2

s” 5n

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3

9

.

- r %etCa2&t I

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‘ I MV’m ~

A * I r

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Rugged Poly Si 1 0 L L li, _I I - i

o 100 200 300 400 sno 600 Stress Time (s)

(b)

Fig 4 Gate voltage shift (AVg/\\ 0) as a function of stress time under negative gate bias for pretreatments I, 11, and 111 in (a) smooth poly-s~ and (b) rugged poly-Si structures

104 ~ - 1 V, Stress U$,, I = I2 hlV/cni +

w - Stre” /Smooth

C I

Pretreatment Condition Fig, 5. Time to 50% failure versus pretreatment conditions under both positive and negative gate biases in both smooth and rugged poly-Si structures.

to the much severe surface asperities of rugged poly-Si surface [3], [8]. Time to 50% failure shows a strong dependence on the surface pretreatment condition under negative bias for both rugged and smooth poly-Si, while it has only a slight influence under positive bias.

IV. CONCLUSION The effects of surface pretreatments on the dielectric char-

acteristics of thin SisN4 films on smooth/rugged poly-Si were studied. Prior to the deposition of the SisN4 film, various surface pretreatments with different combination of HF clean, rapid thermal H 2-Ar clean, and rapid thermal NHa-nitridation ( R T N ) were applied. Results show that pretreatments with RTN effectively reduce leakage current, suppress charge trap- ping, and improve TDDB characteristics of thin Si3N4 films on

both smooth and rugged poly-Si. Rapid thermal H2-Ar clean, on the other hand, has detrimental effects on the electrical properties.

REFERENCES

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[24] S. B. Bibyk, “Charge trapping kinetics in silicon nitride films,” in Proc. Symp. Silicon Nitride and Silicon Dioxide Thin Insulating Films, V. J. Kapoor and K. T. Hankins, Eds. Pennington, NJ: The Electrochemical Soc., p. 10, 1987.

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[26] Y. Ohji, T. Kusaka, 1. Yoshida, A. Hiraiwa, K. Yagi, and K. Mukai, “Re- liability of nanometer thick multilayer dielectric films on polycrystalline silicon,” in Proc. Int. Rel. Phys. Sympo., pp. 55-59, 1987.

Viju K. Mathews was born in Bombay, India, in 1959. He received the B. Tech degree in metal- lurgical engineering from the Indian Institute of Technology, Bombay, India, in 1982, and the M.S. and Ph.D. degrees in materials science and engineer- ing from the University of Kentucky, Lexington, KY, in 1984 and 1988.

He joined the Research and Development group at Micron Semiconductor in Boise, ID, in 1989, as a Process Development Engineer. He has worked on various aspects of semiconductor technology,

including silicon substrates, intrinsic gettering, and high pressure processing. He has published more than 40 technical articles and has several patents issued or pending in the areas of module development and integration for DRAM’S and SRAM’s. His current research interests inlude advanced devices, isolation processes, DRAM cell structure, and metallization technologies.

‘-

Giwan Yoon was bom in Pohang, South Korea, on April 5 , 1959. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1983, and the M.S. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology in 1985.

From 1985 to 1990 he was with the Goldstar Co., Seoul, where he researched and developed a process for bipolar devices. He is currently a Ph.D. student at the Universitv of Texas at Austin. TX. . .

where he is engaged in the research and development of ultrathin alternative gate dielectric films for MOS devices and high-dielectric-constant materials for DRAM applications.

Aniruddha B. Joshi was bom in India on May 8, 1966. He received the B.Tech. degree in electrical engineering and the M.Tech degree in microelec- tronics from the Indian Institute of Technology, Bombay, in 1987 and 1989, respectively. He is now a Ph.D. student at the Microelectronics Research Center at the University of Texas at Austin. His current research interests include hot-carrier phe- nomena in submicrometer MOSFET’s and inves- tigation of performance and reliability of alternate MOS gate dielectrics, with a focus on reoxidized nitrided oxides.

Dim-Lee Kwong was bom in Taiwan, Republic of China, on October 20, 1954. He received the Ph.D. degree in electrical engineering from Rice University, Houston, TX, in 1982.

He is currently a Professor of Electrical and Computer Engineering and the Microelectronics Re- search Center at the University of Texas at Austin. His primary research interests include rapid thermal processing-CVD technology for the growth and deposition of semiconductor materials compatible with ULSI processes, processing, and characteriza-

tion of ultrathin dielectrics for ULSI applications, thin films and interfaces, Ge,Sil,/Si heterojunction and optoelectronic devices, light emission from porous Si, hot-carrier effects, DRAm storage dielectrics, and diffusion mod- eling of ion-implanted impurities during RTA. He has publisher over 180 refereed journal articles and has been granted several patents.

Randhir P. S. Thakur (S‘87-M‘92) was bom in Himachal Pradesh, India, in 1962. He received the B.S. (hons) degree in electronics and communica- tion engineering from Regional Engineering College in Kurukshetra, India, and the M.S. degree from the University of Saskatchewan in Saskatoon, Canada. He received the Ph.D. degree in electrical engineer- ing from the University of Oklahoma, Norman, OK, in 1991.

He joined Micron Semiconductor, Inc., in Boise ID, in 1991, where he has been responsible for

implementing stand-alone single wafer rapid thermal processing (RTP) and CVD technologies as modules to advanced DRAM and SRAm processing. His current research interest involved reduced temperature processing for submicron devices. He has contributed more than 40 articles to professional journals and conferences and has several patents issued or pending.

Dr. Thakur was twice a recipient of a research award from the American Vacuum Society (NM chapter). He is a member of the Electrochemical Society, MRS, and SPIE.

Pierre C. Fazan received the B.S., M.S., and Ph.D. degrees in physics from the Microelectronics Insti- tute of the Swiss Federal Institute of Technology, Lausanne. Switzerland, in 1984, 1985, and 1988.

He joined Micron Semiconductor in 1989, where he is now Manager of the Module Integration Group in Micron’s R&D Process Development department. He manages and leads projects that develop ad- vanced isolation structures, new cell dielectrics, high dielectric constant materials, new gate dielectrics and passivation structures, advanced stacked DRAM

cell concepts, and SRAM TFT’s. He also developed Micron’s Textured STacked Capacitor Structure (TSTC). He is the author or coauthor of more tahn 30 technical papers and holds 21 US patents in semiconductor processing and DRAM cell structures