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Efficiency Optimization In Data Center - From Packaging to Solution PwrSoC, 2018 Hsinchu Presented by: Haoyi Ye Delta Electronics
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Page 1: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Efficiency Optimization

In Data Center

- From Packaging to Solution

PwrSoC, 2018

Hsinchu

Presented by: Haoyi Ye

Delta Electronics

Page 2: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Data Center Power Trend and Architecture

High Efficiency Power Packaging & Integration

Application Case: 48V Solution for Server

Contents

Page 3: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

AI

Image Recognition

NLP

Unmanned Vehicle

Industry 4.0

Smart City

AI is Changing the World

Cloud

Page 5: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Very flexible architecture

2-Stage Power Architecture for AI Processor

>20A

Vin6V Bus

0.6-2V

>100A

>20A

<2A

<2A

>3A

>3A

DC/DC module

Page 6: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Low Voltage Bus for System Efficiency

-0.2%

DCDC module Efficiency @ 48Vin

Vo = 6V

Vo = 12V

DCDC module efficiency slightly drop from 12Vo to 6Vo

Buck efficiency significantly increase from 12Vin to 6Vin

Buck Efficiency (%) @ 1.8Vo

0 10 20 30 40 50 60 70 80 90 100 110

Load Current (A)

+1.7%

Vo = 4V

System Efficiency optimization by low voltage bus

Vin = 8V

Vin = 6V

Vin = 12V

Page 7: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Data Center Power Trend and Architecture

High Efficiency Power Packaging & Integration

Application Case: 48V Solution for Server

Contents

Page 8: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Buck Losses and Key Parameters

100m

R6

C9

10u

C8

10u

C7

10u

_

Q5_

Q6

C6

1u

C5

1u

_

Q1

_

Q2

450p

L2

440u

R1

C4

10u

_

Q4

_

Q3

1.2n

L4

1.2n

L5

100m

R7

Switch ringing loss

Loop inductance is the key parameter for buck efficiency

Body diode

conduction lossBody diode reverse

recovery loss

Page 9: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Embedded DrMOS

Smaller loop inductance, lower switching loss

• Switching loop inductance: 50% decreasing

• Driver loop inductance: 50% decreasing

140u

R11

250p

L10

C10

1u

C11

1u

47m

R8

C12

10u

_

Q7_

Q8

C13

1u

C14

1u

_

Q9

_

Q10

C15

10u

_

Q11

_

Q12

600p

L8

600p

L9

47m

R10

450p

L7

440u

R9

C16

1u

C17

1u

Die

Embedded DrMOS100m

R6

C9

10u

C8

10u

C7

10u

_

Q5_

Q6

C6

1u

C5

1u

_

Q1

_

Q2

450p

L2

440u

R1

C4

10u

_

Q4

_

Q3

1.2n

L4

1.2n

L5

100m

R7

DrMOS

Die

Page 10: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Efficiency improved at different frequency

30A Load

25A Load

Efficiency curve w/ different package

Efficiency Improvement (%)Efficiency (%)

Vin=12V

Vout=1.8V

Load(A)

Fs=2MHz

Efficiency Improvement

The higher fs or load current, the more improved

Fs(MHz)

+0.4%

Page 11: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

VRM Integration

High density integration of high performance device, packaging and magnetics

VIN

BST

SW

PGND

VIN

VOUT

2-Phase Buck Module

Vin 5 - 7.5V

Vo 0.8 – 1.8V

TDC 60A

Footprint 10*10mm

Height 10 mm

DrMOS

Page 12: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Data Center Power Trend and Architecture

High Efficiency Power Packaging & Integration

Application Case: 48V Solution for Server

Contents

Page 13: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

2-Stage Solution for 48V Server

48V 6V

12V

Mainboard

High density VRM/PoL

Good efficiency

Good transient

response

Compact

footprint

Buck

CPU

DDR4

DDR4

PCH

Others

DCDC PCIe/HDD

500W

DCDC

Page 14: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

Proposal Placement

主板

48V

1.2V

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

1.2V

1.8V

DDR4

DDR4

Buck

Buck

Buck

Buck

Buck

Buck

Buck

Buck

6V

Narrow solution Closer to CPU

500W

DCDC

CPU

Page 15: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

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23.78mm36.86mm

Reference

PDN

Proposed

PDN

PDN Modeling and Calculation

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 50 100 150 200

0.0%

0.1%

0.2%

0.3%

0.4%

0.5%

0.6%

0 50 100 150 200

Power saving

P(W)

I(A) I(A)

Eff. benefit

0.4%

@ 145A

0.5%

@175A

Minimum PDN losses, efficiency improvement

1W

@ 145A

1.5W

@175A

Rdc = 536uOhm Rdc = 489uOhm

Page 16: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Delta ConfidentialPwrSoC 2018

AI

IR

NLP

Unmanned Vehicle

Optimize AI Infra with Power Solution

Industry 4.0

Smart City

Cloud

Device level

Convertor level

System level

Page 17: Efficiency Optimization In Data Center - From Packaging to ...pwrsocevents.com/wp-content/uploads/2018-presentations/live/6.1-HaoYi Ye.pdfData Center Power Architecture Evolution More

Smarter. Greener.

Together.

Your questions?

To learn more about Delta, please visit

www.deltaww.com.


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