Efficient and Flexible Dynamic Reconfiguration for Multi...

36 Journal Integrated Circuits and Systems 2009; v.4 / n.1:36-44

Efficient and Flexible Dynamic Reconfiguration for MultiContext Architectures

Julien Lallet, Sébastien Pillement, Olivier Sentieys

INRIA Rennes - Bretagne Atlantique, Université de Rennes, F-22300 Lannione-mail: [email protected]

1. INTRODUCTION

Systems on Chip (SOC) are generally based onthree main kinds of architecture. First, Application-Spe-cific Integrated Circuits (ASIC) allow to efficiently com-pute an algorithm due to dedicated hardware but areunfortunately inflexible. Secondly, Generic Purpose Pro-cessors (GPP) are the most flexible architectures, butcompute in an inefficient way. Finally, static reconfig-urable architectures such as Field-Programmable GateArray (FPGA) are considered as a good compromisebetween processors and ASIC. Meanwhile, mixed archi-tectures have been developed in order to improve theefficiency and the performance of GPP by the use of stat-ic reconfigurable co-processors. These static reconfig-urable co-processors embedded into an SoC, namelyembedded-FPGA (e-FPGA), have allowed GPP to fol-low application developments. Dynamic reconfigurationallows partial configurations at run-time, and thusimproves performances. Some specific processors andFPGAs take advantage of dynamic reconfiguration intheir architecture by the use of the multi-context process.This architectures are either Dynamically ReconfigurableProcessors (DRP) or Dynamically ReconfigurableFPGAs. This is achieved by the local storage of any pos-sible context. When a new configuration is required, the

system switches between one or the other context. Themajor drawback of this solution is the silicon area andpower inefficiency caused by local memories needed tostore all the contexts. Our contribution to multi-contextDRA is the definition of a flexible and optimized struc-ture that supports dynamic, partial and run-time recon-figuration dedicated to both finegrain and coarse-grainDRA structures. This is performed by only two configu-ration memories, one current configuration memory andone parallel configuration memory. The parallel configu-ration memory is used for loading or saving contexts forpreemption to or from the configuration memory in oneclock cycle. New contexts are stored in this parallel con-figuration memory thanks to a splittable scanchain.Compared to previous multi-context Dynamically Re-configurable Architectures (DRA), configurations exploitefficiently the available silicon resources and enables theimplementation of any kind of computing granularity.

The paper is structured as follows. Section 2describes related works on optimization of multi-con-text DRA. Section 3 presents our contribution ondynamic reconfiguration processes of DRA. In Section4, we present the experimental method and discussresults on a WCDMA receiver implementation on an e-FPGA and on the dynamically reconfigurable processorDART. Finally, Section 5 sums up this paper.

ABSTRACT1

Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of theused methodology used consists in the use of multi-context architectures. Unfortunately, the multi-ple contexts bring power and area overhead. This paper introduces the Dynamic Unifier andreConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfigura-tion on both custom designed fine-grain and coarse grain architectures. The DUCK allows to sepa-rate the configuration path and the configuration registers which facilitates simultaneous configura-tion and computing steps. The reconfiguration process is presented in detail, and synthesis resultsare given for different structures. Our solution is finally validated with the implementation of aWCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGAand on the dynamically reconfigurable processor DART.This implementation demonstrates the inter-est and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.

Index Terms: Dynamically reconfigurable architectures, Multi-context.

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Efficient and Flexible Dynamic Reconfiguration for Multi Context ArchitecturesLallet, Pillement & Sentieys

2. RELATED WORKS

For a decade, many dynamically reconfigurablearchitectures have been developed but only a few can beconsidered as multi-context architectures, as they locallystore one or more parallel contexts. NEC-DRP [7] is amassively parallel processor architecture. Reconfigu-ration processes are managed by a central managerwhich can select one futur context from 16 multi-con-textmemories. For the architecture XPP [13] (eXtremeProcessing Platform), dynamic reconfiguration is man-aged by a hierarchical manager composed of a tree ofsub-managers. A cache memory placed in parallel of theconfiguration memory enables multi-context reconfigu-ration. The Adres architecture [14] (Architecture forDynamically Reconfigurable Embedded Systems) storesits configuration either in a RAM configuration memo-ry or in the hierarchical memories for bigger configura-tion spaces. The main constraint of these architecturescomes on one hand from the few flexibility offered bythese architectures in terms of computing granularity,and, on the other hand, from the fact that this architec-tures do not to achieve an efficient reconfiguration fromtheir parallel memory.

The only fine-grain architectures which imple-ment dynamically reconfigurable computing are multi-context FPGAs. Commercial FPGAs (e.g. Xilinx Virtexfamily) allow dynamic reconfiguration, but the reconfig-ured resources have to be stopped before a new config-uration can be propagated [2]. Different approacheshave been proposed in the literature to reduce the exces-sive silicon area used by multicontext FPGAs. First,some works focus on the reduction of the configurationwords. In [6], the method consists in the limitation ofthe connection map inside a switch box. In [1], theauthors reduce the context memory by using redundan-cy and regularity in the configuration data. The firstmethod has the disadvantage to reduce routability. Thesecond is efficient only in good conditions of redundan-cy and regularity, which is not the case for all applica-tions. The second approach [3] is a technological solu-tion which consists in the use of DRAM memoriesinstead of SRAM usually implemented for storing con-figuration contexts. This allows to save between 10%and 60% transistors, but causes a new problem concern-ing mixed process of DRAM and logic.

3. EFFICIENT DYNAMIC RECONFIGURATION

In this section, we present the resource that is pro-posed to make the reconfiguration efficient and flexible,whatever to the granularity of the computing resource.

A. DUCK: Dynamic Unifier and reConfigurationblocK

As mentioned in Section 2, multi-context recon-figuration has provided solutions for fast reconfiguration

but generates redundant resources (local context mem-ories) which contributes to a power inefficient designeven if some solutions have been developed. However,the solution that we propose in this paper needs onlyone context memory for each resource, independentlyof the granularity of the computing resource. But, usingonly one context memory means that it is necessary todevelop other architectural concepts in order to main-tain the timing constraints and the flexibility required bytoday’s applications. The first concept of our contribu-tion consists in the isolation of the configuration pathsand the configuration resources which allows to preparenew contexts during the computation. The DynamicUnifier and reConfiguration blocK (DUCK) is in chargeof the configuration path and has to swap the requiredcontexts to the configuration registers when needed.The second concept consists in the possibility to split theconfiguration path while maintaining a unique comput-ing path in order to propagate the configurationthrough several configuration paths at the same time.Each configuration path composes a reconfigurationdomain. Figure1 shows an example of the implementa-tion of the DUCK concept. This basic example imple-ments interconnection units (Iu), computing units (Cu),input and ouput units (IOu) and reconfiguration units(Ru) namely the DUCK resources. For each units (Iu,Cu or IOu) one DUCK (Ru) is associated and compos-es the configuration path (black arrow in bold print).The inputs of the two configurations paths are repre-sented by the name ConfigIn(i) and the outputs by thename ConfigOut(i). When the system is ready to recon-figure, each DUCK swaps the configuration contextfrom its internal registers to the control registers of eachunit. Once the configuration is swapped, it is possible toextract the context through the configuration path.

Figure 1. Example of a DRA composed of several kind of resources

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B. Dynamically Reconfigurable Architectures

According to the resource to reconfigure, theDUCK implement different functions. In our DRAmodel, the communication resources, called DyRIBox(Dynamically Reconfigurable Interconnection Box),switch signals from input ports to output ports. EachDyRIBox has ni inputs and mi outputs on b bits ateach i of its four sides (North, South, West, East). Thetotal number of input and output ports is therefore

respectively. Depending on thevalue of the configuration register, each input can beconnected to one or several outputs. To reduce thecomplexity and the size of the configuration stream ofthe DyRIBox, the number of inputs that can beswitched to an output is set to P, with P ≤ N.Therefore, the DyRIBox contains M configurationregisters of [p = log2 P] bits.

In case of classical dynamic reconfiguration, thereconfiguration time is too long for the given timingconstraints. To reduce this time, the reconfigurationprocess of the DyRIBox and of the computingresources is based on DUCK context registers (Figu-re2). Each configuration register is connected to onecontext register contained in the DUCK resource anddata could be swapped when needed.

In order to manage the reconfigurationprocess, all DUCK registers are interconnectedthrough a scanpath bus. Scanpath registers are used indesign-for-test (DFT) techniques instead of classicalregisters in order to extract the register value at anytime. The scanpath bus creates a unique big shift reg-ister with all the scanpath registers of the architecture.Thus, the extracted data flow is compared with thetest vectors during testing to detect errors in the com-puting path. This method has been cited in [4] forapplying preemption in reconfigurable architecturesbut has not yet been implemented. This was due tothe fact that the extraction time was too long for thegiven timing constraints required by today’s applica-tions.

The use of the configuration path in a scanpathmanner associated with the DUCK concept allows thesystem to be reconfigured in one clock cycle. The useof the DUCK registers allows the system to preparethe next configuration while it is computing. Thepropagation of a new context is done by three differ-ent steps. First, the configuration registers are alreadyloaded with the current context (Figure2(a)). TheDUCK registers are waiting for the next step. Eitherthe new configuration is already propagated, or iswaiting to be configured. The second step (Figure2(b)) shows how a new configuration is spread to theDUCK registers. As explained before, the DUCK isconnected in a scanpath manner which allows to prop-agate the next context. In case of preemption, theprocess is still the same for extraction of the previouscontext. Finally, each DUCK register swaps its datawith the configuration register. Every configurationregister is directly connected to a DUCK register. It isnoteworthy that in case of a new configuration identi-cal to the current one, the configuration swap doesnot disrupt the interconnection and computingresource behavior. Therefore, reconfiguration is possi-ble even if a computing datapath crosses a reconfigu-ration area which it does not belong to.

Today’s SOCs use very different kinds of com-puting resources, so that, for every new dynamicallyreconfigurable architecture or computing resources, itbecomes more difficult to extract an homogeneousreconfiguration protocol. The DUCK aims to solvethis issue. For example, considering a classical logiccell (gray area on Figure3) several resources are part ofit. The reconfiguration path (area A) allows to set orreset the output register, to select the sequential orcombinatorial output, and to select the carry input.The memory area ( B ) allows to use the logic cell asa RAM memory. The carry resources are needed forarithmetic operations (area C ). The LUT resourcesare needed for the implementation of logical functions(area D ).

Figure 2. Reconfiguration process inside the DUCK structure

N = Σi= 0

3 ni and M = Σi = 0

3 mi

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The configuration path goes through all configura-tion registers and LUT registers. In this example, one logiccell needs 20 clock cycles to be reconfigured. Thus, for ane- FPGA composed of a n·m array of logic cells, n·m·20clock cycles are needed to reconfigure the whole FPGA.This time is not acceptable for fast reconfiguration. Oursolution, the DUCK (area E of Figure3) allows to shift theconfiguration context locally in the same way as for theDyRIBox and to swap the reconfiguration when needed.Therefore, the whole embedded FPGA can be reconfig-ured in 20 clock cycles. In the DUCK, a counter selectseach configuration register one after the other and shifts itto the logic cell configuration path.

C. Results and Exploration

We present here exploration results on theDUCK parameters. First, synthesis results are given toestimate the impact on silicon area of the size of out-puts and inputs, and the number of possible connec-tions to one output. The critical path and power con-sumption are also analyzed. All results are expressed asa function of the computing data bitwidth. Results areobtained with the synthesis tool Design Compilerfrom Synopsys and for a 130nm CMOS technology.

The influence of DUCK parameters on designarea, power and critical path is given in Figure4. Theresults have been obtained by changing the number ofoutputs on the DyRIBox. First, the DUCK has clearly noinfluence on the critical path results because of the phys-ical separation of the configuration path and the config-uration registers in the DyRIBox. Secondly, the moreconnection possibility the DyRIBox has, the less impactthe DUCK has in the design area. This is explained bythe fact that the silicon area used for the interconnectionwires between inputs and outputs grows faster than thesilicon area used by the configuration/DUCK memories.Due to custom libraries used for 8-bit words, the powerconsumption is better controlled from this bitwidth thanfor 4-bit data.

The interconnection network presented in [9]consists in a set of reconfigurable circuit-switchedrouters interconnected by links. One router is com-posed of five 16-bit bidirectional ports connectedthrough a 16x20 fully connected crossbar. We havegenerated and synthesized a DyRIBox associated to aDUCK with the same functionality. The results aregiven for the 130 nm CMOS technology from STMicroelectronics. Area, frequency and power aftersynthesis are given for the two solutions in Table I.These results show that the simplicity of our solutionallows to keep as many flexibility as in their solution,whereas our structure has only 4% area overhead anda gain of 25% on the critical path and of 69% in power.

Figure 3. Simple logic cell architecture developed for fast reconfiguration

Figure 4. Influence of DUCK on area, power and time

Table I. Synthesis results compared with the 4S projects solution

Interconnection Area Critical Powerin mm2 Path in ns in mW

4S project 0.0506 930 17.32DyRIBox 0.0526 692 7.22



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In conclusion, fast dynamic reconfiguration ismade possible by the use of the DUCK concept: theseparation of configuration path and the configurationregisters. A small overhead of silicon area for each logiccell and interconnect box is involved by our method, buton the other hand, the reconfiguration itself allows tosave resources compared to multi-context DRAs.Furthermore, to maintain the timing constraint, it isnecessary to propagate each new context as fast as pos-sible, so that the new tasks can swap in the most efficientway. That is realized by the introduction of the split con-figuration path. Indeed, when several configurationpaths are created, it is possible to propagate new con-texts in parallel with each configuration path. Thismethod allows to reduce the propagation time withregard to the number of configuration path used. Thefollowing case study gives more precise results aboutsaved resources on a telecommunication application.

4. CASE-STUDY

In this section, we present the implementationof a Wideband Code Division Multiple Access WCDMAreceiver on our embedded FPGA (Figure 6) and onthe dynamically reconfigurable processor DART.WCDMA is a high-speed transmission protocol usedin third generation mobile communication systemssuch as UMTS (Universal Mobile Telecommunica-tions System), and is considered as one of the mostcritical applications of third-generation telecommuni-cation systems. It is based on the CDMA access tech-nique where all data sent within a channel and for auser to have to be coded with a specific code to be dis-tinguished from the data transmitted in other chan-nels [8]. The number of codes is limited and dependson the total capacity of the cell, which is the area cov-ered by a single base station. To be compliant with theUMTS radio interface specification (UTRA – Univer-sal Terrestrial Radio Access), each channel mustachieve a data rate of at least 128kbps. The theoreticaltotal number of concurrent channels is 128 channels.As in practice only about 60% of the channels are usedfor user data, the WCDMA base-station can support76 users per carrier.

TheWCDMA application executed on ourreconfigurable architecture consists in the alternateexecution of three main tasks (Figure5): FIR (FiniteImpulse Response) filter, Searcher, and Rake Receiver.Within a WCDMA receiver, real and imaginary partsof the signal received on the antenna after demodula-tion and digital-to-analog conversion, Sr(n), are fil-tered by an FIR (Finite Impulse Response) shaping fil-ters. Since the transmitted signal reflects in obstacleslike buildings or trees, the receiver gets several replicasof the same signal with different delays and phases. Bycombining the different paths, the decision quality is

drastically improved. Consequently, the Rake Receivercombines the different paths extracted by the Searcherblock in order to improve the quality of the symboldecision. Each path is computed by one finger whichcorrelates the received signal by a spreading codealigned with the delay of the multipath signal. In ourcase, a maximum number of fingers are considered.This task is realized at the chip rate of 3.84 MHz. Thedecision is finally done on the combination of all thesespreaded paths.

A. Timing Constraints

WCDMA is the highest speed transmissionprotocol used in the UMTS system. The bandwidth ofthe transmitted signal is equal to 5 MHz. The fre-quency of the code corresponding to the chip rate(Fchip) is fixed to 3.84 MHz. One slot is composed of256 chip data. Registers are used to pipeline datawhile FIR, Searcher or Rake Receiver are computingin one slot. For better synchronization results, thereceived chip is 4-time over-sampled. The computingtime available for the three functions (FIR, Searcher,and Rake Receiver) is therefore tslot = 66.6_s betweenthe computation of two consecutive slots. The FIRand Searcher computes on 1024 samples while oneFinger of the Rake Receiver computes on 256 sam-ples. One sample is computed at each clock cycle.

B. e-FPGA implementation

The implementation of the WCDMA receiveron an hardware accelerator composed from standardlogic cells as such implemented in a FPGA architectureis presented. The interaction of a DUCK and a logiccells allows the architecture to reconfigure the wholeresources in parallel.

Table II presents synthesis results obtained withthe VPR [15] and ABC Berkeley [16] frameworks. Themost complex function, the searcher, requires 4953logic cells to be configured in the e-FPGA. It is there-fore possible to implement the whole WCDMA decoderinto 4953 logic cells using dynamic reconfiguration. Toillustrate dynamic reconfiguration, the three functionsare executed sequentially in a time slot of 66.6µs i.e.22.2µs for each function. Therefore, each function isexecuted during 22.2µs while the next context is propa-gated. As said previously, each function is completed in1024 clock cycles, and the clock frequency is therefore

Figure 5. WCDMA receiver synoptic

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greater than 46.55 MHz. The logic cell critical path hasa value of 0.6ns in a 130nm CMOS technology. Consi-dering that the functions have a critical path of 13 logiccells, the computing frequency can be up to 128.2MHz. For a better power consumption, the frequencycan be reduced to a lower value maintaining the timingconstraint. For this implementation, the computing fre-quency is set to 50 MHz (tcomputing = 20.48µs).

To perform dynamic reconfiguration, 4953 logiccells need to be reconfigured in less than 22.2µs. Onelogic cell has 20 reconfiguration bits and a DyRIBox 10bits. A 6-bit width configuration path is used for itsgood trade-off between performance and silicon area.Therefore, 4953 x 30/6 = 24765 6-bit words are need-ed for each context.

Thanks to our system architecture, the globalconfiguration is split into 8 reconfiguration domainsmanaged in parallel. Using a 300MHz clock frequencyfor the reconfiguration process allows to reconfigure inless than 11µs.

Figure 6 shows the implemented architecturewith 8 domains of 620 logic cells. Static memory isused to allow data exchange between each functions.Light-gray areas represent the 8 configuration pathscomposed of 620 logic cells each. Each WCDMA func-tion can be implemented on this architecture. The FIRfunction is depicted as task T1. Its implementationrequires all domains and thus designs a unique com-puting path. The Searcher function requires also the 8domains and thus designs also a unique computingpath. The last function, Rake Receiver, can be split on8 computing paths. One computing path for one fin-ger. Assuming that a Finger implementation requires561 logic cells, one domain is used for each finger. The

59 remaining logic cells are used to realize the decisionon symbol.

Figure 7 shows that the process of propagation,computing and reconfiguration is fast enough to main-tain the timing constraints thanks to the DUCKresources in the DyRIBox and the logic cell. On oneslot time, the DUCK resources are able to extract theprevious context or propagate the future context.PreeRFS means preemption of the Rake receiver or FIRor Searcher contexts and ConfRFS means configurationof the Rake receiver or FIR or Searcher contexts. TheNOP operation means that the DUCK resources arewaiting for working. Domain 0 and Domain 1 are giv-ing an example of a complete WCDMA computingimplementation including Finger implementation.Domain 7 gives an example where no Finger needs tobe implemented. The computing time (tcomputing) repre-sents the available computing time of one function, thepropagation time (tpropagation) represents the availabletime for the configuration and the preemption process-es, and the reconfiguration time (tr) represents the timeneeded to reconfiguration the whole domain. The syn-thesis results the silicon overhead of the added localconfiguration memories. The overhead silicon area ofthe DUCK resource is 998µm2 for a DyRIBox and1468µm2 for a logic cell. Considering that 4960 of thetwo resources are implemented, the overall area over-head can be estimated at 12.23mm2. It is important tonotice that 12926 logic cells should have been used fora static implementation. Our implementation usingdynamic reconfiguration consumes 7966 logic cells lessthan the static implementation. Considering that thesilicon area needed for a logic cell is 2160µm2 and6850µm2 for a DyRIBox, we can estimate the savedarea to 59mm2. Thanks to partial reconfigurationoffered by today’s Xilinx FPGAs, it could be possibleto implement a WCDMA decoder on two areas of4960 logic cells. This solution requires 4960 logiccells more than our dynamic implementation.

Finally, Table III compares the same WCDMAdecoder implemented in a Xilinx Virtex FPGA. It can

Table II. Necessary logic-cells for WCDMA decoder implementa-tion on a dynmicall reconfigurable architecture

FIR Searcher Rake Receivera Finger All

Logic cells 3475 4953 561 4488

Total 12916

Figure 6. Resource allocation of the implemented embedded FPGA



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be easily concluded that a dynamic reconfiguration isnot possible on the Virtex since the reconfigurationof the entire FPGA takes more than 2ms [12] with aconfiguration frequency of 60MHz and with theSelectMAP interface which enable 8-bit word confi-guration.

C. DART implementation

In this section, we present the implementationof the WCDMA receiver on a hardware acceleratorcomposed from the computing resources of theDART architecture.

The dynamically reconfigurable processorDART [11] is a coarse-grain reconfigurable architec-ture developed mainly for 3G mobile telecommunica-tion application domain. DART architecture is buildaround six computing elements called DPR(DataPath Reconfigurable Figure 8). Each DPR iscomposed of two registers (reg), four AddressGenerators (AG) to access four local memories(Datamem), and four FUs (functional units twoadder/subtracters and two multipliers). The DPR isfully configurable thanks to a fully connected multi-bus. The original architecture was fixed and it was notpossible to modify the structure of the DPR.

A DPR reconfiguration is executed in either 3 or9 clock cycles.Thanks to the DUCK concept and theparallelization of the reconfiguration processes, thisreconfiguration is reduced to one clock cycle. An exam-ple of the interaction between a functional unit of aDPR and its dedicated DUCK is given Figure 9. In thisexample, each bit register used for the configuration ofthe functionnality of the FU becomes a parallel config-uration register so that each configuration bit can beswitched. Each DPR requires NbconfPE = 38 configura-

tion bits (Table IV). Figure 10 shows the implementedarchitecture with 6 DPR needed for this application.Therefore, 228 bits are needed for each configurationof the whole DART architecture, interconnectionDUCK excepted.

Two kinds of interconnection units are used.First, one kind of interconnection (DBdpr) is necessaryto connect all the resources inside a DPR. 18 inputsare connectable to 10 outputs. Therefore, the config-uration size (TCDBdpr) of this interconnection unitrequires :

TCDBdpr = 10 x [log2(18)] = 50 bits (1)

The second kind of interconnection unit(DBcluster) is an 8-bitwidth crossbar type and is neces-sary for the communication between the 60 registersand functional units of all the DPR inside one cluster

Table III. Comparison between results on an enbedded FPGAsolution and on a Virtex commercial FPGA

System Logic Configuration ReconfigurationCells Size (8-bit word) Time

e-FPGA 4960 36k 22.2µsXCV200 5292 164k 2.53ms

Figure 7. Gantt diagram of computing and reconfiguration process

Figure 8. A DPR computing element of the DART reconfigurablearchitecture.

Table 4. Configuration size for each unit of one cluster of six DPR

Reconfiguration Size (Bits) Size (Bits) Size (Bits)Target /Resource /DPR /Cluster

AG 1 4 24Registers 1 6 36

Add/Subb(FU1-3) 3 6 36Multiplier(FU2-4) 11 22 132

Total 38 228

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with a maximum of 30 possible connections.Therefore, the configuration size (TCDBcluster) of thisinterconnection unit requires:

TCDBcluster = 8 x [log2(30)] = 40 bits (2)

The WCDMA implementation on DART hasalready been presented in [10]. The configuration sizeof all interconnection units (TCDB) requires TCDB =6 x 50+40 = 340 bits. The complete bitstream size forthe whole DART architecture (TCDART ) requiresTCDART = 228 + 340 = 568 bits. On DART, thereconfiguration is executed at the same frequency asthe processing frequency, which is up to 130 MHz forthe reference design in [11].

The number of domains needed (ND) is speci-fied by the available time between two configurations(Propt). Propt is determined by the number of registers

to reconfigure and the speed of the configurationmemory to read the bitstream which is equal to 300MHz. A complete new context can be propagated in

The shortest propagation time available is exe-cuted during the channel estimation function. Thiscontext is only implemented during 8 clock cycles.Considering that for this application, the working fre-quency is fixed to 93 MHz, the propagation timeavailable is then equal to 86.22 ns. Therefore, thenumber of reconfiguration domain required to main-tain the reconfiguration constraints are equal to:

ND = 241E -9

86.22E -9 = 3

Propt = 580/8300E6

= 240 ns

Figure 9. DUCK Generated for a fast reconfiguration on DART architecture

Figure 10. Resource allocation on the implemented DPR of DART

Figure 11. Gant diagram of computing and reconfiguration process for the DART implementation

(3)

(4)



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Figure 11 shows the timing implementation ofthe different functions on one reconfigurationdomain. Each domain receives the same configurationin parallel.While the cluster computes, the DUCKs arereceiving the different configuration simultaneously.Next configurations are prepared during the execu-tion of the functions. Csfc stands for configuration ofthe function Synchronisation Fchip, Csfs for configura-tion of the function Synchronisation Fsymb, Cec for con-figuration of the function Channel Estimation, Cd forconfiguration of the function Decoding, and Cf forconfiguration of the function FIR.

5. CONCLUSIONS

In this paper, a new fast dynamically reconfi-gurable concept for embedded hardware accelerator isproposed. This method allows to use dynamic recon-figuration and to gain in flexibility and in silicon areawhile maintaining the timing constraints. The recon-figuration time is reduced compared to traditionalFPGA or DRP. The proposed concept is based on theisolation of the configuration paths and the configura-tion resources, which allows to prepare new contextsduring the computations. The second concept con-sists in the possibility to split the configuration pathwhile maintaining a unique computing path in orderto propagate the configuration through several con-figuration paths at the same time. In the near future,we will develop exploration tools in order to estimatethe possible configuration paths to automatically getthe best trade-off between speed, performance and sil-icon area.

ACKNOWLEDGMENTS

This work has been performed in the context ofthe CoMap project and is financed by the FrenchMinistry of Foreign Affairs. The authors would like tothank A.Kupriyanov, D.Kiessler, F.Hanning, J.Teich,B.Pottier and R.Keryell for their fruitfull collaboration.

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