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EFM32HG322 DATASHEETF64/F32
Preliminary
• ARM Cortex-M0+ CPU platform• High Performance 32-bit processor @ up to 25 MHz• Wake-up Interrupt Controller
• Flexible Energy Management System• 20 nA @ 3 V Shutoff Mode• 0.5 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPUretention
• 46 µA/MHz @ 3 V Sleep Mode• 114 µA/MHz @ 3 V Run Mode, with code executed from flash
• 64/32 KB Flash• 8/8 KB RAM• 35 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drivestrength
• Configurable peripheral I/O locations• 16 asynchronous external interrupts• Output state retention and wake-up from Shutoff Mode
• 6 Channel DMA Controller• 6 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling• Hardware AES with 128-bit keys in 54 cycles• Timers/Counters
• 3× 16-bit Timer/Counter• 3×3 Compare/Capture/PWM channels• Dead-Time Insertion on TIMER0
• 1× 24-bit Real-Time Counter• 1× 16-bit Pulse Counter• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Communication interfaces• 2× Universal Synchronous/Asynchronous Receiv-
er/Transmitter• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S• Triple buffered full/half-duplex operation
• Low Energy UART• Autonomous operation with DMA in Deep Sleep
Mode• I2C Interface with SMBus support
• Address recognition in Stop Mode• Low Energy Universal Serial Bus (USB) Device
• Fully USB 2.0 compliant• On-chip PHY and embedded 5V to 3.3V regulator• Crystal-free operation
• Ultra low power precision analog peripherals• 12-bit 1 Msamples/s Analog to Digital Converter
• 4 single ended channels/2 differential channels• On-chip temperature sensor
• Current Digital to Analog Converter• Selectable current range between 0.05 and 64 uA
• 1× Analog Comparator• Capacitive sensing with up to 5 inputs
• Supply Voltage Comparator• Ultra efficient Power-on Reset and Brown-Out Detec-
tor• Debug Interface
• 2-pin Serial Wire Debug interface• Micro Trace Buffer (MTB)
• Pre-Programmed USB/UART Bootloader• Temperature range -40 to 85 ºC• Single power supply 1.98 to 3.8 V• TQFP48 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering• Health and fitness applications• Smart accessories
• Alarm and security systems• Industrial and home automation
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1 Ordering InformationTable 1.1 (p. 2) shows the available EFM32HG322 devices.
Table 1.1. Ordering Information
Ordering Code Flash (kB) RAM (kB) MaxSpeed(MHz)
SupplyVoltage(V)
Temperature(ºC)
Package
EFM32HG322F32G-A-QFP48 32 8 25 1.98 - 3.8 -40 - 85 TQFP48
EFM32HG322F64G-A-QFP48 64 8 25 1.98 - 3.8 -40 - 85 TQFP48
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combinationof the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time fromenergy saving modes, and a wide selection of peripherals, the EFM32HG microcontroller is well suitedfor any battery operated application as well as other systems requiring high performance and low-energyconsumption. This section gives a short introduction to each of the modules in general terms and alsoshows a summary of the configuration for the EFM32HG322 devices. For a complete feature set andin-depth information on the modules, the reader is referred to the EFM32HG Reference Manual.
A block diagram of the EFM32HG322 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
Clock Management Energy Management
Serial Interfaces I/ O Ports
Core and Memory
Timers and Triggers
32- bit busPeripheral Reflex System
ARM Cortex™ M0+ processor
FlashProgramMemory
Pulse Counter
WatchdogTimer
RAMMemory
GeneralPurposeI/ O
ExternalInterrupts
PinReset
HG322F64/ F32
USART I2C
Power- onReset
VoltageRegulator
VoltageComparator
Brown- outDetector
Timer/Counter
Real TimeCounter
Current DAC
LowEnergyUART™
High FreqCrystalOscillator
Low FreqCrystalOscillator
Low FreqRCOscillator
Ultra Low FreqRCOscillator
High FreqRCOscillator
48/ 24 MHzComm. RCOscillator
Aux HighFreq RCOscillator
PinWakeup
Analog Interfaces
ADC
Security
HardwareAES
DMAController
DebugInterfacew/ MTB
Low EnergyUSB
AnalogComparator
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 DhrystoneMIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-cluded as well. The EFM32 implementation of the Cortex-M0+ is described in detail in ARM Cortex-M0+Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and a MicroTrace Buffer (MTB) for data/instruction tracing.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32HG microcontroller.The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory isdivided into two blocks; the main block and the information block. Program code is normally written tothe main block. Additionally, the information block is available for special user data and flash lock bits.
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There is also a read-only page in the information block containing system and device calibration data.Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.This has the benefit of reducing the energy consumption and the workload of the CPU, and enablesthe system to stay in low energy modes when moving for instance data from the USART to RAM orfrom the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMAcontroller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32HG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32HG microcon-trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMUcan also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board theEFM32HG. The CMU provides the capability to turn on and off the clock on an individual basis to allperipheral modules in addition to enable/disable and configure the available oscillators. The high degreeof flexibility enables software to minimize energy consumption in any specific application by not wastingpower on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by asoftware failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral modulecommunicate directly with each other without involving the CPU. Peripheral modules which send outReflex signals are called producers. The PRS routes these reflex signals to consumer peripherals whichapply actions depending on the data received. The format for the Reflex signals is not given, but edgetriggers and other functionality can be applied by the PRS.
2.1.10 Low Energy USB
The unique Low Energy USB peripheral provides a full-speed USB 2.0 compliant device controller andPHY with ultra-low current consumption. The device supports both full-speed (12MBit/s) and low speed(1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crys-tal-free operation. No external components are required. The Low Energy Mode ensures the currentconsumption is optimized and enables USB communication on a strict power budget. The USB deviceincludes an internal dedicated descriptor-based Scatter/Gather DMA and supports up to 3 OUT end-points and 3 IN endpoints, in addition to endpoint 0. The on-chip PHY includes software controllablepull-up and pull-down resistors.
2.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting asboth a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
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Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.The interface provided to software by the I2C module, allows both fine-grained control of the transmissionprocess and close to automatic transfers. Automatic recognition of slave addresses is provided in allenergy modes.
2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (US-ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexibleserial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0042 is pre-programmed in the device at factory. Thebootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UARTwithout the need for a debugger. The autobaud feature, interface and commands are described furtherin the application note.
2.1.14 Low Energy Universal Asynchronous Receiver/Transmitter(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication ona strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/s. The LEUART includes all necessary hardware support to make asynchronous serial communicationpossible with minimum of software intervention and energy consumption.
2.1.15 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motorcontrol applications.
2.1.16 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystaloscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is alsoavailable in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 wheremost of the device is powered down.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadratureencoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-cating which input voltage is higher. Inputs can either be one of the selectable internal references or fromexternal pins. Response time and thereby also the current consumption can be configured by alteringthe current supply to the comparator.
2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt canbe generated when the supply falls below or rises above a programmable threshold. Response time andthereby also the current consumption can be configured by altering the current supply to the comparator.
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2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bitsat up to one million samples per second. The integrated input mux can select inputs from 4 externalpins and 6 internal signals.
2.1.21 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which canbe output on, or sinked from pin or ADC. The current is configurable with several ranges of variousstep sizes.
2.1.22 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slavewhich enables efficient access to the data and key registers. All write accesses to the AES module mustbe 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.23 General Purpose Input/Output (GPIO)
In the EFM32HG322, there are 35 General Purpose Input/Output (GPIO) pins, which are divided intoports with up to 16 pins each. These pins can individually be configured as either an output or input. Moreadvanced configurations like open-drain, filtering and drive strength can also be configured individuallyfor the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWMoutputs or USART communication, which can be routed to several locations on the device. The GPIOsupports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on thedevice. Also, the input value of a pin can be routed through the Peripheral Reflex System to otherperipherals.
2.2 Configuration SummaryThe features of the EFM32HG322 is a subset of the feature set described in the EFM32HG ReferenceManual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module Configuration Pin Connections
Cortex-M0+ Full configuration NA
DBG Full configuration DBG_SWCLK, DBG_SWDIO,
MSC Full configuration NA
DMA Full configuration NA
RMU Full configuration NA
EMU Full configuration NA
CMU Full configuration CMU_OUT0, CMU_OUT1
WDOG Full configuration NA
PRS Full configuration NA
USB Full configuration USB_VREGI, USB_VREGO, USB_DM,USB_DMPU, USB_DP
I2C0 Full configuration I2C0_SDA, I2C0_SCL
USART0 Full configuration with IrDA and I2S US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration with I2S and IrDA US1_TX, US1_RX, US1_CLK, US1_CS
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Module Configuration Pin Connections
LEUART0 Full configuration LEU0_TX, LEU0_RX
TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration TIM1_CC[2:0]
TIMER2 Full configuration TIM2_CC[2:0]
RTC Full configuration NA
PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]
ACMP0 Full configuration ACMP0_CH[4:0], ACMP0_O
VCMP Full configuration NA
ADC0 Full configuration ADC0_CH[7:4]
IDAC0 Full configuration IDAC0_OUT
AES Full configuration NA
GPIO 35 pins Available pins are shown inTable 4.3 (p. 55)
2.3 Memory Map
The EFM32HG322 memory map is shown in Figure 2.2 (p. 7) , with RAM and Flash sizes for thelargest memory configuration.
Figure 2.2. EFM32HG322 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8) , by simu-lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-age and frequencies, as defined in Table 3.2 (p. 8) , by simulation and/or technology characterisa-tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions arenot guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliabilityor cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.8) .
Table 3.1. Absolute Maximum Ratings
Symbol Parameter Condition Min Typ Max Unit
TSTG Storage tempera-ture range
-40 1501 °C
TS Maximum solderingtemperature
Latest IPC/JEDEC J-STD-020Standard
260 °C
VDDMAX External main sup-ply voltage
0 3.8 V
VIOPIN Voltage on any I/Opin
-0.3 VDD+0.3 V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol Parameter Min Typ Max Unit
TAMB Ambient temperature range -40 85 °C
VDDOP Operating supply voltage 1.98 3.8 V
fAPB Internal APB clock frequency 25 MHz
fAHB Internal AHB clock frequency 25 MHz
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol Parameter Condition Min Typ Max Unit
24 MHz HFXO, all peripheralclocks disabled, VDD= 3.0 V
129 µA/MHz
21 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
127 µA/MHz
14 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
131 µA/MHz
11 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
132 µA/MHz
6.6 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
139 µA/MHz
IEM0
EM0 current. Noprescaling. Runningprime number cal-culation code fromFlash.
1.2 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
173 µA/MHz
24 MHz HFXO, all peripheralclocks disabled, VDD= 3.0 V
55 µA/MHz
21 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
55 µA/MHz
14 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
57 µA/MHz
11 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
59 µA/MHz
6.6 MHz HFRCO, all peripheralclocks disabled, VDD= 3.0 V
65 µA/MHz
IEM1 EM1 current
1.2 MHz HFRCO. all peripheralclocks disabled, VDD= 3.0 V
102 µA/MHz
EM2 current with RTCprescaled to 1 Hz, 32.768kHz LFRCO, VDD= 3.0 V,TAMB=25°C
0.9 µA
IEM2 EM2 currentEM2 current with RTCprescaled to 1 Hz, 32.768kHz LFRCO, VDD= 3.0 V,TAMB=85°C
1.8 µA
EM3 current (ULFRCO en-abled, LFRCO/LFXO disabled),VDD= 3.0 V, TAMB=25°C
0.5 µA
IEM3 EM3 currentEM3 current (ULFRCO en-abled, LFRCO/LFXO disabled),VDD= 3.0 V, TAMB=85°C
1.2 µA
VDD= 3.0 V, TAMB=25°C 0.02 µAIEM4 EM4 current
VDD= 3.0 V, TAMB=85°C 0.30 µA
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3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flashwith HFRCO running at 24 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
2.68
2.70
2.72
2.74
2.76
2.78
2.80
2.82
2.84
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
2.68
2.70
2.72
2.74
2.76
2.78
2.80
2.82
2.84
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.2. EM0 Current consumption while executing prime number calculation code from flashwith HFRCO running at 21 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
2.30
2.35
2.40
2.45
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
2.30
2.35
2.40
2.45
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.3. EM0 Current consumption while executing prime number calculation code from flashwith HFRCO running at 14 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
1.54
1.56
1.58
1.60
1.62
1.64
1.66
1.68
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
1.54
1.56
1.58
1.60
1.62
1.64
1.66
1.68
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.4. EM0 Current consumption while executing prime number calculation code from flashwith HFRCO running at 11 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
1.22
1.24
1.26
1.28
1.30
1.32
1.34
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
1.22
1.24
1.26
1.28
1.30
1.32
1.34
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.5. EM0 Current consumption while executing prime number calculation code from flashwith HFRCO running at 6.6 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO runningat 24 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
1.10
1.12
1.14
1.16
1.18
1.20
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
1.10
1.12
1.14
1.16
1.18
1.20
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO runningat 21 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO runningat 14 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO runningat 11 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.53
0.54
0.55
0.56
0.57
0.58
0.59
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.53
0.54
0.55
0.56
0.57
0.58
0.59
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO runningat 6.6 MHz
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.350
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
Idd
[m
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.350
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
Idd
[m
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Idd
[u
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Idd
[u
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Idd
[u
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Idd
[u
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
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3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
–0.1
0.0
0.1
0.2
0.3
0.4
0.5
Idd
[u
A]
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
–40 –15 5 25 45 65 85Temperature [°C]
–0.1
0.0
0.1
0.2
0.3
0.4
0.5
Idd
[u
A]
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol Parameter Min Typ Max Unit
tEM10 Transition time from EM1 to EM0 0 HF-CORE-CLKcycles
tEM20 Transition time from EM2 to EM0 2 µs
tEM30 Transition time from EM3 to EM0 2 µs
tEM40 Transition time from EM4 to EM0 163 µs
3.6 Power Management
The EFM32HG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (withoptional filter) at the PCB level. For practical schematic recommendations, please see the applicationnote, "AN0002 EFM32 Hardware Design Considerations".
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Table 3.5. Power Management
Symbol Parameter Condition Min Typ Max Unit
VBODextthr- BOD threshold onfalling external sup-ply voltage
1.74 1.96 V
VBODextthr+ BOD threshold onrising external sup-ply voltage
1.85 V
tRESET Delay from resetis released untilprogram executionstarts
Applies to Power-on Reset,Brown-out Reset and pin reset.
163 µs
CDECOUPLE Voltage regulatordecoupling capaci-tor.
X5R capacitor recommended.Apply between DECOUPLE pinand GROUND
1 µF
CUSB_VREGO USB voltage regu-lator out decouplingcapacitor.
X5R capacitor recommended.Apply between USB_VREGOpin and GROUND
1 µF
CUSB_VREGI USB voltage regula-tor in decoupling ca-pacitor.
X5R capacitor recommended.Apply between USB_VREGIpin and GROUND
4.7 µF
3.7 Flash
Table 3.6. Flash
Symbol Parameter Condition Min Typ Max Unit
ECFLASH Flash erase cyclesbefore failure
20000 cycles
TAMB<150°C 10000 h
TAMB<85°C 10 yearsRETFLASH Flash data retention
TAMB<70°C 20 years
tW_PROG Word (32-bit) pro-gramming time
20 µs
tP_ERASE Page erase time 20 20.4 20.8 ms
tD_ERASE Device erase time 40 40.8 41.6 ms
IERASE Erase current 71 mA
IWRITE Write current 71 mA
VFLASH Supply voltage dur-ing flash erase andwrite
1.98 3.8 V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol Parameter Condition Min Typ Max Unit
VIOIL Input low voltage 0.30VDD V
VIOIH Input high voltage 0.70VDD V
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Symbol Parameter Condition Min Typ Max Unit
Sourcing 0.1 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= LOWEST
0.80VDD V
Sourcing 0.1 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= LOWEST
0.90VDD V
Sourcing 1 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= LOW
0.85VDD V
Sourcing 1 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= LOW
0.90VDD V
Sourcing 6 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= STANDARD
0.75VDD V
Sourcing 6 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= STANDARD
0.85VDD V
Sourcing 20 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= HIGH
0.60VDD V
VIOOH
Output high volt-age (Production testcondition = 3.0V,DRIVEMODE =STANDARD)
Sourcing 20 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= HIGH
0.80VDD V
Sinking 0.1 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= LOWEST
0.20VDD V
Sinking 0.1 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= LOWEST
0.10VDD V
Sinking 1 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= LOW
0.10VDD V
Sinking 1 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= LOW
0.05VDD V
Sinking 6 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= STANDARD
0.20VDD V
Sinking 20 mA, VDD=1.98 V,GPIO_Px_CTRL DRIVEMODE= HIGH
0.35VDD V
VIOOL
Output low voltage(Production testcondition = 3.0V,DRIVEMODE =STANDARD)
Sinking 20 mA, VDD=3.0 V,GPIO_Px_CTRL DRIVEMODE= HIGH
0.25VDD V
IIOLEAK Input leakage cur-rent
High Impedance IO connectedto GROUND or Vdd
±0.1 ±100 nA
RPU I/O pin pull-up resis-tor
40 kOhm
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Symbol Parameter Condition Min Typ Max Unit
RPD I/O pin pull-down re-sistor
40 kOhm
RIOESD Internal ESD seriesresistor
200 Ohm
tIOGLITCH Pulse width of puls-es to be removedby the glitch sup-pression filter
10 50 ns
GPIO_Px_CTRL DRIVEMODE= LOWEST and load capaci-tance CL=12.5-25pF.
20+0.1CL 250 ns
tIOOF Output fall timeGPIO_Px_CTRL DRIVEMODE= LOW and load capacitanceCL=350-600pF
20+0.1CL 250 ns
VIOHYST I/O pin hysteresis(VIOTHR+ - VIOTHR-)
VDD = 1.98 - 3.8 V 0.1VDD V
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0Low- Level Output Voltage [V]
0.00
0.05
0.10
0.15
0.20
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0Low- Level Output Voltage [V]
0
1
2
3
4
5
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0Low- Level Output Voltage [V]
0
5
10
15
20
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
45
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.0 0.5 1.0 1.5 2.0High- Level Output Voltage [V]
–0.20
–0.15
–0.10
–0.05
0.00
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0High- Level Output Voltage [V]
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0High- Level Output Voltage [V]
–20
–15
–10
–5
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0Low- Level Output Voltage [V]
0
2
4
6
8
10
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0Low- Level Output Voltage [V]
0
5
10
15
20
25
30
35
40
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0Low- Level Output Voltage [V]
0
10
20
30
40
50
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0High- Level Output Voltage [V]
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0High- Level Output Voltage [V]
–6
–5
–4
–3
–2
–1
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Low- Level Output Voltage [V]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Low- Level Output Voltage [V]
0
2
4
6
8
10
12
14
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Low- Level Output Voltage [V]
0
10
20
30
40
50
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Low- Level Output Voltage [V]
0
10
20
30
40
50
Low
-Le
vel
Ou
tpu
t C
urr
ent
[mA
]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5High- Level Output Voltage [V]
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0.0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5High- Level Output Voltage [V]
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = STANDARD
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5High- Level Output Voltage [V]
–50
–40
–30
–20
–10
0
Hig
h-
Leve
l O
utp
ut
Cu
rren
t [m
A]
- 40°C
25°C
85°C
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol Parameter Condition Min Typ Max Unit
fLFXO Supported nominalcrystal frequency
32.768 kHz
ESRLFXO Supported crystalequivalent series re-sistance (ESR)
30 120 kOhm
CLFXOL Supported crystalexternal load range
5 25 pF
ILFXO Current consump-tion for core andbuffer after startup.
ESR=30 kOhm, CL=10 pF,LFXOBOOST in CMU_CTRL is1
190 nA
tLFXO Start- up time. ESR=30 kOhm, CL=10 pF,40% - 60% duty cycle hasbeen reached, LFXOBOOST inCMU_CTRL is 1
1100 ms
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to helpusers configure both load capacitance and software settings for using the LFXO. For details regardingthe crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator DesignConsideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol Parameter Condition Min Typ Max Unit
fHFXO Supported nominalcrystal Frequency
4 25 MHz
Crystal frequency 25 MHz 30 100 OhmESRHFXO
Supported crystalequivalent series re-sistance (ESR) Crystal frequency 4 MHz 400 1500 Ohm
gmHFXO The transconduc-tance of the HFXOinput transistor atcrystal startup
HFXOBOOST in CMU_CTRLequals 0b11
20 mS
CHFXOL Supported crystalexternal load range
5 25 pF
4 MHz: ESR=400 Ohm,CL=20 pF, HFXOBOOST inCMU_CTRL equals 0b11
85 µA
IHFXO
Current consump-tion for HFXO afterstartup 25 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST inCMU_CTRL equals 0b11
165 µA
tHFXO Startup time 25 MHz: ESR=30 Ohm,CL=10 pF, HFXOBOOST inCMU_CTRL equals 0b11
785 µs
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3.9.3 LFRCO
Table 3.10. LFRCO
Symbol Parameter Condition Min Typ Max Unit
fLFRCO Oscillation frequen-cy , VDD= 3.0 V,TAMB=25°C
32.768 kHz
tLFRCO Startup time not in-cluding softwarecalibration
150 µs
ILFRCO Current consump-tion
190 nA
TUNESTEPL-
FRCO
Frequency stepfor LSB change inTUNING value
1.5 %
Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
30
32
34
36
38
40
42
Freq
uen
cy [
kH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
30
32
34
36
38
40
42
Freq
uen
cy [
kH
z]
2.0 V
3.0 V
3.8 V
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3.9.4 HFRCO
Table 3.11. HFRCO
Symbol Parameter Condition Min Typ Max Unit
21 MHz frequency band 21 MHz
14 MHz frequency band 14 MHz
11 MHz frequency band 11 MHz
7 MHz frequency band 6.6 MHz
fHFRCO
Oscillation frequen-cy, VDD= 3.0 V,TAMB=25°C
1 MHz frequency band 1.2 MHz
tHFRCO_settling Settling time afterstart-up
fHFRCO = 14 MHz 0.6 Cycles
fHFRCO = 21 MHz 93 µA
fHFRCO = 14 MHz 77 µA
fHFRCO = 11 MHz 72 µA
fHFRCO = 6.6 MHz 63 µA
IHFRCOCurrent consump-tion
fHFRCO = 1.2 MHz 22 µA
TUNESTEPH-
FRCO
Frequency stepfor LSB change inTUNING value
0.31 %
1The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustmentrange to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. Byusing a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and thefrequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 21 MHz across operating conditions.
Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Freq
uen
cy [
MH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
Freq
uen
cy [
MH
z]
2.0 V
3.0 V
3.8 V
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Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Freq
uen
cy [
MH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
6.30
6.35
6.40
6.45
6.50
6.55
6.60
6.65
6.70
Freq
uen
cy [
MH
z]
2.0 V
3.0 V
3.8 V
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Freq
uen
cy [
MH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
10.6
10.7
10.8
10.9
11.0
11.1
11.2
Freq
uen
cy [
MH
z]
2.0 V
3.0 V
3.8 V
Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Freq
uen
cy [
MH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
Freq
uen
cy [
MH
z]
2.0 V
3.0 V
3.8 V
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Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd [V]
20.2
20.4
20.6
20.8
21.0
21.2
Freq
uen
cy [
MH
z]
- 40°C
25°C
85°C
–40 –15 5 25 45 65 85Temperature [°C]
20.2
20.4
20.6
20.8
21.0
21.2
Freq
uen
cy [
MH
z]
2.0 V
3.0 V
3.8 V
3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol Parameter Condition Min Typ Max Unit
21 MHz frequency band 21 MHz
14 MHz frequency band 14 MHz
11 MHz frequency band 11 MHz
7 MHz frequency band 6.6 MHz
fAUXHFRCO
Oscillation frequen-cy, VDD= 3.0 V,TAMB=25°C
1 MHz frequency band 1.2 MHz
tAUXHFRCO_settlingSettling time afterstart-up
fAUXHFRCO = 14 MHz 0.6 Cycles
TUNESTEPAUX-
HFRCO
Frequency stepfor LSB change inTUNING value
0.3 %
3.9.6 USHFRCO
Table 3.13. USHFRCO
Symbol Parameter Condition Min Typ Max Unit
No Clock Recovery, Full Tem-perature and Supply Range
47.3 48 48.7 MHz
No Clock Recovery, 25°C, 3.3V 47.5 48 48.5 MHzfUSHFRCO
Oscillation frequen-cy
USB Active with Clock Recov-ery, Full Temperature and Sup-ply Range
47.88 48 48.12 MHz
TCUSHFRCO Temperature coeffi-cient
3.3V 0.0175 %/°C
VCUSHFRCO Supply voltage co-efficient
25°C 0.0045 %/V
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3.9.7 ULFRCO
Table 3.14. ULFRCO
Symbol Parameter Condition Min Typ Max Unit
fULFRCO Oscillation frequen-cy
25°C, 3V 0.70 1.75 kHz
TCULFRCO Temperature coeffi-cient
0.05 %/°C
VCULFRCO Supply voltage co-efficient
-18.2 %/V
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol Parameter Condition Min Typ Max Unit
Single ended 0 VREF VVADCIN Input voltage range
Differential -VREF/2 VREF/2 V
VADCREFIN Input range of exter-nal reference volt-age, single endedand differential
1.25 VDD V
VADCREFIN_CH7 Input range of ex-ternal negative ref-erence voltage onchannel 7
See VADCREFIN 0 VDD - 1.1 V
VADCREFIN_CH6 Input range of ex-ternal positive ref-erence voltage onchannel 6
See VADCREFIN 0.625 VDD V
VADCCMIN Common mode in-put range
0 VDD V
IADCIN Input current 2pF sampling capacitors <100 nA
CMRRADC Analog input com-mon mode rejectionratio
65 dB
1 MSamples/s, 12 bit, externalreference
351 µA
10 kSamples/s 12 bit, internal1.25 V reference, WARMUP-MODE in ADCn_CTRL set to0b00
67 µA
10 kSamples/s 12 bit, internal1.25 V reference, WARMUP-MODE in ADCn_CTRL set to0b01
63 µAIADCAverage active cur-rent
10 kSamples/s 12 bit, internal1.25 V reference, WARMUP-MODE in ADCn_CTRL set to0b10
64 µA
IADCREF Current consump-tion of internal volt-age reference
Internal voltage reference 65 µA
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Symbol Parameter Condition Min Typ Max Unit
CADCIN Input capacitance 2 pF
RADCIN Input ON resistance 1 MOhm
RADCFILT Input RC filter resis-tance
10 kOhm
CADCFILT Input RC filter/de-coupling capaci-tance
250 fF
fADCCLK ADC Clock Fre-quency
13 MHz
6 bit 7 ADC-CLKCycles
8 bit 11 ADC-CLKCycles
tADCCONV Conversion time
12 bit 13 ADC-CLKCycles
tADCACQ Acquisition time Programmable 1 256 ADC-CLKCycles
tADCACQVDD3 Required acquisi-tion time for VDD/3reference
2 µs
Startup time of ref-erence generatorand ADC core inNORMAL mode
5 µs
tADCSTART Startup time of ref-erence generatorand ADC core inKEEPADCWARMmode
1 µs
1 MSamples/s, 12 bit, singleended, internal 1.25V refer-ence
59 dB
1 MSamples/s, 12 bit, singleended, internal 2.5V reference
63 dB
1 MSamples/s, 12 bit, singleended, VDD reference
65 dB
1 MSamples/s, 12 bit, differen-tial, internal 1.25V reference
60 dB
1 MSamples/s, 12 bit, differen-tial, internal 2.5V reference
65 dB
1 MSamples/s, 12 bit, differen-tial, 5V reference
54 dB
1 MSamples/s, 12 bit, differen-tial, VDD reference
67 dB
SNRADCSignal to Noise Ra-tio (SNR)
1 MSamples/s, 12 bit, differen-tial, 2xVDD reference
69 dB
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Symbol Parameter Condition Min Typ Max Unit
200 kSamples/s, 12 bit, sin-gle ended, internal 1.25V refer-ence
62 dB
200 kSamples/s, 12 bit, singleended, internal 2.5V reference
63 dB
200 kSamples/s, 12 bit, singleended, VDD reference
67 dB
200 kSamples/s, 12 bit, differ-ential, internal 1.25V reference
63 dB
200 kSamples/s, 12 bit, differ-ential, internal 2.5V reference
66 dB
200 kSamples/s, 12 bit, differ-ential, 5V reference
66 dB
200 kSamples/s, 12 bit, differ-ential, VDD reference
66 dB
200 kSamples/s, 12 bit, differ-ential, 2xVDD reference
70 dB
1 MSamples/s, 12 bit, singleended, internal 1.25V refer-ence
58 dB
1 MSamples/s, 12 bit, singleended, internal 2.5V reference
62 dB
1 MSamples/s, 12 bit, singleended, VDD reference
64 dB
1 MSamples/s, 12 bit, differen-tial, internal 1.25V reference
60 dB
1 MSamples/s, 12 bit, differen-tial, internal 2.5V reference
64 dB
1 MSamples/s, 12 bit, differen-tial, 5V reference
54 dB
1 MSamples/s, 12 bit, differen-tial, VDD reference
66 dB
1 MSamples/s, 12 bit, differen-tial, 2xVDD reference
68 dB
200 kSamples/s, 12 bit, sin-gle ended, internal 1.25V refer-ence
61 dB
200 kSamples/s, 12 bit, singleended, internal 2.5V reference
65 dB
200 kSamples/s, 12 bit, singleended, VDD reference
66 dB
200 kSamples/s, 12 bit, differ-ential, internal 1.25V reference
63 dB
200 kSamples/s, 12 bit, differ-ential, internal 2.5V reference
66 dB
200 kSamples/s, 12 bit, differ-ential, 5V reference
66 dB
SINADADC
SIgnal-to-NoiseAnd Distortion-ratio(SINAD)
200 kSamples/s, 12 bit, differ-ential, VDD reference
66 dB
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Symbol Parameter Condition Min Typ Max Unit
200 kSamples/s, 12 bit, differ-ential, 2xVDD reference
69 dB
1 MSamples/s, 12 bit, singleended, internal 1.25V refer-ence
64 dBc
1 MSamples/s, 12 bit, singleended, internal 2.5V reference
76 dBc
1 MSamples/s, 12 bit, singleended, VDD reference
73 dBc
1 MSamples/s, 12 bit, differen-tial, internal 1.25V reference
66 dBc
1 MSamples/s, 12 bit, differen-tial, internal 2.5V reference
77 dBc
1 MSamples/s, 12 bit, differen-tial, VDD reference
76 dBc
1 MSamples/s, 12 bit, differen-tial, 2xVDD reference
75 dBc
1 MSamples/s, 12 bit, differen-tial, 5V reference
69 dBc
200 kSamples/s, 12 bit, sin-gle ended, internal 1.25V refer-ence
75 dBc
200 kSamples/s, 12 bit, singleended, internal 2.5V reference
75 dBc
200 kSamples/s, 12 bit, singleended, VDD reference
76 dBc
200 kSamples/s, 12 bit, differ-ential, internal 1.25V reference
79 dBc
200 kSamples/s, 12 bit, differ-ential, internal 2.5V reference
79 dBc
200 kSamples/s, 12 bit, differ-ential, 5V reference
78 dBc
200 kSamples/s, 12 bit, differ-ential, VDD reference
79 dBc
SFDRADC
Spurious-Free Dy-namic Range (SF-DR)
200 kSamples/s, 12 bit, differ-ential, 2xVDD reference
79 dBc
After calibration, single ended 0.3 mVVADCOFFSET Offset voltage
After calibration, differential 0.3 mV
-1.92 mV/°C
TGRADADCTHThermometer out-put gradient
-6.3 ADCCodes/°C
DNLADC Differential non-lin-earity (DNL)
VDD= 3.0 V, external 2.5V ref-erence
±0.7 LSB
INLADC Integral non-linear-ity (INL), End pointmethod
±1.2 LSB
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Symbol Parameter Condition Min Typ Max Unit
MCADC No missing codes 11.9991 12 bits1On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value inthe set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonicat all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that ismissing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scaleinput for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.26 (p.35) and Figure 3.27 (p. 35) , respectively.
Figure 3.26. Integral Non-Linearity (INL)
Ideal t ransfer curve
Digital ouput code
Analog Input
INL= | [(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
0
1
2
3
4092
4093
4094
4095
VOFFSET
Actual ADC tranfer funct ion before offset and gain correct ion Actual ADC
tranfer funct ion after offset and gain correct ion
INL Error (End Point INL)
Figure 3.27. Differential Non-Linearity (DNL)
Ideal t ransfer curve
Digital ouputcode
Analog Input
DNL= | [(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
0
1
2
3
4092
4093
4094
4095
Actual t ransfer funct ion with one missing code.
4
5
Full Scale Range
0.5 LSB
Ideal Code Center
Ideal 50% Transit ion Point
Ideal spacing between two adjacent codesVLSBIDEAL= 1 LSB
Code width = 2 LSBDNL= 1 LSB
Example: Adjacent input value VD+ 1 corrresponds to digital output code D+ 1
Example: Input value VD corrresponds to digital output code D
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3.10.1 Typical performance
Figure 3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference 2.5V Reference
2XVDDVSS Reference 5VDIFF Reference
VDD Reference
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Figure 3.31. ADC Absolute Offset, Common Mode = Vdd /2
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8Vdd (V)
–4
–3
–2
–1
0
1
2
3
4
5
Act
ual
Off
set
[LSB
]
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
Offset vs Supply Voltage, Temp = 25°C
–40 –15 5 25 45 65 85Temp (C)
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
Act
ual
Off
set
[LSB
]
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
Offset vs Temperature, Vdd = 3V
Figure 3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
–40 –15 5 25 45 65 85Temperature [°C]
63
64
65
66
67
68
69
70
71
SNR
[d
B]
1V25
2V5
Vdd
5VDIFF
2XVDDVSS
Signal to Noise Ratio (SNR)
–40 –15 5 25 45 65 85Temperature [°C]
78.0
78.2
78.4
78.6
78.8
79.0
79.2
79.4
SFD
R [
dB]
1V25
2V5Vdd
5VDIFF
2XVDDVSS
Spurious-Free Dynamic Range (SFDR)
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Figure 3.33. ADC Temperature sensor readout
–40 –15 5 25 45 65 85Temperature [°C]
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
Sen
sor
read
ou
t
Vdd = 2.0
Vdd = 3.0
Vdd = 3.8
3.11 Current Digital Analog Converter (IDAC)
Table 3.16. IDAC Range 0 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 11.7 µAIIDAC
Active current withSTEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
0.84 µA
ISTEP Step size 0.049 µA
ID Current drop at highimpedance load
VIDAC_OUT = VDD - 100mV 0.73 %
TCIDAC Temperature coeffi-cient
VDD = 3.0V, STEPSEL=0x10 0.3 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 11.7 nA/V
Table 3.17. IDAC Range 0 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current withSTEPSEL=0x10
EM0, default settings 13.7 µA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
0.84 µA
ISTEP Step size 0.050 µA
ID Current drop at highimpedance load
VIDAC_OUT = 200 mV 0.16 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 0.2 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 12.5 nA/V
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Table 3.18. IDAC Range 1 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 13.0 µAIIDAC
Active current withSTEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
3.17 µA
ISTEP Step size 0.097 µA
ID Current drop at highimpedance load
VIDAC_OUT = VDD - 100mV 0.79 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 0.7 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 38.4 nA/V
Table 3.19. IDAC Range 1 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current withSTEPSEL=0x10
EM0, default settings 17.9 µA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
3.18 µA
ISTEP Step size 0.098 µA
ID Current drop at highimpedance load
VIDAC_OUT = 200 mV 0.20 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 0.7 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 40.9 nA/V
Table 3.20. IDAC Range 2 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 16.2 µAIIDAC
Active current withSTEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
8.40 µA
ISTEP Step size 0.493 µA
ID Current drop at highimpedance load
VIDAC_OUT = VDD - 100mV 1.26 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 2.8 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 96.6 nA/V
Table 3.21. IDAC Range 2 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current withSTEPSEL=0x10
EM0, default settings 28.4 µA
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Symbol Parameter Condition Min Typ Max Unit
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
8.44 µA
ISTEP Step size 0.495 µA
ID Current drop at highimpedance load
VIDAC_OUT = 200 mV 0.55 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 2.8 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 94.4 nA/V
Table 3.22. IDAC Range 3 Source
Symbol Parameter Condition Min Typ Max Unit
EM0, default settings 18.3 µAIIDAC
Active current withSTEPSEL=0x10 Duty-cycled 10 nA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
34.03 µA
ISTEP Step size 1.996 µA
ID Current drop at highimpedance load
VIDAC_OUT = VDD - 100 mV 3.18 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 10.9 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 159.5 nA/V
Table 3.23. IDAC Range 3 Sink
Symbol Parameter Condition Min Typ Max Unit
IIDAC Active current withSTEPSEL=0x10
EM0, default settings 62.9 µA
I0x10 Nominal IDAC out-put current withSTEPSEL=0x10
34.16 µA
ISTEP Step size 2.003 µA
ID Current drop at highimpedance load
VIDAC_OUT = 200 mV 1.65 %
TCIDAC Temperature coeffi-cient
VDD = 3.0 V, STEPSEL=0x10 10.9 nA/°C
VCIDAC Voltage coefficient T = 25 °C, STEPSEL=0x10 148.6 nA/V
Table 3.24. IDAC
Symbol Parameter Min Typ Max Unit
tIDACSTART Start-up time, from enabled to output settled 40 µs
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Figure 3.34. IDAC Source Current as a function of voltage on IDAC_OUT
–2.0 –1.5 –1.0 –0.5 0.0V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 0
–2.0 –1.5 –1.0 –0.5 0.0V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 1
–2.0 –1.5 –1.0 –0.5 0.0V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 2
–2.0 –1.5 –1.0 –0.5 0.0V(IDAC_OUT) - Vdd [V]
90
91
92
93
94
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 3
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Figure 3.35. IDAC Sink Current as a function of voltage from IDAC_OUT
0.0 0.5 1.0 1.5 2.0V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 0
0.0 0.5 1.0 1.5 2.0V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 1
0.0 0.5 1.0 1.5 2.0V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 2
0.0 0.5 1.0 1.5 2.0V(IDAC_OUT) [V]
95
96
97
98
99
100
101
Perc
enta
ge
of
no
min
al c
urr
ent
[%]
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
Range 3
Figure 3.36. IDAC linearity
0 5 10 15 20 25 30Step
0
1
2
3
4
5
Idd
[u
A]
Range 0
Range 1
0 5 10 15 20 25 30Step
0
10
20
30
40
50
60
70
Idd
[u
A]
Range 2
Range 3
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3.12 Analog Comparator (ACMP)
Table 3.25. ACMP
Symbol Parameter Condition Min Typ Max Unit
VACMPIN Input voltage range 0 VDD V
VACMPCM ACMP CommonMode voltage range
0 VDD V
BIASPROG=0b0000, FULL-BIAS=0 and HALFBIAS=1 inACMPn_CTRL register
0.1 µA
BIASPROG=0b1111, FULL-BIAS=0 and HALFBIAS=0 inACMPn_CTRL register
2.87 µAIACMP Active current
BIASPROG=0b1111, FULL-BIAS=1 and HALFBIAS=0 inACMPn_CTRL register
195 µA
Internal voltage reference off.Using external voltage refer-ence
0 µA
IACMPREF
Current consump-tion of internal volt-age reference
Internal voltage reference 5 µA
VACMPOFFSET Offset voltage BIASPROG= 0b1010, FULL-BIAS=0 and HALFBIAS=0 inACMPn_CTRL register
0 mV
VACMPHYST ACMP hysteresis Programmable 17 mV
CSRESSEL=0b00 inACMPn_INPUTSEL
39 kOhm
CSRESSEL=0b01 inACMPn_INPUTSEL
71 kOhm
CSRESSEL=0b10 inACMPn_INPUTSEL
104 kOhmRCSRES
Capacitive SenseInternal Resistance
CSRESSEL=0b11 inACMPn_INPUTSEL
136 kOhm
tACMPSTART Startup time 10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage referenceas given in Equation 3.1 (p. 45) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF (3.1)
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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
0 4 8 12ACMP_CTRL_BIASPROG
0.0
0.5
1.0
1.5
2.0
2.5
Cu
rren
t [u
A]
Current consumption, HYSTSEL = 4
0 2 4 6 8 10 12 14ACMP_CTRL_BIASPROG
0
5
10
15
20
Res
po
nse
Tim
e [u
s]
HYSTSEL= 0
HYSTSEL= 2
HYSTSEL= 4
HYSTSEL= 6
Response time , Vcm =1.25V, CP+ to CP- = 100mV
0 1 2 3 4 5 6 7ACMP_CTRL_HYSTSEL
0
20
40
60
80
100
Hys
tere
sis
[mV
]
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.26. VCMP
Symbol Parameter Condition Min Typ Max Unit
VVCMPIN Input voltage range VDD V
VVCMPCM VCMP CommonMode voltage range
VDD V
BIASPROG=0b0000 andHALFBIAS=1 in VCMPn_CTRLregister
0.1 µA
IVCMP Active currentBIASPROG=0b1111 andHALFBIAS=0 in VCMPn_CTRLregister. LPREF=0.
14.7 µA
tVCMPREF Startup time refer-ence generator
NORMAL 10 µs
Single ended 10 mVVVCMPOFFSET Offset voltage
Differential 10 mV
VVCMPHYST VCMP hysteresis 17 mV
tVCMPSTART Startup time 10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register inaccordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL (3.2)
3.14 I2C
Table 3.27. I2C Standard-mode (Sm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 1001 kHz
tLOW SCL clock low time 4.7 µs
tHIGH SCL clock high time 4.0 µs
tSU,DAT SDA set-up time 250 ns
tHD,DAT SDA hold time 8 34502,3 ns
tSU,STA Repeated START condition set-up time 4.7 µs
tHD,STA (Repeated) START condition hold time 4.0 µs
tSU,STO STOP condition set-up time 4.0 µs
tBUF Bus free time between a STOP and START condition 4.7 µs1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32HG Reference Manual.2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 5).
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Table 3.28. I2C Fast-mode (Fm)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 4001 kHz
tLOW SCL clock low time 1.3 µs
tHIGH SCL clock high time 0.6 µs
tSU,DAT SDA set-up time 100 ns
tHD,DAT SDA hold time 8 9002,3 ns
tSU,STA Repeated START condition set-up time 0.6 µs
tHD,STA (Repeated) START condition hold time 0.6 µs
tSU,STO STOP condition set-up time 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32HG Reference Manual.2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 5).
Table 3.29. I2C Fast-mode Plus (Fm+)
Symbol Parameter Min Typ Max Unit
fSCL SCL clock frequency 0 10001 kHz
tLOW SCL clock low time 0.5 µs
tHIGH SCL clock high time 0.26 µs
tSU,DAT SDA set-up time 50 ns
tHD,DAT SDA hold time 8 ns
tSU,STA Repeated START condition set-up time 0.26 µs
tHD,STA (Repeated) START condition hold time 0.26 µs
tSU,STO STOP condition set-up time 0.26 µs
tBUF Bus free time between a STOP and START condition 0.5 µs1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32HG Reference Manual.
3.15 USBThe USB hardware in the EFM32HG322 passes all tests for USB 2.0 Full Speed certification. The testreport will be distributed with application note "AN0046 - USB Hardware Design Guide" when ready.
3.16 Digital Peripherals
Table 3.30. Digital Peripherals
Symbol Parameter Condition Min Typ Max Unit
IUSART USART current USART idle current, clock en-abled
7.5 µA/MHz
ILEUART LEUART current LEUART idle current, clock en-abled
150 nA
II2C I2C current I2C idle current, clock enabled 6.25 µA/MHz
ITIMER TIMER current TIMER_0 idle current, clockenabled
8.75 µA/MHz
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Symbol Parameter Condition Min Typ Max Unit
IPCNT PCNT current PCNT idle current, clock en-abled
100 nA
IRTC RTC current RTC idle current, clock enabled 100 nA
IAES AES current AES idle current, clock enabled 2.5 µA/MHz
IGPIO GPIO current GPIO idle current, clock en-abled
5.31 µA/MHz
IPRS PRS current PRS idle current 2.81 µA/MHz
IDMA DMA current Clock enable 8.12 µA/MHz
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4 Pinout and PackageNote
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" forguidelines on designing Printed Circuit Boards (PCB's) for the EFM32HG322.
4.1 PinoutThe EFM32HG322 pinout is shown in Figure 4.1 (p. 50) and Table 4.1 (p. 50) . Alternate locationsare denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the modulein question.
Figure 4.1. EFM32HG322 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFP48 Pin#and Name
Pin Alternate Functionality / Description
Pin
# Pin Name Analog Timers Communication Other
1 PA0 TIM0_CC1 #6
TIM0_CC0 #0/1/4PCNT0_S0IN #4
USB_DMPU #0US1_RX #4LEU0_RX #4I2C0_SDA #0
PRS_CH0 #0PRS_CH3 #3
GPIO_EM4WU0
2 PA1 TIM0_CC0 #6
TIM0_CC1 #0/1I2C0_SCL #0
CMU_CLK1 #0PRS_CH1 #0
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QFP48 Pin#and Name
Pin Alternate Functionality / DescriptionP
in # Pin Name Analog Timers Communication Other
3 PA2 TIM0_CC2 #0/1 CMU_CLK0 #0
4 IOVDD_0 Digital IO power supply 0.
5 VSS Ground.
6 PC0 ACMP0_CH0TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5/6US1_TX #0US1_CS #5
I2C0_SDA #4
PRS_CH2 #0
7 PC1 ACMP0_CH1TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5/6US1_TX #5US1_RX #0
I2C0_SCL #4
PRS_CH3 #0
8 PC2 ACMP0_CH2 TIM0_CDTI0 #4 US1_RX #5
9 PC3 ACMP0_CH3 TIM0_CDTI1 #4 US1_CLK #5
10 PC4 ACMP0_CH4 TIM0_CDTI2 #4 GPIO_EM4WU6
11 PB7 LFXTAL_P TIM1_CC0 #3US0_TX #4
US1_CLK #0
12 PB8 LFXTAL_N TIM1_CC1 #3US0_RX #4US1_CS #0
13 PA8 TIM2_CC0 #0
14 PA9 TIM2_CC1 #0
15 PA10 TIM2_CC2 #0
16 RESETnReset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-upensure that reset is released.
17 PB11 IDAC0_OUTTIM1_CC2 #3
PCNT0_S1IN #4US1_CLK #4
CMU_CLK1 #3ACMP0_O #3
18 VSS Ground.
19 AVDD_1 Analog power supply 1.
20 PB13 HFXTAL_P US0_CLK #4/5LEU0_TX #1
21 PB14 HFXTAL_N US0_CS #4/5LEU0_RX #1
22 IOVDD_3 Digital IO power supply 3.
23 AVDD_0 Analog power supply 0.
24 PD4 ADC0_CH4 LEU0_TX #0
25 PD5 ADC0_CH5 LEU0_RX #0
26 PD6 ADC0_CH6TIM1_CC0 #4
PCNT0_S0IN #3US1_RX #2/3I2C0_SDA #1
ACMP0_O #2
27 PD7 ADC0_CH7TIM1_CC1 #4
PCNT0_S1IN #3US1_TX #2/3I2C0_SCL #1
CMU_CLK0 #2
28 VDD_DREG Power supply for on-chip voltage regulator.
29 DECOUPLE Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
30 PC8 TIM2_CC0 #2 US0_CS #2
31 PC9 TIM2_CC1 #2 US0_CLK #2 GPIO_EM4WU2
32 PC10 TIM2_CC2 #2 US0_RX #2
33 USB_VREGI
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QFP48 Pin#and Name
Pin Alternate Functionality / DescriptionP
in # Pin Name Analog Timers Communication Other
34 USB_VREGO
35 PC14 TIM0_CDTI1 #1/6
TIM1_CC1 #0PCNT0_S1IN #0
US0_CS #3US1_CS #3/4LEU0_TX #5
USB_DM
PRS_CH0 #2
36 PC15 TIM0_CDTI2 #1/6
TIM1_CC2 #0
US0_CLK #3US1_CLK #3LEU0_RX #5
USB_DP
PRS_CH1 #2
37 PF0 TIM0_CC0 #5US1_CLK #2LEU0_TX #3I2C0_SDA #5
DBG_SWCLK #0BOOT_TX
38 PF1 TIM0_CC1 #5US1_CS #2LEU0_RX #3I2C0_SCL #5
DBG_SWDIO #0GPIO_EM4WU3
BOOT_RX
39 PF2 TIM0_CC2 #5/6TIM2_CC0 #3
US1_TX #4LEU0_TX #4
CMU_CLK0 #3PRS_CH0 #3
GPIO_EM4WU4
40 PF3 TIM0_CDTI0 #5 PRS_CH0 #1
41 PF4 TIM0_CDTI1 #5 PRS_CH1 #1
42 PF5 TIM0_CDTI2 #5 PRS_CH2 #1
43 IOVDD_5 Digital IO power supply 5.
44 VSS Ground.
45 PE10 TIM1_CC0 #1 US0_TX #0 PRS_CH2 #2
46 PE11 TIM1_CC1 #1 US0_RX #0 PRS_CH3 #2
47 PE12 ADC0_CH0TIM1_CC2 #1TIM2_CC1 #3
US0_RX #3US0_CLK #0/6I2C0_SDA #6
CMU_CLK1 #2PRS_CH1 #3
48 PE13 ADC0_CH1 TIM2_CC2 #3US0_TX #3
US0_CS #0/6I2C0_SCL #6
ACMP0_O #0PRS_CH2 #3
GPIO_EM4WU5
4.2 Alternate Functionality PinoutA wide selection of alternate functionality is available for multiplexing to various pins. This is shown inTable 4.2 (p. 52) . The table shows the name of the alternate functionality in the first column, followedby columns showing the possible LOCATION bitfield settings.
NoteSome functionality, such as analog interfaces, do not have alternate settings or a LOCA-TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-TION 0.
Table 4.2. Alternate functionality overview
Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.
ACMP0_O PE13 PD6 PB11 Analog comparator ACMP0, digital output.
ADC0_CH0 PE12 Analog to digital converter ADC0, input channel number 0.
ADC0_CH1 PE13 Analog to digital converter ADC0, input channel number 1.
ADC0_CH4 PD4 Analog to digital converter ADC0, input channel number 4.
ADC0_CH5 PD5 Analog to digital converter ADC0, input channel number 5.
ADC0_CH6 PD6 Analog to digital converter ADC0, input channel number 6.
ADC0_CH7 PD7 Analog to digital converter ADC0, input channel number 7.
BOOT_RX PF1 Bootloader RX.
BOOT_TX PF0 Bootloader TX.
CMU_CLK0 PA2 PD7 PF2 Clock Management Unit, clock output number 0.
CMU_CLK1 PA1 PE12 PB11 Clock Management Unit, clock output number 1.
DBG_SWCLK PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, andhas a built-in pull down.
DBG_SWDIO PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, andhas a built-in pull up.
GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4
GPIO_EM4WU6 PC4 Pin can be used to wake the system up from EM4
HFXTAL_N PB14 High Frequency Crystal negative pin. Also used as exter-nal optional clock input pin.
HFXTAL_P PB13 High Frequency Crystal positive pin.
I2C0_SCL PA1 PD7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA PA0 PD6 PC0 PF0 PE12 I2C0 Serial Data input / output.
IDAC0_OUT PB11 IDAC0 output.
LEU0_RX PD5 PB14 PF1 PA0 PC15 LEUART0 Receive input.
LEU0_TX PD4 PB13 PF0 PF2 PC14 LEUART0 Transmit output. Also used as receive input inhalf duplex communication.
LFXTAL_N PB8 Low Frequency Crystal (typically 32.768 kHz) negativepin. Also used as an optional external clock input pin.
LFXTAL_P PB7 Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC0 PD6 PA0 Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PC1 PD7 PB11 Pulse Counter PCNT0 input number 1.
PRS_CH0 PA0 PF3 PC14 PF2 Peripheral Reflex System PRS, channel 0.
PRS_CH1 PA1 PF4 PC15 PE12 Peripheral Reflex System PRS, channel 1.
PRS_CH2 PC0 PF5 PE10 PE13 Peripheral Reflex System PRS, channel 2.
PRS_CH3 PC1 PE11 PA0 Peripheral Reflex System PRS, channel 3.
TIM0_CC0 PA0 PA0 PA0 PF0 PA1 Timer 0 Capture Compare input / output channel 0.
TIM0_CC1 PA1 PA1 PC0 PF1 PA0 Timer 0 Capture Compare input / output channel 1.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
TIM0_CC2 PA2 PA2 PC1 PF2 PF2 Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0 PC2 PF3 Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1 PC14 PC3 PF4 PC14 Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2 PC15 PC4 PF5 PC15 Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.
TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB11 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PC8 PF2 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PC9 PE12 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PC10 PE13 Timer 2 Capture Compare input / output channel 2.
US0_CLK PE12 PC9 PC15 PB13 PB13 PE12 USART0 clock input / output.
US0_CS PE13 PC8 PC14 PB14 PB14 PE13 USART0 chip select input / output.
US0_RX PE11 PC10 PE12 PB8 PC1 PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output(MISO).
US0_TX PE10 PE13 PB7 PC0 PC0
USART0 Asynchronous Transmit.Also used as receive in-put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input(MOSI).
US1_CLK PB7 PF0 PC15 PB11 PC3 USART1 clock input / output.
US1_CS PB8 PF1 PC14 PC14 PC0 USART1 chip select input / output.
US1_RX PC1 PD6 PD6 PA0 PC2
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output(MISO).
US1_TX PC0 PD7 PD7 PF2 PC1
USART1 Asynchronous Transmit.Also used as receive in-put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input(MOSI).
USB_DM PC14 USB D- pin.
USB_DMPU PA0 USB D- Pullup control.
USB_DP PC15 USB D+ pin.
USB_VREGI USB_VREGI USB Input to internal 3.3 V regulator
USB_VREGO USB_VREGO USB Decoupling for internal 3.3 V USB regulator and reg-ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32HG322 is shown in Table 4.3 (p. 55) . Each GPIO port isorganized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicatedby a number from 15 down to 0.
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Table 4.3. GPIO Pinout
Port Pin15
Pin14
Pin13
Pin12
Pin11
Pin10
Pin9
Pin8
Pin7
Pin6
Pin5
Pin4
Pin3
Pin2
Pin1
Pin0
Port A - - - - - PA10 PA9 PA8 - - - - - PA2 PA1 PA0
Port B - PB14 PB13 - PB11 - - PB8 PB7 - - - - - - -
Port C PC15 PC14 - - - PC10 PC9 PC8 - - - PC4 PC3 PC2 PC1 PC0
Port D - - - - - - - - PD7 PD6 PD5 PD4 - - - -
Port E - - PE13 PE12 PE11 PE10 - - - - - - - - - -
Port F - - - - - - - - - - PF5 PF4 PF3 PF2 PF1 PF0
4.4 TQFP48 Package
Figure 4.2. TQFP48
Note:
1. Dimensions and tolerance per ASME Y14.5M-19942. Control dimension: Millimeter.3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead exists
from the plastic body at the bottom of the parting line.4. Datums T, U and Z to be determined at datum plane AB.5. Dimensions S and V to be determined at seating plane AC.6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimen-
sions A and B do include mold mismatch and are determined at datum AB.7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimension
to exceed 0.350.8. Minimum solder plate thickness shall be 0.0076.
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9. Exact shape of each corner is optional.
Table 4.4. QFP48 (Dimensions in mm)
DIM MIN NOM MAX DIM MIN NOM MAX
A - 7.000 BSC - M - 12DEG REF -
A1 - 3.500 BSC - N 0.090 - 0.160
B - 7.000 BSC - P - 0.250 BSC -
B1 - 3.500 BSC - R 0.150 - 0.250
C 1.000 - 1.200 S - 9.000 BSC -
D 0.170 - 0.270 S1 - 4.500 BSC -
E 0.950 - 1.050 V - 9.000 BSC -
F 0.170 - 0.230 V1 - 4.500 BSC -
G - 0.500 BSC - W - 0.200 BSC -
H 0.050 - 0.150 AA - 1.000 BSC -
J 0.090 - 0.200
K 0.500 - 0.700
L 0DEG - 7DEG
The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch.
The TQFP48 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. TQFP48 PCB Land Pattern
e
a
d
c
bp1
p2
p3 p4
p5
p6
p7p8
Table 5.1. QFP48 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol Dim. (mm) Symbol Pin number Symbol Pin number
a 1.60 P1 1 P6 36
b 0.30 P2 12 P7 37
c 0.50 P3 13 P8 48
d 8.50 P4 24 - -
e 8.50 P5 25 - -
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Figure 5.2. TQFP48 PCB Solder Mask
e
a
d
c
b
Table 5.2. QFP48 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.72
b 0.42
c 0.50
d 8.50
e 8.50
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Figure 5.3. TQFP48 PCB Stencil Design
e
a
d
c
b
Table 5.3. QFP48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol Dim. (mm)
a 1.50
b 0.20
c 0.50
d 8.50
e 8.50
1. The drawings are not to scale.2. All dimensions are in millimeters.3. All drawings are subject to change without notice.4. The PCB Land Pattern drawing is in compliance with IPC-7351B.5. Stencil thickness 0.125 mm.6. For detailed pin-positioning, see Figure 4.2 (p. 55) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 60) .
6.3 Errata
Please see the errata document for EFM32HG322 for description and resolution of device erratas. Thisdocument is available in Simplicity Studio and online at:http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 0.90
March 16th, 2015
Corrected EM2 current consumption condition in Electrical Characteristics section.
Updated GPIO electrical characteristics.
Updated Max ESRHFXO value for Crystal Frequency of 25 MHz.
Updated LFRCO plots.
Updated HFRCO table and plots.
Updated ADC table and temp sensor plot.
Added DMA current in Digital Peripherals section.
Updated block diagram.
7.2 Revision 0.20
December 11th, 2014
Preliminary Release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentationof all peripherals and modules available for system and software implementers using or intending to usethe Silicon Laboratories products. Characterization data, available modules and peripherals, memorysizes and memory addresses refer to each specific device, and "Typical" parameters provided can anddo vary in different applications. Application examples described herein are for illustrative purposes only.Silicon Laboratories reserves the right to make changes without further notice and limitation to productinformation, specifications, and descriptions herein, and does not give warranties as to the accuracyor completeness of the included information. Silicon Laboratories shall have no liability for the conse-quences of use of the information supplied herein. This document does not imply or express copyrightlicenses granted hereunder to design or fabricate any integrated circuits. The products must not beused within any Life Support System without the specific written consent of Silicon Laboratories. A "LifeSupport System" is any product or system intended to support or sustain life and/or health, which, if itfails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratoriesproducts are generally not intended for military applications. Silicon Laboratories products shall under nocircumstances be used in weapons of mass destruction including (but not limited to) nuclear, biologicalor chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registeredtrademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other productsor brand names mentioned herein are trademarks of their respective holders.
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B Contact InformationSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701
Please visit the Silicon Labs Technical Support web page:http://www.silabs.com/support/pages/contacttechnicalsupport.aspxand register to submit a technical support request.
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Table of Contents1. Ordering Information .................................................................................................................................. 22. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 32.2. Configuration Summary .................................................................................................................... 62.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 83.1. Test Conditions .............................................................................................................................. 83.2. Absolute Maximum Ratings .............................................................................................................. 83.3. General Operating Conditions ........................................................................................................... 83.4. Current Consumption ....................................................................................................................... 93.5. Transition between Energy Modes .................................................................................................... 163.6. Power Management ....................................................................................................................... 163.7. Flash .......................................................................................................................................... 173.8. General Purpose Input Output ......................................................................................................... 173.9. Oscillators .................................................................................................................................... 263.10. Analog Digital Converter (ADC) ...................................................................................................... 313.11. Current Digital Analog Converter (IDAC) .......................................................................................... 403.12. Analog Comparator (ACMP) .......................................................................................................... 453.13. Voltage Comparator (VCMP) ......................................................................................................... 473.14. I2C ........................................................................................................................................... 473.15. USB .......................................................................................................................................... 483.16. Digital Peripherals ....................................................................................................................... 48
4. Pinout and Package ................................................................................................................................. 504.1. Pinout ......................................................................................................................................... 504.2. Alternate Functionality Pinout .......................................................................................................... 524.3. GPIO Pinout Overview ................................................................................................................... 544.4. TQFP48 Package .......................................................................................................................... 55
5. PCB Layout and Soldering ........................................................................................................................ 575.1. Recommended PCB Layout ............................................................................................................ 575.2. Soldering Information ..................................................................................................................... 59
6. Chip Marking, Revision and Errata .............................................................................................................. 606.1. Chip Marking ................................................................................................................................ 606.2. Revision ...................................................................................................................................... 606.3. Errata ......................................................................................................................................... 60
7. Revision History ...................................................................................................................................... 617.1. Revision 0.90 ............................................................................................................................... 617.2. Revision 0.20 ............................................................................................................................... 61
A. Disclaimer and Trademarks ....................................................................................................................... 62A.1. Disclaimer ................................................................................................................................... 62A.2. Trademark Information ................................................................................................................... 62
B. Contact Information ................................................................................................................................. 63B.1. ................................................................................................................................................. 63
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List of Figures2.1. Block Diagram ....................................................................................................................................... 32.2. EFM32HG322 Memory Map with largest RAM and Flash sizes ........................................................................ 73.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 24MHz ........................................................................................................................................................ 103.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21MHz ........................................................................................................................................................ 103.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14MHz ........................................................................................................................................................ 113.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11MHz ........................................................................................................................................................ 113.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 6.6MHz ........................................................................................................................................................ 123.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 24 MHz .............................. 123.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 133.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 133.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 143.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6 MHz ........................... 143.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 153.12. EM3 current consumption. ................................................................................................................... 153.13. EM4 current consumption. ................................................................................................................... 163.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 203.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 213.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 223.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 233.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 243.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 253.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 273.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 283.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 293.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 293.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 293.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 303.26. Integral Non-Linearity (INL) ................................................................................................................... 353.27. Differential Non-Linearity (DNL) .............................................................................................................. 353.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 363.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 373.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 383.31. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 393.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 393.33. ADC Temperature sensor readout ......................................................................................................... 403.34. IDAC Source Current as a function of voltage on IDAC_OUT ....................................................................... 433.35. IDAC Sink Current as a function of voltage from IDAC_OUT ........................................................................ 443.36. IDAC linearity .................................................................................................................................... 443.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 464.1. EFM32HG322 Pinout (top view, not to scale) ............................................................................................. 504.2. TQFP48 .............................................................................................................................................. 555.1. TQFP48 PCB Land Pattern ..................................................................................................................... 575.2. TQFP48 PCB Solder Mask ..................................................................................................................... 585.3. TQFP48 PCB Stencil Design ................................................................................................................... 596.1. Example Chip Marking (top view) ............................................................................................................. 60
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List of Tables1.1. Ordering Information ................................................................................................................................ 22.1. Configuration Summary ............................................................................................................................ 63.1. Absolute Maximum Ratings ...................................................................................................................... 83.2. General Operating Conditions ................................................................................................................... 83.3. Current Consumption ............................................................................................................................... 93.4. Energy Modes Transitions ...................................................................................................................... 163.5. Power Management ............................................................................................................................... 173.6. Flash .................................................................................................................................................. 173.7. GPIO .................................................................................................................................................. 173.8. LFXO .................................................................................................................................................. 263.9. HFXO ................................................................................................................................................. 263.10. LFRCO .............................................................................................................................................. 273.11. HFRCO ............................................................................................................................................. 283.12. AUXHFRCO ....................................................................................................................................... 303.13. USHFRCO ......................................................................................................................................... 303.14. ULFRCO ............................................................................................................................................ 313.15. ADC .................................................................................................................................................. 313.16. IDAC Range 0 Source ......................................................................................................................... 403.17. IDAC Range 0 Sink ............................................................................................................................. 403.18. IDAC Range 1 Source ......................................................................................................................... 413.19. IDAC Range 1 Sink ............................................................................................................................. 413.20. IDAC Range 2 Source ......................................................................................................................... 413.21. IDAC Range 2 Sink ............................................................................................................................. 413.22. IDAC Range 3 Source ......................................................................................................................... 423.23. IDAC Range 3 Sink ............................................................................................................................. 423.24. IDAC ................................................................................................................................................. 423.25. ACMP ............................................................................................................................................... 453.26. VCMP ............................................................................................................................................... 473.27. I2C Standard-mode (Sm) ...................................................................................................................... 473.28. I2C Fast-mode (Fm) ............................................................................................................................ 483.29. I2C Fast-mode Plus (Fm+) .................................................................................................................... 483.30. Digital Peripherals ............................................................................................................................... 484.1. Device Pinout ....................................................................................................................................... 504.2. Alternate functionality overview ................................................................................................................ 524.3. GPIO Pinout ........................................................................................................................................ 554.4. QFP48 (Dimensions in mm) .................................................................................................................... 565.1. QFP48 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 575.2. QFP48 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 585.3. QFP48 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 59
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List of Equations3.1. Total ACMP Active Current ..................................................................................................................... 453.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 47