E.Fullana, J. Torres, J. Castelo Speaker: Jose Castelo IFIC - Universidad de Valencia Tile...

E.Fullana, J. Torres, J. CasteloSpeaker: Jose Castelo

IFIC - Universidad de Valencia Tile Calorimeter – ROD

Colmar, 11 Sept. 2002

ROD General Requirementsand

Present Hardware Solution for the ATLAS Tile Calorimeter

LECC 2002, 8th Workshop on Electronics for LHC Experiments, Colmar

Introduction: Basic functionalities

DATA PROCESSING: Raw Data gathering from FE at the L1A event rate 100Khz to ROBS with intermediate processing and formatting.

TRIGGER: TTC signals will be present (latency ~2s after L1A) at each module providing ROD L1ID, ROD BCID and Ttype (trigger type).

ERROR DETECTION: Synchronism Trigger Tasks. The ROD must check that the BCID and L1ID numbers received from CTP match with the ones received from the FEB. If a mismatch is detected an error flag must be reported.

DATA LINKS: Input data must be received with optical input RX. Event data processed must be sent to ROB through the standard ATLAS readout links and standard DAQ-1 data format at the L1A event rate (100khz).

BUSY GENERATION: Provide a ROD busy signal in order to stop L1A generation. This signal will be an OR function ROD crate modules and managed by the ROD TTC crate as an interface with CTP.

LOCAL MONITORING: VME access of the data during a run without introducing dead-time or additional latency in the main DAQ data. Each ROD motherboard are VME slaves commanded by the ROD Controller (VME SBC).


ATLAS TDAQ & Read-Out System

LVL1 decision taken with calorimeter data (coarse granularity) and muon trigger chambers data. Buffering is done on Detector Electronics.

LVL2 is using Region of Interest data (up to 4% of whole event) with full granularity and combines information from all detectors. Buffering is implemented in ROBs.

EF refines the selection, can perform event reconstruction at full granularity using latest alignment and calibration data. Buffering in EB & EF

RODs


9856 calorimeter channels. (Two fibers/drawer. 19712 ch with redundant info)

PARTIONMASTER 4

PARTIONMASTER 3

PARTIONMASTER 2

PARTION MASTER 1

ROD CRATE 2

32 RODs/ 64ROBsROD/ROB Mapping

1:2

ROD Crate

RO

D C

rate Controller

TB

M M

od

ule

RO

D 1

RO

D 2

RO

D 3

RO

D 8

TBM Bus (VME P3 backplane)

DAQ On-line software (network)

VME Bus (VME P1/P2 backplane)

BUSYTTC

TO/FROMCTP or TTCvi

ROD CRATE 2

S-Link Output:Dataflow to LVL2 ROB

ROD CRATE 1

ROD 1 ROD 8


ROD CRATE 4

ROD 32


TileCal Detector. 64 Modules

64 MODULES

FEB ROBFEB ROB8 8

2 2

DRAWER D32 channels

Extended Barrel

64 Drawers(2048ch )

DRAWER A45 channels

Barrel

64 Drawers(2880-ch )

DRAWER B45 channels

Barrel

64 Drawers(2880-ch )

DRAWER C32 channels

Extended Barrel

64 Drawers(2048ch )

TileCal ROD Dataflow and TTC partitions


ROD Crate

Crate Hardware: ROD Controller TTC interface (TBM): Trigger and

Busy Module FE, Calibration Cards: for data

injection, calibration, etc M RODs per N Crates: Motherboards

with Processing Units + Transition modules for Output optical links. Nowadays design M=8 and N=4. Total 32 ROD modules for 10.000 calorimeter cells acquisition.

Interface with Environment: ATLAS DAQ and TileCal Run Control:

Online Software CTP: Reception of TTC information

and management of a per crate ROD BUSY.

DATAFLOW: Process FEB events, detects synchronization errors, and send data to ROBs for ROIs lvl2 decision.

TTC signals from CTP

Crate OR BUSY to CTP

Online Software

Detector Data

Event Data


TCC scheme

Number of TTC partitions: 4

Organized around [0, 2]: EB(<0), CB(<0), CB(0), EB(0)

This distribution will allow us to work with only central barrels if there are not enough RODs in the early runs.

The scheme shown is for 4 partitions in two crates with 2 TBM (actually is only possible with 4 crates because TBM architecture design)

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D9

RO

D10

RO

D11

RO

D12

RO

D13

RO

D14

RO

D15

RO

D16

RO

D C

rate

1

Detector FEBs

To ROBs

TTC and BUSY Bus

TT

CP

arti

tio

n 1

&2

CO

NT

RO

LLE

R

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP

CTP

DataBase

Partition Master

4

2

LAN (e.g. ethernet)

TB

M

TTC and BUSY Bus

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP

2

TT

CP

arti

tio

n 3

&4

CO

NT

RO

LLE

R

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP

2

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D9

RO

D10

RO

D11

RO

D12

RO

D13

RO

D14

RO

D15

RO

D16

RO

D C

rate

2

Detector FEBs

To ROBs

TTC and BUSY Bus

TB

M

TTC and BUSY Bus

2

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D9

RO

D10

RO

D11

RO

D12

RO

D13

RO

D14

RO

D15

RO

D16

RO

D C

rate

1

Detector FEBs

To ROBs

TTC and BUSY Bus

TB

M

TTC and BUSY Bus

TT

CP

arti

tio

n 1

&2

CO

NT

RO

LLE

R

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP

DC

TP

I

TT

Cvi

TT

Cex

RO

D B

usy

‘OR

’

LTP


Tiles ROD Racks and interconnections between crates

USA15 room (radiation free) 2 Racks (52U) Standard 9U Atlas crates.

9U(slot) with transition module (probably 160mm). External size for CERN crates: 10U

Cooling: Air/water (not decided, it depends on the amount of power dissipated by G-LINK receivers)

Readout fibers: Input fibers (front in MB) Output fibers (rear TM)

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D C

rate

39U

(10

U)

Detector FEBs(Front panel fibres)

TTC and BUSY Bus

To ROBs(Rear transition module)

2

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D C

rate

49U

(10

U)

TTC and BUSY Bus

TT

CP

arti

tio

n 1

&3

6U (

7U)

CO

NT

RO

LL

ER

DC

TP

I

TT

Cvi

TT

Ce

x

RO

D B

usy

‘OR

’

LT

P

CTP

DataBase

Partition Master

4

2

LAN (e.g. ethernet)

DC

TP

I

TT

Cvi

TT

Ce

x

RO

D B

usy

‘OR

’

LT

P

TT

CP

arti

tio

n 2

&4

6U (

7U)

CO

NT

RO

LL

ER

DC

TP

I

TT

Cvi

TT

Ce

x

RO

D B

usy

‘OR

’

LT

P

DC

TP

I

TT

Cvi

TT

Ce

x

RO

D B

usy

‘OR

’

LT

P

2

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D C

rate

29U

(10

U)

TTC and BUSY Bus

RO

DC

TB

M

RO

D1

RO

D2

RO

D3

RO

D4

RO

D5

RO

D6

RO

D7

RO

D8

RO

D C

rate

19U

(10

U)

TTC and BUSY Bus

RACK 8 (52U) RACK 9 (52U)








Using new LArg ROD Motherboard for Tiles

9U ROD Motherboard (i+1)/2

P3

(160

pin)

P2

(160

pin)

P1

(160

pin)

PROCESSING UNIT 1

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 3

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 4

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

OutputController

FPGA

16@80MHz

16@80MHz

OutputController

FPGA

OutputController

FPGA

OutputController

FPGA

16@80MHz

16@80MHz

PROCESSING UNIT 2

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

32@40MHz

32@40MHz

Ser

ializ

er*

LVDSreceiver

SDRAM32

SDRAM32

SDRAM32

SDRAM32

2

2

2

2

8

TTCFPGA+TTCrx

40MHz

VMEFPGA

128@40MHz

16@80MHz

16@80MHz

16@80MHz

16@80MHz

J3 (

160p

in)

J2 (

160p

in)

9U Transition Module (i+1)/2

32@40MHz

32@40MHz

32@40MHz

32@40MHz

16

64

LV

DS D

riv

er

32

P0

DeS

eria

lizer

*

64

FIF

O

32@40MHz

32@40MHz

32@40MHz

32@40MHz

LVDSdriver16

LinkControlFPGA

S-LINK MezzanineDUAL ODIN or HOLA

Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or

32

32

32

32

CONTROLBus

128@40MHz

8 control

ROBi/4

*Serializers/Deserializers40MHz => 280MHz

Unipolar => Differential

1 Partition = 64

Drawers

i=1...64

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

5v

5v

5v

5v

5v

5v

5v

5v

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

80MHz 40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHzDra

wer

i+1

Dra

wer

i+2

Dra

wer

i+6

ROBi/4 -1

S-LINKControl

lines

Dra

wer

i+7

Dra

wer

i+5

Dra

wer

i+4

Dra

wer

i+3

Dra

wer

i


P3

(160

pin)

P2

(160

pin)

P1

(160

pin)

PROCESSING UNIT 1

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 3

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 4

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

OutputController

FPGA

16@80MHz

16@80MHz

OutputController

FPGA

OutputController

FPGA

OutputController

FPGA

16@80MHz

16@80MHz

PROCESSING UNIT 2

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

32@40MHz

32@40MHz

Ser

ializ

er*

LVDSreceiver

SDRAM32

SDRAM32

SDRAM32

SDRAM32

2

2

2

2

8

TTCFPGA+TTCrx

40MHz

VMEFPGA

128@40MHz

16@80MHz

16@80MHz

16@80MHz

16@80MHz

J3 (

160p

in)

J2 (

160p

in)


32@40MHz

32@40MHz

32@40MHz

32@40MHz

16

64

LV

DS D

riv

er

32

P0

DeS

eria

lizer

*

64

FIF

O

32@40MHz

32@40MHz

32@40MHz

32@40MHz

LVDSdriver16

LinkControlFPGA


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or

32

32

32

32

CONTROLBus

128@40MHz

8 control

ROBi/4



1 Partition = 64

Drawers

i=1...64

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

5v

5v

5v

5v

5v

5v

5v

5v

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

80MHz 40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHzDra

wer

i+1

Dra

wer

i+2

Dra

wer

i+6

ROBi/4 -1

S-LINKControl

lines

Dra

wer

i+7

Dra

wer

i+5

Dra

wer

i+4

Dra

wer

i+3

Dra

wer

i


P3

(160

pin)

P2

(160

pin)

P1

(160

pin)

PROCESSING UNIT 1

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 3

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 4

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

OutputController

FPGA

16@80MHz

16@80MHz

OutputController

FPGA

OutputController

FPGA

OutputController

FPGA

16@80MHz

16@80MHz

PROCESSING UNIT 2

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

32@40MHz

32@40MHz

Ser

ializ

er*

LVDSreceiver

SDRAM32

SDRAM32

SDRAM32

SDRAM32

2

2

2

2

8

TTCFPGA+TTCrx

40MHz

VMEFPGA

128@40MHz

16@80MHz

16@80MHz

16@80MHz

16@80MHz

J3 (

160p

in)

J2 (

160p

in)


32@40MHz

32@40MHz

32@40MHz

32@40MHz

16

64

LV

DS D

riv

er

32

P0

DeS

eria

lizer

*

64

FIF

O32@40MHz

32@40MHz

32@40MHz

32@40MHz

LVDSdriver16

LinkControlFPGA


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or

32

32

32

32

CONTROLBus

128@40MHz

8 control

ROBi/4



1 Partition = 64

Drawers

i=1...64

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

5v

5v

5v

5v

5v

5v

5v

5v

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

80MHz 40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHzDra

wer

i+1

Dra

wer

i+2

Dra

wer

i+6

ROBi/4 -1

S-LINKControl

lines

Dra

wer

i+7

Dra

wer

i+5

Dra

wer

i+4

Dra

wer

i+3

Dra

wer

i


Using LArg new motherboard. Hardware performance

LArg needs more processing power per link: 128 channels/link (LArg), 45 for CB and 32 for EB ch/link (tilecal); so only 2 Processing Units, and 2 Output Controllers plus SDRAM data storage are enough for Tiles dataflow needs. Some estimations: Input bandwidth. The maximum input BW of each link for a tilecal physic event is 467,2

Mbit/sec, so 4 links (4 drawers) is 1,825 Gbits/sec. Input bandwidth of the Processing Unit is 2,5Gbits/sec (64bits@40Mhz) => One PU has enough input BW for 4 links.

The processing unit. We need to process 154 channels (four drawers) in two TMS320C6414@600MHz DSPs (4800 MIPS each). This DSP has the same core with some improvements in number of registers and an enhanced DMA unit over the actual DSP we have tested is the TMS320C6202@250MHz (2000 MIPS). Our actual lab routines could process 45 channels in around 5,5s (assembler) or 15,5s (C code). Potentially, we could process 154 channels with the new PU TMS320C6414@600MHz with 9600MIPs (two DSPs) in 3,92 s (assembler) or around 11s (C language). Because our limit is 10s at LVL1 100KHz rate, thus if we believe in improvements in the C compiler from Texas Instruments, probably we could program the final system in a better maintainable C code and only with 2 Processing Unit mezzanines installed in the motherboard.

Output Bandwidth. The typical BW for 154 channels (four drawers) is 656 Mbits/sec. Then, an Output Controller FPGA of 1,28 Gbits/sec (32@40MHz) has enough BW for the output of each Processing Unit (154 channels each).

Transition Module: 2 mezzanine links are enough for this configuration.


From Tiles FEB electronics we need to adjust a simple VHDL change in FEB FPGAs (Glink HDMP1032 pin ESMPXENB=0)

From LArg new motherboard design we need: To connect the CAV line of the HDMP1024 to the Staging FPGA in

order to receive control words (not only data words). In the Figure this line is highlighted in RED color.

To connect the FLAGSEL line of HDMP1024 to Staging FPGA. LArg used the FLAG bit to mark the even and odd 16 bit fragments, and Tilecal use CAV (control bit) to mark the start of transmission and count for the even and odd 16 bit fragment. Tiles use the FLAG bit to mark the global CRC word so Tiles need FLAGSEL set high, and LArg set low, so is needed to connect this pin to Staging FPGA for maintaining compatibility. In Figure this line is highlighted in RED color.

The connection of FDIS, ACTIVE, LOOPEN and STAT1, seems to be correct since they are standard. The configuration is “Simplex method III”.

To replace the LArg 80MHz clock with Tiles 40MHz clock, (pinout compatible oscillators needed) for getting the right reference clock for the G-LINK receivers (Tiles uses HDMP1032@40MHz in the interface links).

Compatibility issues with LArg motherboard


Noise reduction of optimal filtering algorithm (OF) versus others algorithms (FF). Data: testbeam 2001

ROD SOFTWARE : OPTIMAL FILTERING ALGORITHM (I)

A multisampled method firstly developed for liquid ionization calorimeters. (See W.E. Cleland and E.G. Stern, Nucl. Instr. And Meth. A 338 (1994) 467)

Allows the reconstruction of Energy and time information.

Additionally minimizes the noise coming from thermal sources (electronics) and also from minimum bias events. (see plots)


Samples coming from the front end electronics:

S1

S2

S3

….

Sn

First Set of weights:

a1, a2, a3… an,

Second Set of weights:

b1, b2, b3… bn,

n

i ii aSKE1

n

i ii bSKE1

Energy information: E

Time information:

n

iii bS

E

K

1

ROD SOFTWARE : OPTIMAL FILTERING ALGORITHM (II)

Weights are obtained from noise atocorrelation matrix and ideal PMT shape waveform g(t).

The mathematical procedure uses Lagrange Multipliers in order to reduce the electronic noise factor (see E.Fullana’s talk @feb_tilecal_analysis_meeting)

samplesn

i ii EgpSK1

22 ))((

:ninformatioFit ofQuality


DSP Software Implementation: DSP Core Architecture

Based on Texas DSP C6202

Harvard Architecture: Program and data memory could be accessed at the same time.

FCLK

= 250Mhz . Cycle time = 4ns. 2000

MIPs

Data/Program Memory: 1Mbit (128kbyte)/ 2Mbit (64k 32bits)

DMA channels: 4

EMIF & HPI: 32bits

McBSP: 3

Timers: 2 (32 bit)

VCORE

: 1.8v / VI/O

: 3.3v

3 phase PIPELINE

8 independent ALUS. Load-Store Architecture With 32 32-Bit General-Purpose Registers (two banks of 16). All instruction conditional


DSP Software Implementation: OF Algorithm

Using Optimal filtering for obtain Energy, Tau, and 2.The implementation is considering 7 samples of 10 bits.Actual studies demonstrate that the resolution will not be

improved with different weights for each cell => Use of the same calibration constants table for all channels (this could be changed).

The calculations are 32bit integer except for Multiplication (16bits) due to DSP architecture. Always trying to get the maximum resolution of the integer ALU operations.

C and Assembler code were developed: compare two input languages for coding the algorithm


C vs. Assembler

Energy/Tau/2 algorithm for 45 channels and 7 samples of 10bit. Compilation characteristics comparative for the best speed performance profiling option:

N u m b ercycles

C od e S ize

(b y te s )

T ota l tim e forE n erg y, tim e and 2

(C y c le = 4 n s )

T ota l tim e for D S Pp rog ra m : A lg o r i th m ,D M A s c h ed u le , B u sy

L o g ic , f i l te rh is to g ra m s ,...

M ain ta inab ilityS ou rce

C od e L in es

A ssem b ler 9 8 226976(2 7 k b ) 3 ,9 2 8s

5 ,4 2 8s

(~1,5s overhead)D iffic u lt 7 2 7 1

C co d e 3 5 2 42228

(2 ,1 7 k b ) ss

(~1,5s overhead)E a sy 1 6 0


Actual developments: Staging FPGA (I)

Online dataflow: Routes the incoming data from the different FEB inputs and send it to the

connector of the PU concerned, depending if it is staging or not. This feature provides the possibility to use only two processing units instead of four, routing the data to the desired PU (the staging is configured through VMEbus).

Glink chips configuration that will be performed by the staging chips. It gets the temperature of the Glink and transmits it to the VME chip (generates

an IRQ). Because these chip usually has high power consumption. It transmits the Glink errors (parity and ready) to the PUs and to the VME.

During the tests it will: Read the Glink data and transfer it to the VME. Transfer data from the VME to the PU. Similar function as 'data distributor block'

in the demonstrator board. Transfer at high rate some pattern data to the PU.

The code must be written in VHDL because of maintainability reasons.


P3

(160

pin

)P

2 (1

60p

in)

P1

(160

pin

)

PROCESSING UNIT 1

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 3

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

PROCESSING UNIT 4

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

OutputController

FPGA

16@80MHz

16@80MHz

OutputController

FPGA

OutputController

FPGA

OutputController

FPGA

16@80MHz

16@80MHz

PROCESSING UNIT 2

InputFPGA

DSP

OutputFPGA

DSP

FIFO

FIFO

32@40MHz

32@40MHz

Ser

iali

zer*

LVDSreceiver

SDRAM32

SDRAM32

SDRAM32

SDRAM32

2

2

2

2

8

TTCFPGA+TTCrx

40MHz

VMEFPGA

128@40MHz

16@80MHz

16@80MHz

16@80MHz

16@80MHz

J3 (

160p

in)

J2 (

160p

in)


32@40MHz

32@40MHz

32@40MHz

32@40MHz

16

64

LV

DS D

rive

r

32

P0

De

Ser

ializ

er*

64

FIF

O

32@40MHz

32@40MHz

32@40MHz

32@40MHz

LVDSdriver16

LinkControlFPGA


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or


Link

Con

nect

or

32

32

32

32

CONTROLBus

128@40MHz

8 control

ROBi/4



1 Partition = 64

Drawers

i=1...64

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

5v

5v

5v

5v

5v

5v

5v

5v

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

G-LINKRX

HDMP1024

80MHz 40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHz

16@40MHz 16@40MHz

16@40MHz

16@40MHz

16@40MHz

StagingFPGA

16@40MHz

16@40MHzDra

we

r i+

1D

raw

er

i+2

Dra

we

r i+

6

ROBi/4 -1

S-LINKControl

lines

Dra

we

r i+

7D

raw

er

i+5

Dra

we

r i+

4D

raw

er

i+3

Dra

we

r i


Actual developments: Staging FPGA (II)

GLINK_1data

Buffering

GLINK1_DATA[15..0]

GL1_FLAGGL1_CLK80/40

GL1_DAVnGL1_CAVn

GL1_ERRORGL1_FLAGSEL

GL1_LINKRDYn

STAG1_FLAG

STAG1_RESET

GLINK_2data

Buffering

GLINK2_DATA[15..0]

GL2_FLAGGL2_CLK80/40

GL2_DAVnGL2_CAVn

GL2_ERRORGL2_FLAGSEL

GL2_LINKRDYn

STAG2_RESET

GL1[15..0]

GL1_FLAG

GL1_ERROR

GL1_LINKRDYn

GL2[15..0]

GL2_FLAG

GL2_ERROR

GL2_LINKRDYn

GL1_RESET

GL2_RESET

FE

B1_

DA

TA

[15.

.0]

FE

B1_

ER

RO

R

FE

B1_

LIN

KR

DY

n

FE

B1_

FL

AG

STAG1_ERRORSTAG1_LINKRDYn

STAG2_FLAGSTAG2_ERROR

STAG2_LINKRDYn

FE

B2_

DA

TA

[15.

.0]

FE

B2_

ER

RO

R

FE

B2_

LIN

KR

DY

n

FE

B2_

FL

AG

FE

B1_

DA

TA

s[15

..0]

FE

B1_

ER

RO

Rs

FE

B1_

LIN

KR

DY

ns

FE

B1_

FL

AG

s

FE

B2_

DA

TA

s[15

..0]

FE

B2_

ER

RO

Rs

FE

B2_

LIN

KR

DY

ns

FE

B2_

FL

AG

s

STAG1_DATA[15..0]

STAG2_DATA[15..0]

DATAFLOW Management UNIT

VMECONTROL

UNIT

STAGINGFPGA

CONTROL

VME_ctrl_in

VME_ctrl_out

VME_byte_in[3..0]

VME_byte_out[3..0]

CSn

SCLK

MOSI

MISO

STROBE

RSTn

TTC_CLK40MHZ

PLL_CLK80MHZ

TTC_CLK40MHZ

PLL_CLK80MHZ

INIT

_Tem

p

En

_Tem

p

INIT

_VM

E

En

_VM

E

INIT_VME

En_VME

TTC_CLK40MHZ

PLL_CLK80MHZ

TTC_CLK40MHZ

PLL_CLK80MHZ

DATA[32..0]

VM

E_I

RQ

INIT_data

En_data

Dat

a_V

ME

[32.

.0]

AD

R_V

ME

[3..0

]

GLINKTemperature

Control

R/W

n

AD

C[7..0]

R/W

n

FE

B In

terf

ace

ST

AG

ING

In

terf

ac

e

Sta

gin

gF

PG

A c

on

tro

lV

ME

in

terf

ac

eA

DC

In

terf

ac

e

PU Interface


Summary

Work with ROD demonstrator board were very useful and instructive

Waiting for the first prototypes of new motherboard and studying LArg and Tilecal compatibilities for a common ROD board for ATLAS calorimeters

Programming a versatile program of Staging FPGA compliant with tilecal and LArg

Optimal Filtering studies and analysis were successful for 1998 testbeam data. Actually this work is focused over 2001 and 2002 tilecal testbeam data. Better results are expected with final FEB electronics mounted on these test beams (real electronic noise).

DSP implementation of Optimal Filtering under 10s (100KHz atlas lvl1 rate) in ASSEMBLER, but not in “C” using 250MHz C6202 DSP. We expect to be below this threshold with new generation PU with 600MHz C6414

DAQ (online software) integration of demonstrator board.

Date post:	20-Dec-2015
Category:	Documents
View:	215 times
Download:	1 times

E.Fullana, J. Torres, J. Castelo Speaker: Jose Castelo IFIC - Universidad de Valencia Tile...

Documents