ELCT 501: Digital System Design - GUCeee.guc.edu.eg/Courses/Electronics/ELCT501 Digital System...

ELCT 501:

Digital System Design

Lecture 2: Memory and Programmable Logic

Dr. Mohamed Abd El Ghany,

Department of Electronics and Electrical Engineering

Memory

2 Dr. Mohamed Abd el Ghany


Random Access Memory

(RAM)

Read-Only Memory

(ROM)

Can be read and written

Static Random Access Memory

(SRAM)

Data stored so long as vdd

is applied

6-transistors per cell

Faster

Dynamic Random Access

Memory (DRAM)

Require periodic refresh

Smaller (can be

implemented by 1 or 3

transistors)

slower

A memory device in which permanent

binary information is stored

Mask ROM: The programming is done by

the semiconductor company during the

last fabrication process of the unit

PROM: Once the PROM is programmed,

it cannot be reversed

EPROM: An erasable PROM and can be

erased by exposure to UV light

EEPROM: Can be erased and

programmed with electrical pulses

Flash memory: High-density read/write

memories that are nonvolatile. They have

the ability to retain charge for years with

no applied power

ELCT 501: Digital System

Design

Winter 2011

Block Diagram of Memory



2k words N-bit per word

Memory Unit

N-bit Data Input (for Write)

N-bit Data Output (for Read)

K-bit address lines

Read/Write

Chip Enable

N

N

K

Example: 2MB memory, byte-addressable

-N =8 (because of byte-addressability)

-K= 21 (1 word= 8-bit)


Design

Winter 2011

Static Random Access Memory

(SRAM)



BitLine BitLine

Wordline (WL)

Typically each bit is implemented with 6 transistors (6T SRAM Cell)

During read, the bitline and its inverse are precharged to Vdd (1) before set

WL=1

During write, put the value on Bitline and its inverse on Bitline_bar before

set WL=1


Design

Winter 2011

Dynamic Random Access Memory

(DRAM)



1-transistor DRAM cell

During a write, put value on bitline and then set WL=1

During a read, prechage bitline to Vdd (1) before assert WL to 1

Storage decays, thus requires periodic refreshing (read-sense-write)

Bitline

Wordline (WL)


Design

Winter 2011

Memory Description



Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

Capacity of a memory is described as

# addresses x Word size


Design

Winter 2011

How to address Memory



1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory

2-to-4 Decoder

A0

A1

CS

Chip Select


Design

Winter 2011

How to address Memory







0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory 2-to-4 Decoder

A0=1

A1=0

CS

Chip Select=1

Access address = 0x1


Design

Winter 2011

Use 2 Decoders

9





0

1

2

3

2-to-4 Decoder Row Decoder

A1

A2

CS

1-to-2 Decoder Column Decoder

D0 D1 D2 D3

Tristate Buffer (read)

0 1

A0

Chip Select CS

Dr. Mohamed Abd el Ghany


8x4 Memory


Design

Winter 2011

Tristate Buffer



Input Output

En

Input Output

En

Output

En

En Input

Vdd

CMOS circuit

Could amplify signal

Typically used for signal

traveling e.g. bus


Design

Winter 2011

Bi-directional Bus using Tri-state

Buffer



Direction (control data flow for read/write)

A

B

Input/Output


Design

Winter 2011

Read/Write Memory

12





0

1

2

3


A1

A2

CS


D0 D1 D2 D3

0 1

A0

Chip Select CS

8x4 Memory

Rd / Wr = 0


Design

Winter 2011

Read/Write Memory

13





0

1

2

3


A0

A1

CS


D0 D1 D2 D3

0 1

A0

Chip Select=1 CS

8x4 Memory

Rd / Wr = 1


Design

Winter 2011

Building Memory in Hierarchy



D3

D2

D1

D0

A19 A18 A17

A0

1Mx4

R/W CS

D7

D6

D5

D4

A19 A18

1Mx4

R/W CS

A17

A0 CS

Design a 1Mx8 using

1Mx4 memory chips


Design

Winter 2011




Design a 2Mx4 using

1Mx4 memory chips

A19 A18 A17

A0

1Mx4

R/W CS

A19 A18 A17

A0

1Mx4

R/W CS

A20 1-to-2 Decoder

CS

1

0

D3

D2

D1

D0


Design

Winter 2011


16

Design a 2Mx8 using

1Mx4 memory chips

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

A19 A18 A17

A0

1Mx4

CS R/W

D7

D6

D5

D4

D3

D2

D1

D0

A19 A18 A17

A0

A20 1-to-2 Decoder

CS

1

0




Memory Model

Flat Memory Model

0x0A

0xB6

0x41

0xFC

Lower Memory Address

0x00000000

Higher Memory Address

0x00000001

0x00000002

0x00000003

0xFFFFFFFF 0x0D

32-bit address space

can address up to 4 GB

(232) different memory

locations


Design

Winter 2011



Endianness [Danny Cohen 91]

A byte ordering- How a multiple byte data word stored in memory

Endianness (from Gulliver’s Travels)

Big Endian

Most significant byte of a multi-byte word is stored at the lowest

memory address

E.g. Sun Sparc, PowerPC

Little Endian

Least significant byte of a multi-byte word is stored at the lowest

memory address

e.g. Intel x86

Some embedded & DSP processors would support both for interoperability


Design

Winter 2011



Endianness Examples

Store 0x21436587 at address 0x0000

0x87

0x65

0x43

0x21



0x0000

0x0001

0x0002

0x0003

BIG ENDIAN

0x21

0x43

0x65

0x87



0x0000

0x0001

0x0002

0x0003

LITTLE ENDIAN


Design

Winter 2011



“Permanent” binary information is stored

Non-volatile memory

Power off does not erase information stored

Read Only Memory (ROM)

2k words N-bit per work

ROM N-bit Data Output

K-bit address lines

N K


Design

Winter 2011



32x8 ROM

32x8 ROM 8 5

0 1 2 3

28 29 30 31

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32 Decoder

Each represents 32 wires

Fuse can be implemented as a diode or a pass transistor


Design

Winter 2011

Programming the 32x8 ROM

22

0 1 2

29 30 31

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32 Decoder



A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 1 1 0 0 0 1 0 1

0 0 0 0 1 1 0 0 0 1 0 1 1

0 0 0 1 0 1 0 1 1 0 0 0 0

… … … … … … … … … … … … …

1 1 1 0 1 0 0 0 1 0 0 0 0

1 1 1 1 0 0 1 0 1 0 1 1 0

1 1 1 1 1 1 1 1 0 0 0 0 1


Design

Winter 2011

Example: Lookup Table



X F(X)=X2

0 0

1 1

2 4

3 9

4 16

5 25

6 36

7 49

X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

Design a square lookup table for F(X)=X2 using ROM


Design

Winter 2011

Square Lookup Table using ROM



X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8 Decoder 4

5

6

7


Design

Winter 2011




X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8 Decoder 4

5

6

7

=X0

Not used


Design

Winter 2011




X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

0

1

2

3

F5 F4 F3 F2 F0

X2

X1

X0

3-to-8 Decoder 4

5

6

7

F1


Design

Winter 2011

Classifying Three Basic PLDs



Fixed AND plane (decoder)

Programmable OR plane

Programmable Connections

(Programmable) Read-Only Memory (ROM)

INPUT OUTPUT

Programmable OR plane

Programmable Connections

Programmable Logic Array (PLA)

Programmable AND plane

INPUT OUTPUT

Programmable AND plane

Fixed OR plane

Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers

INPUT OUTPUT

F/F


Design

Winter 2011

Programmable Logic Array (PLA)



C

B

A

C C B B A A

Programmable AND Plane

Programmable OR Plane

F2


Design

Winter 2011

Example using PLA



m(0,5,6,7)C)B,F2(A,

m(0,1,2,4) C)B,F1(A,

CBAACABF2

BCACABF1

CBCABAF1


Design

Winter 2011

Example using PLA



C

B

A

C C B B A A

CBAACABF2

BCACABF1

AB

AC

BC

A B C

F2 F1


Design

Winter 2011

PLA Device



A

B

IO1

IO2

IO1 IO1 B B A A IO2 IO2

Programmable AND Plane

Fixed OR Plane


Design

Winter 2011

PLA Device Design Example



A

B

IO1

IO2

IO1 IO1 B B A A

DCBADCADCBACABIO2

DCBACABIO1

D D C C

Not programmed


Design

Winter 2011

CPLD and FPGA [brown & Rose 96]



Complex Programmable Logic Device (CPLD)

Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnection

structure

Pioneered by Altera

Field-Programmable Gate Array (FPGA)

High logic capacity with large distributed interconnection structure

Logic capacity= number of 2-input NAND gates

Offers more narrow logic resources

CPLD offers logic resources with a wide number of inputs (AND planes)

Offer a higher ratio of Flip-flops to logic resources than CPLD

High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA


Design

Winter 2011

CPLD Structure



PLD PLD PLD PLD

PLD PLD PLD PLD

Logic block

Interconnects

I/O block


Design

Winter 2011

FPGA Structure



Logic block

I/O block

Interconnects


Design

Winter 2011

FPGA Programmability



Floating gate transistor

Used in EPROM and EEPROM

SRAM-controlled switch-Control

Pass transistors

Multiplexers (to determine how to route inputs)

Antifuse

Similar to fuse

Originally an Open-Circuit

One-Time Programmable (OTP)


Design

Winter 2011

References



Logic and Computer Design Fundamentals

by M. Morris Mano and Charles R. Kime. 4th

edition, Prentice Hall. 2008.

P. Marwedel: Embedded System Design,

Springer, 2006

“First Steps with Embedded Systems” Byte

Craft Limited


Design

Winter 2011

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