ELE432ADVANCED DIGITAL DESIGN

HACETTEPE UNIVERSITYController Design - Finite State Machines

Based on Lectures from George Mason and CMU

Suggested Readings

• P. Chu, FPGA Prototyping by VHDL Examples• Chapter 5, FSM

• S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design• Chapter 8, Synchronous Sequential Circuits• Sections 8.1-8.5• Chapter 8.10, Algorithmic State Machine

Datapathvs.

Controller

Structure of a Typical Digital System

Datapath(Execution

Unit)

Controller(Control

Unit)

Data Inputs

Data Outputs

Control Inputs

Status Outputs

Control Signals

StatusSignals

Datapath (Execution Unit)

• Manipulates and processes data• Performs arithmetic and logic operations, shifting, and other

data-processing tasks• Composed of registers, gates, multiplexers, decoders, adders,

comparators, ALUs, etc.• Provides all necessary resources and interconnects among

them to perform specified task• Interprets control signals from the Controller and generates

status signals for the Controller

Controller (Control Unit)

• Controls data movements in the Datapath by switching multiplexers and enabling or disabling resources

Example: enable signals for registersExample: control signals for muxes

• Provides signals to activate various processing tasks in the Datapath

• Determines the sequence the operations performed by Datapath

• Follows Some ‘Program’ or Schedule

Controller• Controller can be programmable or non-programmable• Programmable

• Has a program counter which points to next instruction• Instructions are held in a RAM or ROM externally• Microprocessor is an example of programmable controller

• Non-Programmable• Once designed, implements the same functionality• Another term is a “hardwired state machine” or “hardwired

instructions” (THIS WEEK)

Finite State Machines

• Digital Systems and especially their Controllers can be described as Finite State Machines (FSMs)

• FSM is a mathematical model of an entity that describes its behavior as a result of its past history and current inputs.

• Finite State Machines can be represented using• State Diagrams and State Tables - suitable for simple digital systems

with a relatively few inputs and outputs• Algorithmic State Machine (ASM) Charts - suitable for complex digital

systems with a large number of inputs and outputs• All these descriptions can be easily translated to the

corresponding synthesizable VHDL code

Hardware Design with RTL VHDL

Pseudocode

Datapath Controller

Blockdiagram

Blockdiagram

State diagramor ASM chart

VHDL code VHDL code VHDL code

Interface

Finite State MachinesRefresher

Finite State Machines (FSMs)

• Any Circuit with Memory Is a Finite State Machine• Even computers can be viewed as huge FSMs

• Design of an FSM Involves• Defining states• Defining transitions between states• Optimization / minimization

• Manual Optimization/Minimization Is Practical for Small FSMs Only

Moore FSM• Output Is a Function of a Present State Only

Present Stateregister

Next Statefunction

Outputfunction

Inputs

Present StateNext State

Outputs

clockreset

Moore Machine : state diagram

state 1 /output 1

state 2 /output 2

transitioncondition 1

transitioncondition 2

Mealy FSM• Output Is a Function of a Present State and Inputs

Next Statefunction

Outputfunction

Inputs

Present StateNext State

Outputs

Present Stateregister

clockreset

Mealy Machine :state diagram

state 1 state 2

transition condition 1 /output 1

transition condition 2 /output 2

Moore vs. Mealy FSM

• Moore and Mealy FSMs Can Be Functionally Equivalent• Equivalent Mealy FSM can be derived from Moore FSM and vice versa

• Mealy FSM Has Richer Description and Usually Requires Smaller Number of States

• Smaller circuit area• Mealy FSM Computes Outputs as soon as Inputs Change

• Mealy FSM responds one clock cycle sooner than equivalent Moore FSM• Moore FSM Has No Combinational Path Between Inputs and

Outputs• Moore FSM is more likely to have a shorter critical path

Which Way to Go?

Safer.Less likely to affect

the critical path.

Mealy FSM Moore FSM

Lower Area

Responds one clockcycle earlier

Fewer states

Moore FSM - Sequence “10”• Moore FSM that Recognizes Sequence “10”

S0 / 0 S1 / 0 S2 / 1

00

0

1

11

reset

Meaning of states:

S0: No elements of the sequenceobserved

S1: “1”observed

S2: “10”observed

Mealy FSM - Sequence “10”

• Mealy FSM that Recognizes Sequence “10”

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset

Moore & Mealy FSMs – Sequence “10”

clock

input

Moore

Mealy

0 1 0 0 0

S0 S1 S2 S0 S0

S0 S1 S0 S0 S0

Ex:Moore Machine State Graph and Table

• Easy to convert state graph to state table• Moore machine note output is function of the state

9/2/2012 – ECE 3561 Lect 7 Copyright 2012 - Joanne DeGroat, ECE, OSU 21

Ex:Mealy Machine State Graph and Table

• Mealy machine state graph and state table• In Mealy machine the output is a function of the state and the current input

9/2/2012 – ECE 3561 Lect 7 Copyright 2012 - Joanne DeGroat, ECE, OSU 22

FSMs in VHDL

• Finite State Machines can be easily described with processes• Synthesis Tools Understand FSM Description if Certain Rules

Are Followed• State transitions should be described in a process sensitive to

clock and asynchronous reset signals only• Output function described using rules for combinational logic, i.e.

as concurrent statements or a process with all inputs in the sensitivity list

Moore FSM – coding style 1

Present StateRegister

Next Statefunction

Outputfunction

Inputs

Present State

Next State

Outputs

clockreset

process(clock, reset)

concurrent statements

Mealy FSM – coding style 1

Next Statefunction

Outputfunction

Inputs

Present StateNext State

Outputs

Present StateRegister

clockreset

process(clock, reset)

concurrent statements

Moore FSM in VHDL Sequence “10”

• Moore FSM that Recognizes Sequence “10”

S0 / 0 S1 / 0 S2 / 1

00

0

1

11

reset

TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;

U_Moore: PROCESS (clock, reset)BEGIN

IF(reset = ‘1’) THENMoore_state <= S0;

ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS

WHEN S0 =>IF input = ‘1’ THEN

Moore_state <= S1; ELSE

Moore_state <= S0;END IF;

Moore FSM in VHDL Sequence “10”

WHEN S1 =>IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF;

WHEN S2 =>IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF;

END CASE;END IF;

END PROCESS;Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

Moore FSM – Sequence more than two “11” : State diagram

C z 1 =

Reset

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

Present Next state Outputstate w = 0 w = 1 z

A A B 0 B A C 0 C A C 1

Moore FSM – Sequence more than two “11” : State diagram

w

w

w 0 1

0

1

0

1

A

B

C

z

Reset

w

w

w 0 1

0

1

0

1

A

B

C

z

Reset Moore FSM – Sequence more than two “11” - ASM Chart

CASE y ISWHEN A =>

IF w = '0' THEN y <= A ;

ELSE y <= B ;

END IF ;WHEN B =>

IF w = '0' THENy <= A ;

ELSEy <= C ;

END IF ;WHEN C =>

IF w = '0' THENy <= A ;

ELSEy <= C ;

END IF ;END CASE ;

END IF ;END PROCESS ;z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;

Example Sequence more than two “11” : VHDL code

USE ieee.std_logic_1164.all ;

ENTITY simple ISPORT ( clock : IN STD_LOGIC ;

resetn : IN STD_LOGIC ;w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;END simple ;

ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;

BEGINPROCESS ( resetn, clock )BEGIN

IF resetn = '0' THENy <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

Mealy FSM in Sequence “10” in VHDL

TYPE state IS (S0, S1);SIGNAL Mealy_state: state;

U_Mealy: PROCESS(clock, reset)BEGIN

IF(reset = ‘1’) THENMealy_state <= S0;

ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS

WHEN S0 =>IF input = ‘1’ THEN

Mealy_state <= S1; ELSE

Mealy_state <= S0;END IF;

WHEN S1 =>IF input = ‘0’ THEN

Mealy_state <= S0; ELSE

Mealy_state <= S1;END IF;END CASE;

END IF;END PROCESS;

Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

S0 S1

0 / 0 1 / 0 1 / 0

0 / 1reset

A

w 0 = z 0 =

w 1 = z 1 = B w 0 = z 0 =

Reset

w 1 = z 0 =

Mealy FSM – Sequence more than two “11”’s : State diagram

ASM Chart for Mealy FSM – Sequence more than two “11”’s

w

w 0 1

0

1

A

B

Reset

z

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;

resetn : IN STD_LOGIC ;w : IN STD_LOGIC ;z : OUT STD_LOGIC ) ;

END Mealy ;

ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;

BEGINPROCESS ( resetn, clock )BEGIN

IF resetn = '0' THENy <= A ;

ELSIF (clock'EVENT AND clock = '1') THEN

Sequence more than two “11”’s : VHDL codeCASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

z <= '1' WHEN (y = B) AND (w=‘1’) ELSE '0' ;

END Behavior ;

Alternative Coding Style

Based on RTL Hardware Design by P. Chu

Process(clk, reset)

Process(Present State, Input)

Next StatePresent State

Implementation of FSM in VHDL

Architecture Declarationarchitecture rtl of four_state_mealy_state_machine is-- Build an enumerated type for the state machinetype state_type is (s0, s1, s2); -- definition of state-- Register to hold the current statesignal state : state_type; -- definition of register of inner statesbegin – architecture beginning--- there are a couple of approaches here

process (clk, reset) -- process for creating statebegin

if reset = '1' then -- async reset of machinestate <= s0; -- default state after reset

elsif (rising_edge(clk)) then -- sync part of machinecase state is -- use CASE for FSMwhen s0=> -- description of transitional conditions for state 0

if input = '1' thenstate <= s1;

elsestate <= s0;

end if;when s1=> -- description of transitional conditions for state 1

if input = '1' thenstate <= s2;

elsestate <= s1;

end if;…

end case;end if;

end process;

process (state, input)begin

case state is -- use CASE for FSM implementationwhen s0=> -- output description for state 0

if input = '1' thenoutput <= "00"; -- output definitionelseoutput <= "01"; -- output definitionend if;

when s1=> -- output description for state 1if input = '1' thenoutput <= "01"; -- output definitionelseoutput <= "11"; -- output definition

end if;end case;…

end process; -- end keyword for processend rtl; -- end keyword for architecture rtl

Summary

• Definition of entity• Definition of architecture – inside – enum. type for declaration of

FSM states• 1 process for description of transitional conditions• 1 process for description of output signals• Both processes can be concated in only one

ASM Chart of Moore Machine S0

reset

input

S1

S2

input

input

0

1

0

1

1 0

output

Moore FSM in VHDL (1)

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY FSM_Moore_2 ISPORT ( clk : IN STD_LOGIC ;

reset : IN STD_LOGIC ;input : IN STD_LOGIC ;output : OUT STD_LOGIC) ;

END FSM_Moore_2 ;

ARCHITECTURE behavioral of FSM_Moore_2 ISTYPE state IS (S0, S1, S2);SIGNAL Present_State, Next_State: state;

BEGIN

U_Moore: PROCESS (clk, reset)BEGIN

IF(reset = '1') THENPresent_State <= S0;

ELSIF rising_edge(clk) THENPresent_State <= Next_State;

END IF;END PROCESS;

Moore FSM in VHDL (2)WHEN S1 =>

IF input = '0' THEN

Next_State <= S2;

ELSE

Next_State <= S1;

END IF;

WHEN S2 =>

output <= '1' ;

IF input = '1' THEN

Next_State <= S1;

ELSE

Next_State <= S0;

END IF;

END CASE;

END PROCESS;

END behavioral;

Next_State_Output:

PROCESS (Present_State, input)

BEGIN

Next_State <= Present_State;

output <= '0';

CASE Present_State IS

WHEN S0 =>

IF input = '1' THEN

Next_State <= S1;

ELSE

Next_State <= S0;

END IF;

ASM Chart of Mealy Machine

S0

S1

reset

input

input

output

0

1

1 0

Mealy FSM in VHDL (1)

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY FSM_Mealy_2 ISPORT ( clk : IN STD_LOGIC ;

reset : IN STD_LOGIC ;input : IN STD_LOGIC ;output : OUT STD_LOGIC) ;

END FSM_Mealy_2 ;

Mealy FSM in VHDL (1)

ARCHITECTURE behavioral of FSM_Mealy_2 ISTYPE state IS (S0, S1);SIGNAL Present_State, Next_State: state;

BEGINU_Mealy: PROCESS(clk, reset)BEGIN

IF(reset = '1') THENPresent_State <= S0;

ELSIF rising_edge(clk) THENPresent_State <= Next_State;

END IF;END PROCESS;

Mealy FSM in VHDL (2)

Next_State_Output: PROCESS (Present_State, input)BEGIN

Next_State <= Present_State;output <= '0';CASE Present_State IS

WHEN S0 =>IF input = '1' THEN

Next_State <= S1; ELSE

Next_State <= S0;END IF;

WHEN S1 =>

IF input = '0' THEN

Next_State <= S0;

Output <= '1' ;

ELSE

Next_State <= S1;

END IF;

END CASE;

END PROCESS;

END behavioral;

Example : Another Sequence Detector• Design a sequence detector using D flip-flops and 8-to-1

multiplexers.• The sequence detector outputs a 1 when exactly two of the

last three inputs are 1.▫ An input of 011011100 produces

the output of 001111010• There is a one-bit serial input line and we will assume that

initially no inputs have been seen.• Note: the sequence detector cannot output a 1 until at least

three inputs have been read.

• There are a total of eight sequences that the machine can observe:

• 000, 001, 010, 011, 100, 101, 110, 111

• We will assume that state A is the initial state where no inputs have been fed into the machine.

• In states B and C, only one input has been fed into the machine and therefore we cannot output a 1.

Example : Another Sequence Detector

State Transition Diagram for the Sequence Detector

Design a machine thatoutputs a 1 when exactly two of the lastthree inputs are 1.

State Table and State Assignment for the Sequence Detector

Truth Table for the Sequence Detector

Creating the Circuit for the Sequence Detector

• There needs to be one flip-flop for each state variable, so a total of three are needed.

• Also, there are three next state functions and one output function, so four 8-to-1 multiplexers are needed.

Logic Diagram for the Sequence Detector

Circuit Minimization

Courtesy of UMBC, CMSC313, Richard Chang <chang@umbc.edu>

Sequence DetectorCourtesy of UMBC, CMSC313, Richard Chang <chang@umbc.edu>

Sequence DetectorCourtesy of UMBC, CMSC313, Richard Chang <chang@umbc.edu>

Sequence DetectorCourtesy of UMBC, CMSC313, Richard Chang <chang@umbc.edu>

Notes on K-map

• Also works for POS• Takes 2n time for formulas with n variables• Only optimizes two-level logic

• Reduces number of terms, then number of literals in each term• Assumes inverters are free• Does not consider minimizations across functions• Circuit minimization is generally a hard problem• Quine-McCluskey can be used with more variables• CAD tools are available if you are serious

Karnaugh Maps

• Implicant: rectangle with 1, 2, 4, 8, 16 ... 1’s• Prime Implicant: an implicant that cannot be extended into a larger

implicant• Essential Prime Implicant: the only prime implicant that covers

some 1• K-map Algorithm:

• 1. Find ALL the prime implicants. Be sure to check every 1 and to use don’t cares.

• 2. Include all essential prime implicants.• 3. Try all possibilities to find the minimum cover for the remaining 1’s.

Simplifying FSM’s

• State Reduction: equivalent FSM with fewer states• State Assignment: choose an assignment of bit patterns to states

(e.g., A is 010) that results in a smaller circuit• Choice of flip-flops: use D flip-flops, J-K flip-flops or T flip-flops? a

good choice could lead to simpler circuits.

State Reduction

• Description of state machine Mo to be reduced.

State Reduction in original transition diagram

State Reduction Algorithm

1. Use a 2-dimensional table — an entry for each pair of states.2. Two states are "distinguished" if:

1. States X and Y of a finite state machine M are distinguished if there exists an input r such that the output of M in state X reading input r is different from the output of M in state Y reading input r.

2. States X and Y of a finite state machine are distinguished if there exists an input r such that M in state X reading input r goes to state X', M in state Y reading input r goes to state Y‘ and we already know that X' and Y' are distinguished states.

3. For each pair (X,Y), check if X and Y are distinguished using thedefinition above.

4. At the end of the algorithm, states that are not found to be distinguished are in fact equivalent.

State Reduction Table

• An x entry indicates that the pair of states are known to be distinguished.

• A & B are equivalent, C & D are equivalent

State Reduction Example: reduced transition diagram

Homework for next week

• Apply state reduction on the exactly two of the last three inputs are 1 – sequence detector.

State Reduction Algorithm Performance

• As stated, the algorithm takes O(n4) time for a FSM with n states, because each pass takes O(n2) time and we make at most O(n2) passes.

• A more clever implementation takes O(n2) time.• The algorithm produces a FSM with the fewest number states

possible.• Performance and correctness can be proven.

Example : A Vending Machine Controller

• Design a vending machine controller using D-flip flops and a Programmable Logic Array (PLA).

• The vending machine accepts three types of inputs: a nickel (5¢), a dime (10¢), or a quarter (25¢).

• When the value of the total inserted coins equals or exceeds 20¢, the machine dispenses the merchandise, returns any excess change, and waits for the next transaction.

The Vending Machine Controller• For simplicity, we will assume that if the machine currently has 15¢

and the user inserts a quarter, the merchandise will be dispensed, 15¢ will be returned, and the machine will keep 5¢ and await for more money.

• This way, we can use 4 states to represent all possible states:A (00) = 0¢ C (10) = 10¢B (01) = 5¢ D (11) = 15¢

• We will need two bits each to uniquely encode all possible states as well as inputs.

State Transition Diagram for the Vending Machine

Input / Output2Output1Output0

Input = Nickel | Dime | QuarterOutput2 = 1|0 = Dispense / Do not dispense merchandiseOutput1 = 1|0 = Return / Do not return a nickel in changeOutput0= 1|0 = Return / Do not return a dime in change

State Table and State Assignment for the Vending Machine

Present State = snInput = xn

Output = zn

Truth Table for the Vending Machine

s1 s2 x1 x0 s1 s0 z2 z1 z00 0 0 0 0 0 1 0 0 0

1 0 0 0 1 1 0 0 0 0

2 0 0 1 0 0 0 1 1 0

3 0 0 1 1 d d d d d

4 0 1 0 0 1 0 0 0 0

5 0 1 0 1 1 1 0 0 0

6 0 1 1 0 0 0 1 0 1

7 0 1 1 1 d d d d d

8 1 0 0 0 1 1 0 0 0

9 1 0 0 1 0 0 1 0 0

10 1 0 1 0 0 0 1 0 0

11 1 0 1 1 0 0 1 1 1

12 1 1 0 0 d d d d d

13 1 1 0 1 0 0 1 1 0

14 1 1 1 0 1 1 1 1 1

15 1 1 1 1 d d d d d

For the FSM circuit, we will need:

• Two D flip-flops to represent the two state bits.

• PLA that takes four inputs (two for the present state bits and two for the coin bits) and has five outputs (two for the next state bits and three for the dispense and return bits).

Logic Design for the Vending Machine

Assumes the clock input is asserted only on an event such as the user inserting a coin into the machine.

5x5PLA

Q Ds0

Q Ds1

CLK

z2

z1

z0

x1

x0

State Encoding Problem

• State Encoding Can Have a Big Influence on Optimality of the FSM Implementation

• No methods other than checking all possible encodings are known to produce optimal circuit

• Feasible for small circuits only• Using Enumerated Types for States in VHDL Leaves Encoding

Problem for Synthesis Tool

Types of State Encodings (1)

• Binary (Sequential) – States Encoded as Consecutive Binary Numbers• Small number of used flip-flops• Potentially complex transition functions leading to slow implementations

• One-Hot – Only One Bit Is Active• Number of used flip-flops as big as number of states• Simple and fast transition functions• Preferable coding technique in FPGAs

Types of State Encodings (2)

State Binary Code One-Hot CodeS0 000 10000000S1 001 01000000S2 010 00100000S3 011 00010000S4 100 00001000S5 101 00000100S6 110 00000010S7 111 00000001

(ENTITY declaration not shown)

ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;ATTRIBUTE ENUM_ENCODING : STRING ;ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ;SIGNAL y_present, y_next : State_type ;

BEGIN

con’t ...

Figure 8.34

A user-defined attribute for manual state assignment

type fruit is (apple, orange, pear, mango); attribute enum_encoding : string; attribute enum_encoding of fruit : type is "11 01 10 00";

In this example, the enumeration literals are encoded as follows:

apple = "11" orange = "01" pear = "10" mango = "00"

Using constants for manual state assignmentARCHITECTURE Behavior OF simple IS

SUBTYPE ABC_STATE is STD_LOGIC_VECTOR(1 DOWNTO 0);

CONSTANT A : ABC_STATE := "00" ;CONSTANT B : ABC_STATE := "01" ;CONSTANT C : ABC_STATE := "11" ;

SIGNAL y_present, y_next : ABC_STATE;BEGIN

PROCESS ( w, y_present )BEGIN

CASE y_present ISWHEN A =>

IF w = '0' THEN y_next <= A ;ELSE y_next <= B ;END IF ;

… con’t

Control Unit Example: Arbiter (1)

Arbiter

reset

r1

r2

r3

g1

g2

g3

clock

An important form of arbiter is used in asynchronous circuits to select the order of access to a shared resource among asynchronous requests

Idle

000

1xx

Reset

gnt1 g 1 1 =

x1x

gnt2 g 2 1 =

xx1

gnt3 g 3 1 =

0xx 1xx

01x x0x

001 xx0

Control Unit Example: Arbiter (2)

Control Unit Example: Arbiter (3)

r 1 r 2

r 1 r 2 r 3

Idle

Reset

gnt1 g 1 1 =

gnt2 g 2 1 =

gnt3 g 3 1 =

r 1 r 1

r 1

r 2

r 3

r 2

r 3

r 1 r 2 r 3

r 1 r 2

r 1 r 2 r 3

Idle

Reset

gnt1 g 1 1 =

gnt2 g 2 1 =

gnt3 g 3 1 =

r 1 r 1

r 1

r 2

r 3

r 2

r 3

r 1 r 2 r 3

ASM Chart for Control Unit - Arbiter

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

Example : VHDL code Arbiter LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY arbiter ISPORT ( Clock, Resetn : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter ISTYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL y : State_type ;

Example : VHDL code Arbiter BEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THEN y <= Idle ;ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y ISWHEN Idle =>

IF r(1) = '1' THEN y <= gnt1 ;ELSIF r(2) = '1' THEN y <= gnt2 ;ELSIF r(3) = '1' THEN y <= gnt3 ;ELSE y <= Idle ;END IF ;

WHEN gnt1 =>IF r(1) = '1' THEN y <= gnt1 ;ELSE y <= Idle ;END IF ;

WHEN gnt2 =>IF r(2) = '1' THEN y <= gnt2 ;ELSE y <= Idle ;END IF ;

Example : VHDL code Arbiter

WHEN gnt3 =>

IF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

g(1) <= '1' WHEN y = gnt1 ELSE '0' ;

g(2) <= '1' WHEN y = gnt2 ELSE '0' ;

g(3) <= '1' WHEN y = gnt3 ELSE '0' ;

END Behavior ;

ASM Chart for Control Unit - Example 4

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

r 1

r 3 0 1

1

Idle

Reset

r 2

r 1

r 3

r 2

gnt1

gnt2

gnt3

1

1

1

0

0

0

g 1

g 2

g 3

0

0

1

VHDL code of arbiter – Style 1 (1)LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY arbiter ISPORT ( Clk, Reset : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter ISTYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL y : State_type ;

VHDL code of arbiter – Style 1 (2)

BEGINPROCESS ( Reset, Clk )

BEGINIF Reset = '1' THEN y <= Idle ;ELSIF rising_edge(Clk) THEN

CASE y ISWHEN Idle =>

IF r(1) = '1' THEN y <= gnt1 ;ELSIF r(2) = '1' THEN y <= gnt2 ;ELSIF r(3) = '1' THEN y <= gnt3 ;ELSE y <= Idle ;END IF ;

WHEN gnt1 =>IF r(1) = '0' THEN y <= Idle ;ELSE y <= gnt1 ;END IF ;

WHEN gnt2 =>IF r(2) = '0' THEN y <= Idle ;ELSE y <= gnt2 ;END IF ;

WHEN gnt3 =>IF r(3) = '0' THEN y <= Idle ;ELSE y <= gnt3 ;

END IF ;END CASE ;

END IF ;END PROCESS ;

g(1) <= '1' WHEN y = gnt1 ELSE '0' ;g(2) <= '1' WHEN y = gnt2 ELSE '0' ;g(3) <= '1' WHEN y = gnt3 ELSE '0' ;

END Behavior ;

VHDL code of arbiter – Style 1 (3)

VHDL code of arbiter – Style 2 (1)LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY arbiter ISPORT ( Clk, Reset : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter ISTYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;SIGNAL y, y_next : State_type ;

VHDL code of arbiter – Style 2 (2)BEGIN

PROCESS ( Reset, Clk )BEGIN

IF Reset = '1' THEN y <= Idle ;

ELSIF rising_edge(Clk) THENy <= y_next;

END IF;END PROCESS;

VHDL code of arbiter – Style 2 (3)PROCESS ( y, r )BEGIN

y_next <= y;g <= "000";CASE y IS

WHEN Idle =>IF r(1) = '1' THEN y_next <= gnt1 ;ELSIF r(2) = '1' THEN y_next <= gnt2 ;ELSIF r(3) = '1' THEN y_next <= gnt3 ;ELSE y_next <= Idle ;END IF ;

WHEN gnt1 =>g(1) <= '1' ;IF r(1) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt1 ;END IF ;

WHEN gnt2 =>g(2) <= '1' ;IF r(2) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt2 ;END IF ;

WHEN gnt3 =>g(2) <= '1' ;IF r(3) = '0' THEN y_next <= Idle ;ELSE y_next <= gnt3 ;END IF ;

END CASE ;END PROCESS ;

END Behavior ;

VHDL code of arbiter – Style 2 (4)