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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 11
ELEC 5270/6270 Spring 2009ELEC 5270/6270 Spring 2009Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Power Analysis: High-LevelPower Analysis: High-Level
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 22
Key ParametersKey Parameters
CapacitanceCapacitanceAreaAreaComplexityComplexity
ActivityActivityDynamic behaviorDynamic behaviorOperational characteristicsOperational characteristics
Power α Capacitance × Activity
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 33
Architecture-Level Power EstimationArchitecture-Level Power Estimation
Analytical methodsAnalytical methodsComplexity-based modelsComplexity-based modelsActivity-based modelsActivity-based models
Empirical methodsEmpirical methodsFixed-activity modelsFixed-activity modelsActivity-sensitive modelsActivity-sensitive models
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 44
A Complexity-Based ModelA Complexity-Based Model
wherewhere GEGEkk = = gate equivalent count for block k, e.g., gate equivalent count for block k, e.g.,
estimated estimated number of 2-input NANDs.number of 2-input NANDs. EEtyptyp = = average energy consumed per clock cycle by average energy consumed per clock cycle by
an an active typical 2-input NAND.active typical 2-input NAND. CCLk Lk == average capacitance of a gate in block k.average capacitance of a gate in block k. f f = = clock freqency.clock freqency. VVDDDD = = supply voltage.supply voltage. AAkk = = average fraction of gates switching per cycle in average fraction of gates switching per cycle in
block k.block k.
Power = Σ GEk (Etyp + CLkVDD2) f Ak
All functional blocks k
Ref.: K. Müller-Glaser, K. Kirsch and K. Neusinger, “Estimating EssentialDesign Characteristics to Support Project Planning for ASIC DesignManagement,” Proc. IEEE Int. Conf. CAD, Nov. 1991, pp. 148-151.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 55
Improving Complexity ModelsImproving Complexity Models
Treat logic, memory, interconnects and Treat logic, memory, interconnects and clock tree, separately.clock tree, separately.
For example, a memory array may not be For example, a memory array may not be modeled as equivalent NAND gates, but modeled as equivalent NAND gates, but as memory cells.as memory cells.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 66
Memory array
An On-Chip SRAMAn On-Chip SRAM
Sense and column decode
Ro
w d
eco
de a
nd
dri
vers
Ctrl
Ad
dre
ss b
us
. . .
. . .
. . .
. . .
Address bus
word line
bit
line
Six-transistor memory cell
2k cells
2n-k c
ells
Data
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 77
Power Consumed by SRAMPower Consumed by SRAM
2k
Power = ── (cint lcol + 2n-k ctr) VDD Vswing f 2
Where 2k number of cells in a rowcint wire capacitance per unit lengthlcol memory column length2n-k number of cells in a columnctr minimum size transistor drain capacitanceVswing bitline voltage swing
Ref.: D. Liu and C. Svenson, “Power Consumption Estimation inCMOS VLSI Chips,” IEEE J. Solid-State Circuits, June 1991,pp. 663-670.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 88
Activity-Based ModelsActivity-Based Models PowerPower αα capacitance × activitycapacitance × activity CapacitanceCapacitance αα area area Both area and activity can be estimated from the Both area and activity can be estimated from the
entropy of a Boolean function.entropy of a Boolean function. Definition: Entropy of a system with m states having Definition: Entropy of a system with m states having
probabilities p1, p2, . . . , pm, isprobabilities p1, p2, . . . , pm, is
mm
HH = – = – ΣΣ pk logpk log22 pk pk bitsbits
k=1k=1
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 99
Binary SignalsBinary Signals Entropy of a binary signal:Entropy of a binary signal:
H(p1) = – p1 logH(p1) = – p1 log22 p1 – (1– p1) log p1 – (1– p1) log22(1– p1)(1– p1)
Entropy of an n-bit binary vector:Entropy of an n-bit binary vector:nn
H(X)H(X) == ΣΣ H(p1k)H(p1k) k=1k=1
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1010
Entropy and ActivityEntropy and Activity
p1k
0.0 0.25 0.5 0.75 1.0
1.0
0.75
0.50
0.25
0.0
En
tro
py
4 p1k(1-p1k)
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1111
Entropy of a CircuitEntropy of a Circuit
CombinationalLogic
.
.
.
X1
X2
Xn
.
.
.
Y1
Y2
Ym
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1212
Input and Output EntropyInput and Output Entropy
2n
Hi = – Σ pk log2 pk k=1
where pk = probability of kth input vector
2m
Ho = – Σ pj log2 pjj=1
where pj = probability of jth output vector
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1313
Average AcrivityAverage Acrivity
Hi
Ho
Circuit depth →PI PO
2/3Average entropy ≈ ─── (Hi + 2Ho)
n+m
Quadratic decay
Hi ≥ Ho
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1414
Area EstimateArea Estimate K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the K.-T. Cheng and V. D. Agrawal, “An Entropy Measure for the
Complexity of Multi-Output Boolean Functions,” Complexity of Multi-Output Boolean Functions,” Proc. 17Proc. 17thth DAC DAC, , 1990, pp. 302-305.1990, pp. 302-305.
M. Nemani and F. Najm, “Towards a High-Level Power Estimation M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capability,” Capability,” IEEE Trans. CADIEEE Trans. CAD, vol. 15, no. 6, pp. 588-598, June , vol. 15, no. 6, pp. 588-598, June 1996.1996.
Area = 2n Ho/n for large n
= 2n Ho for n ≤ 10
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1515
PowerPower
NPower = K1 × Av. Activity × Σ Ck = K2 × Av. Activity × Area
k=1
where Ck is the capacitance of kth node in a circuit with N nodes
2n+1
Power = K3 ────── Ho (Hi + 2Ho) 3n(n+m)
Constant K3 is determined by simulation of gate-level circuits.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1616
Sequential CircuitSequential Circuit
CombinationalLogic
Flip-flops
PI PO
Hi Ho
Hi and Ho are determined from high-level simulation.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1717
Empirical MethodsEmpirical Methods
Functional blocks are characterized for Functional blocks are characterized for power consumption in active and inactive power consumption in active and inactive (standby) modes by(standby) modes byAnalytical methods, orAnalytical methods, orSimulation, orSimulation, orMeasurementMeasurement
A software simulator determines which A software simulator determines which blocks become active and adds their blocks become active and adds their power consumption.power consumption.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1818
Example: RISC MicroprocessorExample: RISC Microprocessor
IF ID EX MEM WB
IF ID EX MEM WB
add R1← R2+R3
lw R4 ← 4(R5)
Clock cycles 1 2 3 4 5 6 . . .
mem rfile ALU rfile pcadd bradd
mem rfile ALU mem rfilepcadd bradd
mem
ALU
rfile
mem
ALU
ALUALU ALU rfile rfile
ALUrfile
mem
time
Powerprofile
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 7ELEC6270 Spring 09, Lecture 7 1919
Additional ReferencesAdditional References
P. E. Landman, “A Survey of High-Level Power P. E. Landman, “A Survey of High-Level Power Estimation Techniques,” in Estimation Techniques,” in Low-Power CMOS Low-Power CMOS DesignDesign, A. Chandrakasan and R. Brodersen , A. Chandrakasan and R. Brodersen (Editors), New York: IEEE Press, 1998.(Editors), New York: IEEE Press, 1998.
P. E. Landman and J. M. Rabaey, “Activity-P. E. Landman and J. M. Rabaey, “Activity-Sensitive Architectural Power Analysis,” Sensitive Architectural Power Analysis,” IEEE IEEE Trans. CADTrans. CAD, vol. 15, no. 6, pp. 571-587, June , vol. 15, no. 6, pp. 571-587, June 1996.1996.
A. Raghunathan, N. K. Jha, and S. Dey, A. Raghunathan, N. K. Jha, and S. Dey, High-High-level power analysis and optimizationlevel power analysis and optimization, Boston: , Boston: Springer, 1997.Springer, 1997.