Electric Power Systems Research 143 (2017) 703–714
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Electric Power Systems Research
j o ur na l ho mepage: www.elsev ier .com/ locate /epsr
new bidirectional hybrid multilevel inverter with 49-level outputoltage using a single dc voltage source and reduced number of onomponents
.J. Mesquita ∗, F.L.M. Antunes, S. Daherederal University of Ceara, Brazil
r t i c l e i n f o
rticle history:eceived 16 May 2016eceived in revised form 7 October 2016ccepted 14 October 2016vailable online 4 November 2016
a b s t r a c t
This paper proposes an isolated bidirectional asymmetrical multilevel inverter topology composed by anH-bridge (HB) inverter connected to the primary side of transformer. The transformer secondary side iscomposed by two windings, and each one is connected to a new cell introduced in this work. The proposednew cell is based on the conventional HB inverter, where two bidirectional switches are added to eachHB leg, thus resulting in the structure referred to as CHB-2bs. The transformer can also be composed by
multiple secondary winding in order to provide the necessary voltages to supply as many as CHB-2bscells are. A 600 W laboratory prototype with dc input voltage of 48 V and an ac output voltage of 220 V,60 Hz using a grain-oriented silicon–steel toroidal transformer operating at 300 Hz is implemented tovalidate the theoretical assumptions and the advantages addressed to the CHB-2bs cell.
tage ca–caultiple winding transformer
. Introduction
Different strategies for the integration of energy sources areecoming increasingly present nowadays, where the inclusion ofenewable energy is supposed to modify the dynamic behavior ofraditional one way energy flow power systems [1–6]. The everncreasing electricity generation at the consumer side and thedvent of microgrids made the bidirectional power flow to play anmportant role [7,8]. Within this context bidirectional power con-erters are quite important when interconnecting storage systems,olid-state transformers (SSTs), microgrids and electric vehicleso the power grid [9–15]. All of the aforementioned fields corre-pond to potential applications of multilevel inverter topologies.rrangements called asymmetrical or hybrid inverters have beenresenting significant interest in generating more levels in the out-ut voltage with fewer components [16,17].
Currently asymmetrical multilevel inverters are frequentlypplied in FACTS (flexible ac transmission systems) devices [18],specially for STATCOMs (Synchronous Static Compensators), elec-
ric machines drives, and renewable energy systems. Moreover,hen the inverter is applied to machine drives, torque ripples are
reatly reduced when compared to other topologies [19].
The main disadvantage of asymmetrical topologies comparedto other aforementioned approaches lies on the required numberof additional isolated voltage sources. However, it is drasticallyreduced when compared to symmetrical cascade topologies toprovide an output voltage with the same number of levels. Solu-tions using a single dc voltage source have been successfullyimplemented with low-frequency inverters and multi-windingtransformers. Besides, research for new materials and magneticcores has shown that it is possible to process tens of kilowattswith efficiencies higher than 99.4% [20], which brings prominentadvantages for the implementation of such topologies. Withinthis context, this paper proposes a new multilevel asymmetri-cal inverter topology based on the HB cell with two bidirectionalswitches, resulting in a base module called CHB-2bs. Several asym-metrical configurations for the proposed topology are presented,while using a suitable input voltage for the two cascaded CHB-2bscells can provide an output voltage waveform with up to 49 levels.
A prototype with dc input voltage of 48 V and an ac out-put voltage of 220 V using a grain-oriented silicon–steel toroidaltransformer operating at 300 Hz is implemented to validate the the-oretical assumptions. It can be stated that the proposed approachincreases the converter efficiency, also maintaining low total har-monic distortion of the output voltage and reducing the total
number of on components when compared with the conventionalmultilevel converter using an ac–ac stage to produce the samenumber of levels of the output voltage waveform. The theoreti-cal analysis is carried out and experimental results are discussed to
704 S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714
ne qu
ervaio
2
bmhtinaaattibtt
elhiiwadtmmfeunt
m
i
Fig. 1. N-level output voltage waveform during o
valuate the proposed converter with ac–ac stage, which does notequire the use of an additional diode bridge. A study for the con-erter operating with n levels for the output voltage is presented,s well as relevant mathematical expressions. Finally, importantssues are discussed and eventual comparison is performed withther asymmetrical topologies.
. Features and performance of multilevel inverters
Multilevel inverters are characterized by the improved distri-ution of the voltages stresses across the semiconductors, thusaking them suitable for a wide range of applications that involve
igh power and medium voltage levels [9]. In the early days of thisechnology [21], this aspect had direct impact on the output voltagen terms of a multilevel waveform, as shown in Fig. 1(a). However,owadays there are multilevel inverters where the voltage stressescross the semiconductors are not equally shared, although theyre able to generate the same multilevel waveform Vo with thedvantage of reducing the number of required components. Suchopologies are widely known in literature as hybrid inverters dueo the use of semiconductor devices with distinct technologies e.g.,ntegrated gate commutated thyristors (IGCTs) and insulated gateipolar transistors (IGBTs), also called asymmetrical inverters dueo employing dc voltage sources with distinct magnitudes to supplyhe cascaded cells [15,22–25].
The output voltage waveform in a multilevel inverter with n lev-ls can be generated with fixed levels as in Fig. 1(a) or modulatedevels as in Fig. 1(b). The operation with fixed levels is adequate forigh power applications where each angle �N can be used to elim-
nate harmonics. Fig. 1(b) shows that the inverter output voltages expressed by modulated levels, resulting from the use of pulse
idth modulation (PWM) strategies such as phase disposition (PD),lternative phase opposite disposition (APOD), phase oppositionisposition (POD), phase shift (PS), hybrid modulation, space vec-or modulation (SVM), among others [9,26,27]. Usually one of the
ain advantages addressed to PWM is the concentration of the har-onic amplitudes around the switching frequency, which are far
rom the fundamental component, thus making harmonic filteringasier in terms of smaller filter elements when compared to thosesed in inverters operating with the same number of fixed levels. However when operating levels with many fixed voltage levels,he harmonic content of the output voltage is drastically affected.
The inverter topology studied in this work employs staircaseodulation, which produces an output voltage as shown in Fig. 1(a).The output voltage vo(ωt) presented in Fig. 1(a) can be expressed
n terms of the Fourier series given by:
vo(ωt) = a0 +∞∑
(ak cos kwt + bk sin kwt)
2
k=1
=∞∑
k=−∞(Cke−jkωt)
(1)
arter cycle: (a) fixed levels; (b) modulated levels.
where a0, ak, and bk are the Fourier series coefficients, and Ck is themagnitude of the k-th harmonic.
Ck = 12�
�∫−�
vo(ωt)e−jkωtdωt
= 12�
N∑i=1
⎡⎢⎣
−�i∫−(�−�i)
− Vdce−jkωtdωt +�−�i∫
�i
Vdce−jkωtdωt
⎤⎥⎦
= Vdc
2�k
N∑i=1
j[−(
ejk�i + e−jk�i)
+(
ejk(�−�i) + e−jk(�−�i))]
= Vdc
2�k
N∑i=1
j[cos(k(� − �i)) − cos(k�i)
]
(2)
where Vdc is the dc input voltage.Since voltage vo(ωt) has central symmetry, the dc component
(term a0) and even harmonics are null. Thus the output voltageexpressed in terms of the Fourier series becomes:
vo(t) =N∑
i=1
∞∑k=1
2Vdc
k�
[cos(k�i) − cos
(k(� − �i)
)]sin(kωt) (3)
The fundamental component of the output voltage Vof 1 employ-ing staircase modulation in Fig. 1(a) is:
Vof 1 = 4Vdc
�
N∑i=1
cos(�i) (4)
The (2l − 1)-th harmonic components of the output voltage aregiven by:
Voh(2l−1) = 4Vdc
(2l − 1)�
N∑i=1
cos[(2l − 1)�i
]for l = 2, 3, 4, ....
(5)
In order to check the quality of the resulting waveform, thetotal harmonic distortion (THD) index given by Eq. (6) can be used.According to standard IEEE Std 519, the THD of the resulting outputvoltage must be lower than 5%.
THD =
√∑∞l=2
[4Vdc2l−1
∑Ni=1 cos (2l − 1) �i
]4Vdc
�
∑Ni=1 cos
(�i
) (6)
From Eq. (4), the modulation index mi can be obtained to deter-mine the output voltage amplitude considering a given number of
levels N during one quarter cycle i.e.:
mi = Vof 1�
4NVdc(7)
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S.J. Mesquita et al. / Electric Power
Expressions Eqs. (4) and (5) can be used to determine �i andliminate dominant harmonics, always resulting in a system with
available transcendental equations, wherein the first equations used to find the fundamental component as in Eq. (8). Isolatinghe cosine terms and assuming that the harmonic amplitudes arequal to zero i.e., Vh(2l−1) = 0, the N − 1 harmonic components cane eliminated:
*where l = 2, l = 3p − 1, p = 1, 2, 3. . ., as this expression is only validor single-phase inverters considering the phase voltage. The thirdarmonic Vh(3) and its respective even multiples do not exist in the
ine voltage and thus l /= 3p − 1 in Eqs. (5), (6), and (8) when appliedo the line voltage.
The line voltage in three-phase systems is√
3 times higherhan the phase voltage and can be considered as a sum given by
o(t) + vd(t), where vd(t) corresponds to vo(t) lagged by 1
3f 1 .Several approaches can be used for the solution of Eq. (8) e.g.,
esultant theory, Newton–Raphson, genetic algorithms, computa-ional tools, among others based on numerical methods [28–31].
Fig. 2. Proposed topology with an
ms Research 143 (2017) 703–714 705
3. Proposed topology
The topology proposed in this work is shown in Fig. 2, being com-posed by a dc voltage source Vin responsible for supplying the inputbus of the HB cell, which in turn imposes an ac voltage to the pri-mary side of the multi-winding transformer operating at mediumfrequency. It is worth to mention that the transformer provides thedesired voltage across each CHB-2bs cell.
Generic aspects of the aforementioned topology are describedin Section 4.
3.1. Prominent advantages and applications of the proposedtopology
The main advantage addressed to the topology when comparedwith other multilevel cascaded inverters lies on the drastic reduc-tion in the number of required dc voltage sources. It needs a singleone only as seen in Fig. 2.
Other features such as insulation, possibility to associate theoutput side in series with other inverters to generate a larger buswithout short-circuit issues, operation at reduced frequency dueto the use of staircase modulation, absence of electromagneticshielding to eliminate conducted and radiated electromagneticinterference (EMI), as well as the absence of output filter elements(or use of small-sized ones) are some prominent advantages of theconverter.
Another interesting aspect of this approach lies in increasedrobustness due to the absence of electrolytic capacitors in the cells,since such components typically present short useful life, and alsothe absence of complex techniques to balance the voltages acrossthem. It is also possible to mention that the semiconductors presentthermal relief due to existence of minimized stresses and operation
with reduced frequency.
Considering the aforementioned aspects, it can be stated that thepotential applications of the topology include standalone systemsusing PV modules as a primary source. Besides, it can be applied
intermediate ac–ac stage.
706 S.J. Mesquita et al. / Electric Power Syste
F(W
tab
4
ss
eOsct
oSFn
bhct
4
tvF
gmS
ig. 3. Generic configuration of the proposed structure with cascaded CHB-2bs cells.a) Operation with dc voltage sources and (b) operation with ac voltage sources.
here: Vpo is the peak value of output voltage with n levels.
o microgrids as an interface with renewable energy sources, ors a link between the dc bus and ac systems due to the inherentidirectional characteristic.
. General characteristics of the topology
The cascaded CHB-2bs cells must operate with bidirectionalwitches for the adequate operation of the proposed topology ashown in Fig. 2.
The adopted configuration for the bidirectional switches Sxyzmploys two antiseries-connected n-channel MOSFETs (Metalxide Semiconductor Field Effect Transistors) (with common
ource connection), which is responsible for ensuring the path forurrent io according to the switching logic, with consequent reduc-ion of power losses if compared with the use of low-voltage IGBTs.
The independent drive of the bidirectional switches Sxyz (Sxyar Sxyb) results in a modular topology, also allowing both switchesxya and Sxyb to be turned on simultaneously instead of one MOS-ET and one diode of a switch Sxyz during a given state with level.
The simultaneous turn on of one switch and one diode in a givenidirectional switch Sxyz is avoided in this work, since it impliesigher losses. This configuration is also adopted during the intervalsorresponding to level transitions, while minimizing the diode on-ime.
.1. General operation modes of the topology
The association of voltage sources Vsx,j (where j correspondso the position of the source in cell x i.e., j = 1 or j = 2) must pro-ide equally-spaced levels with the same magnitude according toig. 1(a) so that the THD of the output voltage is not affected.
The restrictions imposed to the commutation when doubleating signals are applied to Sxyz must comply with the comple-entarity conditions of the HB cell, as well as switches Sx5z and
x6z must obey the restrictions imposed by Eq. (9).
Sx5z ↔ Sx1z , Sx2z
and
Sx6z ↔ Sx3z , Sx4z
(9)
ms Research 143 (2017) 703–714
where x = 1, 2, . . . corresponds to the first, second, . . . x − nth cell,respectively, and z = {a,b}.
Then, observing a given CHB-2bs cell in the proposed topologyin Fig. 2 and also the simplified circuit in Fig. 3, it is possible tochoose cases 1 and 2 using only positive values for Vsx,j consider-ing Vsx ,2 = 2Vsx ,1. Seven different ideal levels result in the outputvoltage Vohx when using double gating signals for Sxyz, consideringonly term Sxy i.e.,
Vohx =
⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩
0 → Sx1 and Sx3, Sx2 and Sx4 or
Sx5 and Sx6,
Vsx,1 → Sx1 and Sx6,
−Vsx,1 → Sx3 and Sx5,
2Vsx,1 → Sx5 and Sx4,
−2Vsx,1 → Sx2 and Sx6,
3Vsx,1 → Sx1 and Sx4,
−3Vsx,1 → Sx2 and Sx3.
(10)
During the transition between adjacent states as shown in Eq.(10), it is not possible to change the switches commutation accord-ing to the aforementioned configuration, since overvoltage acrossswitches Sxyz may occur when supplying inductive loads, for exam-ple.
An alternative to avoid voltage spikes during the level transitionhas been implemented in Ref. [14], based on the application of apassive snubber to each switch Sxyz. However, it implies increasedcost and the component count.
Due to the adopted switching configuration, an additional snub-ber is not used to ensure the current flow during the level transition.The configuration corresponding to turning on one switch and onediode in Sxyz is only used during the level transition period ast ≤ 1 �s, so that safe operation of the power converter is ensuredwhen inductive loads are supplied. This technique enables currentio to flow, thus avoiding damaging voltage spikes across switchesSxyz due to L di
dt effect. It is also worth to mention that the adopteddriving strategy always allows one switch of Sxyz (Sxya or Sxyb)to remain on due to the polarity of the voltage across the primarywinding Vpr.
Distinct combinations of switches Sxya and Sxyb and theirrespective diodes and the current direction i.e., io > 0 or io < 0 in theCHB-2bs cell represented by x can be verified in order to maintainthe current flowing during a level transition.
This work uses only one intermediate state during the leveltransition, while the simultaneous turn on of two MOSFETs in abidirectional switch Sxyz is maintained for a state with level n, thusresulting in reduced losses. Other strategies for the generation ofn levels can be achieved by turning on one switch and one diodeof the adjacent switch in Sxyz (Sxya and Sxyb) analogously to theimplementation given in Ref. [32], even though higher losses resultsince the diodes are forward biased.
The weight of a voltage source �x,j in position j is �x,j = Vsx,j/Vs1,1for a given cell, as x is related to the weight of cell Px, i.e.,Px = Vsx/Vs1,1, where Vsx is the bus voltage across cell x i.e.,Vsx = Vsx ,1 + Vsx ,2.
The association of cascaded cells can generate differentcombinations when varying parameter �x,j , resulting in moreequally-spaced levels in the output voltage, also using the samenumber of components.
Systems Research 143 (2017) 703–714 707
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S.J. Mesquita et al. / Electric Power
This can be accomplished by a specific relationship among dis-inct weights Px (normalized as function of Vs1,1, Pnorx) and relatedy an integer multiplicative factor as in Eq. (11).
Pnorx = {x ∈ N∗ :
(Vs1
Vs1,1
),
(Vs2
Vs1,1
),
(Vs3
Vs1,1
)...(
Vsx−2
Vs1,1
),
(Vsx−1
Vs1,1
),
(Vsx
Vs1,1
)},
with Px ⊂ Pnorx, and
Px ≤ 3 + 6n=x−1∑m=1
Vsm
Vs1,1, x ≥ 2;
(11)
Distinct weighting ratios Px defined according to expressionquation reference goes here Eq. (11) can be found in Table 1 fromhe sum (�x,j=1+�x,j=2). Parameter �x,j defines how Vsx,j increases inhe proposed topology with x cells.
According to the modes represented in Table 1, it is possible tobtain n different levels for the inverter output voltage from �x,j .
Other configurations proposed in this work that allow the betteristribution of voltage stresses across the switches are defined asollows (Vs1,1,Vs1,2; Vs2,1,Vs2,2): (1) 31 levels—Vs1,1, 5Vs1,1; 3Vs1,1,Vs1,1; (2) 35 levels—Vs1,1, 9Vs1,1; 5Vs1,1, 7Vs1,1; (3) 39 levels—Vs1,1,Vs1,1; 8Vs1,1, 10Vs1,1; (4) 33 levels—Vs1,1, 10Vs1,1; 8Vs1,1, 5Vs1,1; (5)3 levels—Vs1,1, 8Vs1,1; 4Vs1,1, 11Vs1,1. As it was mentioned before,hey are able to produce a maximum number of equally-spacedevels for the output voltage by using only two cells, thus makinghe converter prominent for high-voltage applications.
Table 2 shows a comparison among the operation modes pre-ented in Table 1 and the conventional topologies.
Among the modes presented in Tables 1 and 2, a configurationefined as (1:2:7:14) was chosen for the implementation of theopology shown in Fig. 2, since it uses reduced component numbero provide the desired number of levels.
Fig. 3 presents the generic form of the circuit depicted in Fig. 2or the inverter operating with x CHB-2bs cells.
This representation shows that the inverter is able to operateith two possible configurations for Vsx,j . Case 1 includes the pos-
ibility of using independent dc voltage sources, where the x-thHB-2bs cell is supplied by a dc voltage Vsx,j whose magnitude isx,j .Vs1,1. In case 2, it is possible to use Vsx,j as an ac voltage source,hich can be obtained by using a transformer arranged according
o Fig. 2. The maximum value of Vsx,j in this arrangement dependsn parameter �x,j , the number of levels n, and the peak value ofhe desired sinusoidal output voltage Vpo. The inverter operation
able 1roposed topology—configurations versus parameter �x,j .
Mode Configuration �x,j
I 1:2:4:8:16:32. . . 22(x−1)+(j−1)
II 1:2:7:14:28:56. . . 22(x−1)+(j−1) · 7, x ≥ 2III 1:2:7:14:49:98. . . 2(j−1) · 7(x−1)
able 2symmetrical topologies versus number of levels.
Comparison among asymmetrical topologies
Cells Config. 1 2 3 x
Number oflevels
CHB Binary 3 7 15 2x+1 − 1Ternary 3 9 27 3x
CHB-2bs Mode I 7 31 63 22x − 1Mode II 7 49 217 7 · (22x−1 − 1)Mode III 7 49 343 7x
Fig. 4. Waveform representing the voltage across the primary winding Vpr and itsrespective magnetic flux ˚.
in case 2 is analyzed in this work, whose advantages have beenpreviously mentioned.
According to the topology proposed in Figs. 2 and 3 and consid-ering that double gating signals are applied to switch Sxyz followingthe restrictions imposed by Eq. (9), while omitting the term z in thenomenclature due to the simultaneous drive, Sx2 can be defined asa NOR function of Sx1 and Sx5, as switch Sx4 becomes a NOR func-tion of Sx3 and Sx6. Besides, Sxy = 1 and Sxy = 0 correspond to stateswhen the switch is on and off, respectively.
Thus, the output voltage expressed in terms of a switching func-tion for the multilevel inverter operating in case 1 as shown inFig. 3(a) is given by:
Vo = Vs1,1 ·x∑
x=1
[(�x,j=1 + �x,j=2)(Sx1 − Sx3) + �x,j=2(Sx5 − Sx6)
](12)
According to Eq. (12), the output voltage can be controlleddepending only on four switches per CHB-2bs cell. The switchingfrequencies for the chosen configuration (1:2:7:14) of the inverterrepresented in Fig. 3 operating in case 1 and employing dc voltagesources with staircase modulation are defined by:
Fsx1 and sx3 = (22(xt−xd)+3 − 5)f1
Fsx5 and sx6 = (22(xt−xd)+3 − 4)f1
Fsx2 and sx4 = (22(xt−xd)+2 − 3)f1
(13)
where xt is the total amount of series-connected CHB-2bs cells andxd corresponds to the position of the desired cell.
The expressions in Eq. (13) are the referential basis for the com-parison of switching frequencies in the inverter implemented withac voltage sources i.e., case 2 in Fig. 3, which will be discussed inthe next section.
Session 5 is concerned with evaluating how the increase of thetransformer operating frequency is supposed to affect the switch-ing frequencies in the inverter presented in Fig. 2.
5. Operation of the multilevel inverter with ac–ac stage
5.1. Transformer
Based on Fig. 2, it is possible to notice that the voltage acrossthe primary winding with Npr turns can be expressed as a switch-ing function given by Vpri = Vin(Si1–Si3). This voltage appearsacross the secondary windings with Nsx,j turns as defined byVsx,j = (Nsx,j/Npr).[Vin(Si1–Si3)].
The waveform in Fig. 4 represents the practical implementa-tion of the proposed multilevel inverter, while voltage Vpr can bemeasured across the primary winding.
7 Systems Research 143 (2017) 703–714
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os
08 S.J. Mesquita et al. / Electric Power
According to Fig. 4, the relationship between the magnetic fluxeasured in maxwell with the waveform of the voltage across the
rimary winding Vpr is defined in Eqs. (14) and (15).
Vpr(t) = Nprd�
dt· 10−8(V)⎧⎪⎨
⎪⎩Vprmax = Npr
�max
(1/4)Ttr· 10−8 (V), if
TL
2≤ t ≤ Ttr − TL
2.
−Vprmax = Ntr�max
(1/4)Ttr· 10−8(V), if
Ttr + TL
2≤ t ≤ 2Ttr − TL
2.
(14)
Vprrms =
√√√√√∫ Ttr − TL
2TL
2
Vprmax2dt +
∫ 2Ttr − TL
2TL + Ttr
2
(−Vprmax)2dt
= Vprmax
√1 − 2TL
Ttr= Npr
�max
(1/4)T
√1 − 2TL
Ttr· 10−8
= 4 · Npr · ftr · Bmax · Aef .
√1 − 2TL
Ttr· 10−8
(15)
From expression (15), it is possible to obtain the number ofurns of the primary winding as in Eq. (16), where Aef is the coreffective cross section area measured in cm2 and ftr is the trans-ormer operating frequency. Besides, converting gauss to tesla inmax gives:
pr = Vprrms · 104
4 · Npr · ftr · Bmax · Aef .
√1 − 2TL
Ttr
(16)
If the number of primary turns Npr, the peak-to-peak value of theesired sinusoidal waveform defined as Vpo, and the input voltagein are known, the number of secondary turns can be obtained as:
sx,j = 2j · 7x−1 · Vpo · Npr
(n − 1)Vin(17)
In order to implement the proposed topology, a grain-orientedilicon–steel toroidal core has been employed in the transformeronsidering the following parameters: flux density Bmax = 0.68 T,perating frequency ftr = 300 Hz, and Aef = 7.75 cm2, with dimen-ions 102 mm × 134 mm × 51 mm (inside diameter—ID × outsideiameter—OD × height—H), sheets of 0.27 mm, and stacking factorf 0.95.
.2. Operation of the proposed asymmetrical inverter
The converter output voltage Vo corresponds to the combina-ion of voltages across the secondary windings Vsx,j defined by awitching function expressed as:
According to Eq. (18), a particular switching configuration isecessary to obtain either positive or negative values of the out-ut voltage for each one of the states for voltage Vpr (positive oregative), thus resulting in a desired level n. In general, the fol-
owing equality must be maintained: Sign(p).Sign(q) = Sign(Vo). If
ign(p) = 0, q remains the same.
Therefore, if a hypothetical example of the proposed inverterperating with 25-level output voltage is chosen, the switchingtates defined in Fig. 5 are valid.
Fig. 5. Composition of the output voltage waveform based on the primary voltageVpr for the inverter employing an ac–ac stage and configuration (1:2:7:14).
If the voltage across the HB is positive i.e., Vpr > 0 and thedesired voltage is also positive i.e., Vo > 0 to generate level +n asin Eq. (18), then p > 0 and q > 0. If the voltage across HB becomesnegative for Vo > 0, then p < 0 and q < 0 so that the symmetri-cal state +n is obtained, thus keeping Vo unchanged. This case isshown in Fig. 5 when the switching states change from 12 V1,1 to11 V1,1.
Fig. 5 presents the output voltage waveform and its compositionas influenced by the primary voltage and the inverter switchingstates. Discontinuities can be seen in voltage Vo, which result fromthe zero-crossing interval of the HB. However, they can be promptlyeliminated by using an output filter.
Fig. 5 also shows the switching states (Sxy = 1 → Sxya is on andSxyb is on) necessary for the generation of levels. The state definedas Sxy = 0 corresponds to turning on a given switch depending onthe polarity of Vpr and turning off another switch that is part of thecorresponding pair Sxya or Sxyb.
This work has considered the optimum case for the level transi-tion, where one state avoids eventual short-circuit through voltagesources Vsx ,1 and Vsx ,2.
Table 3 presents the transition states regarding one eighth of theoutput voltage cycle, which comprehends seven distinct states forthe fundamental component Voh1. Besides, R and S represent the(R/S) states valid for Vpr > 0 and Vpr < 0, respectively.
In order to check the switching frequency of the independentswitches (Sxya or Sxyb) that are part of the bidirectional switch,Table 4 was obtained for different values for the operating fre-quency of the transformer represented by ftr .
It can be seen that the switches in the cell that processes the low-est amount of power (S1yz) operate with higher frequency, whilethe cell that processes the highest amount of power (S2yz) presentlower switching frequency, which contributes drastically to thereduction of switching losses.
The first row containing the ratio between the switching fre-quency and the fundamental frequency (Fsxy/f1) represents animportant benchmark since it refers to the implementation of theinverter using dc voltage sources (No ftr).
This prominent behavior shows that the switches in the firstcell are not significantly affected by the operating frequency of the
transformer even when it is assumed to be 1800 Hz, consideringthat the switching frequencies for S1yz are very close to the casewhere the inverter operates with dc voltage sources. On the otherhand, the switches in the cell processing the highest power (S2yz)
S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714 709
Table 3Transition states for the first CHB-2bs cell.
ig. 6. Comparison among switching frequencies: (a) S11 and S13 correspond to tnverter operation with ac voltage sources at 300 Hz.
perate with switching frequencies lower than that of the trans-ormer. Besides, a significant reduction of the frequency ratio withespect the operation at 1800 Hz can be verified.
An example obtained by simulation shows the gating pulses forwitches S11 and S13 while the inverter operates with dc voltageources, and also the gating pulses applied to S11a and S13a wherehe inverter employs a transformer operating at 300 Hz consideringne cycle of the output voltage in Fig. 6. It can be seen that switches11a and S13a operate with lower frequency in this case.
Table 5 shows the THD of the output voltage Vo (before the filter)or different values of the transformer frequency operating withL = 2us.
.3. Power processed by the asymmetrical inverter
The maximum value of the fundamental output voltage Vomaxf 1 ,
ig. 7 that can be assumed by the inverter can be expressed in terms
erter operation with dc voltage sources and (b) S11a and S13a correspond to the
of a Fourier series as shown in Eqs. (1)–(3). Finally, it is possible torewrite it in Eq. (4) knowing that term Vdc can be expressed asa function of the maximum voltage that can be assumed by thesecond cell, resulting in Eq. (19).
Vomaxf 1
= 4Vdc
�.
[cos
(sin−1 1
7x
)+ cos
(sin−1 3
7x
)+ · · · cos
(sin−1 7x − 2
7x
)]
= 4�
Vomaxh2
3 · 7x−1cos
[sin−1
(2i + 1
7x
)] 7x − 12
− 1∑i=0
(19)
Fig. 7 shows the waveforms of the voltages across the output
sides of the CHB-2bs cells, as well as the respective maximumvalues of their fundamental components, the output voltage Vo(t)and its corresponding fundamental component Vof 1, and also itsrespective maximum value i.e., (Vo)max
f 1 = 100%.
710 S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714
Table 5Transformer frequency versus THD (Vo) for TL = 2 �s.
Table 6Power processing profile of the proposed inverter.
Description Voltages (V) Processed power (%)
Second CHB-2bs cell (Voh2)maxf 1 = 1.10 · Vomax
h295%a
First CHB-2bs cell (Voh1)maxf 1 = 0.06 · Vomax
h25%a
Inverter output Vomaxf 1
= 1.16 · Vomaxh2
100%
(Vo )max
ig. 7. Relevant waveforms (a) output voltage Vo(t), (b) voltage across the secondell Voh2(t) and (c) voltage across the first cell Voh1(t) and respective maximumalues of the fundamental components (Voh2)max
f 1 and (Voh1)maxf 1 .
In order to obtain the maximum fundamental components of theutput voltage across the cells, expression (20) can be employed.
Vohxd)maxf 1 =
{Vomax
f 1 | x=xt−xd+1, for xd = xt,
Vomaxf 1 | x=xt−xd+1 − Vomax
f 1 | x=xt−xd, for xd /= xt
(20)
The second statement shown in Eq. (20) can be seen graphicallyn Fig. 7 for the inverter operating with two cells (xt = 2), when its desired to obtain the maximum fundamental component of the
rst cell (xd = 1), which is expressed as Vomaxf 1 | x=2 − Vomax
f 1 | x=1.
The power processed by the inverter Po can be written accordingo Eq. (21), where (Vohxd)rms
f 1 and (Iohxd)rmsf 1 correspond to the rms
alues of the fundamental components of the output voltage andutput current in cell xd, respectively, and � is the phase shift angle.
o = 1T
∫ T
o
io(t)vo(t)dt =x∑
xd=1
(Vohxd)rmsf 1 · (Iohxd)rms
f 1 .cos � (21)
Since the CHB-2bs cells are connected in series, the currentowing through them is equal to the load current i.e., (Ioh1)rms
f 1 =Ioh2)rms
f 1 = (Io)rmsf 1 . It is also known that the voltages across the cell
utputs Voh1 and Voh2 in Fig. 7 are in phase and therefore the sameower factor exists in this case. Thus, taking into account the afore-entioned statements, it can be concluded according to Eq. (21)
hat the output power Po is the sum of powers processed by theHB-2bs cells as the inverter power distribution is associated witherm (Vohxd)rms
f 1 only, which is the rms value of the fundamentalomponent of the output voltage for each CHB-2bs cell (xdth).
Table 6 summarizes the operating features of the proposed mul-ilevel inverter.
Table 5 shows that most power is processed by the second cell,
hich corresponds to 95% of the output power, while the first cell
s responsible for processing only 5%. It is worth to mention thathe cell that processes the highest amount of power operates atow frequency and vice versa. This characteristic is quite prominent
a Ratio given by PhxdPo = hxd f 1
Vomaxf 1
, where Phxd is the power processed by the desired
cell xd, as xd = 1 and xd = 2 for the first and second cells, respectively.
for high-power applications considering that switching losses arereduced and the converter efficiency is significantly increased.
6. Comparison with other inverter topologies
Considering the aforementioned aspects, it can be stated thatCHB-symmetrical inverter in Ref. [33] presents reduced componentcount compared with conventional topologies such as neutral pointclamped (NPC) and flying capacitor (FC). It is also known that thenumber of active switches (on switches) per synthesized levels inthe conventional NPC, FC, and CHB-symmetrical topologies is thesame. Thus, this work has adopted the CHB-symmetrical inverteras a reference to compare it in terms of the number of on switchesin the proposed topology.
Fig. 8 shows a comparison between the classical CHB-symmetrical inverter topology using independent voltage sourcesand the proposed one considering the number of on switches.
As it can be seen in Fig. 8, the common point to the three curvesshows the same number of on components (i.e., six switches) con-sidering that all inverters operate with seven levels. Besides theCHB-symmetrical inverter in this case operates with three inde-pendent voltage sources, while the proposed solution uses a singledc voltage for the whole operating range defined in the graph.
Fig. 8 also shows that the number of on components increasessignificantly as the number of levels becomes higher than sevenin the CHB-symmetrical inverter if compared with the remainingapproaches.
Fig. 9 presents a comparison among the proposed solution, theCHB-Binary ac–ac inverter, and the CHB-Ternary ac–ac inverteremploying a HB with multi-winding transformer in order to obtainthe voltage sources for the cells. It can be seen that 10 switchesmust be turned on to generate seven levels in both the CHB-Binaryac–ac and CHB-Ternary ac–ac inverters. However, the proposed onerequires only six on switches in this case. Besides, it can be statedthe number of on components is drastically reduced as the numberof levels increases when comparing with the other configurations.
7. Experimental results
The laboratory prototype shown in Fig. 10 was implementedto validate the whole theoretical analysis. The converter designincludes a multi-winding transformer operating at 300 Hz, whilethe input voltage Vin = 48 V.
The inverter supervisory system was developed in an FPGA (fieldprogrammable gate array) model Ciclone IV EP4CE22F17C6N man-ufactured by Altera.
Since the external crystal that powers the FPGA operates at50 MHz, an internal phase-locked loop (PLL) module was employedto obtain a clock frequency which is a multiple of the inverter oper-ating frequency so that internal mathematical operations could beperformed without error accumulation.
The reference clock signal provided by the PLL module is 60 MHz.The clock signals for other peripherals as well as that for theanalog-to-digital converter (ADC) was obtained using 60-MHzclock frequency dividers. In addition, in order to ensure the accurate
S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714 711
Fig. 8. Comparison between the CHB inverter and the proposed topology considering the number of on switches per number of synthesized levels.
Fig. 9. Comparison among the proposed approach, the CHB-Bynary ac–ac inverter, and thof synthesized levels.
Fa
pdttcai
ig. 10. Experimental: prototype of the bidirectional multilevel converter withc–ac stage.
rototype operation, the code developed in VHDL (virtual hardwareescription language) must define the operating frequency of theransformer ftr as a multiple of the output frequency f1. It is worth
o mention that the commutation of the switches in the CHB-2bsells must occur when Vpr = 0 V in order to ensure the desired volt-ge Vo when the polarity of the voltage across the primary windings reversed so that short-circuit is avoided.
e CHB-Ternary ac–ac inverter considering the number of on switches per number
The prototype was evaluated considering an input volt-age Vin = 48 V, rms output voltage Vo = 220 V and output powerPo = 600 W when the inverter supplies an RL (resistor–inductor)load (Ro = 77.4 �, Lo = 19.2 mH).
The contribution of each CHB-2bs cell for the achievement of 49levels in the desired waveform is shown in Fig. 11.
Fig. 12 is shown the current in the primary winding controlledand without spikes, which validates the implementation.
According to Figs. 11 and 12, the resulting waveform does notpresent voltage spikes during the level transition, thus validat-ing the successful application of optimum switching states for theinverter operation with inductive loads.
The existing discontinuities in the voltage waveforms rep-resented in Figs. 11–13 are due to the zero-crossing intervalcorresponding to TL = 2 �s, which is used by the HB that suppliesthe transformer primary winding. However they can be attenuatedby reducing TL and using a proper output filter.
8. Conclusions
This paper has presented a new bidirectional multilevel inverterusing a multi-winding power transformer. The transformer stageoperates at medium frequency, thus reducing the overall converter
size and volume when compared to other topologies operating atlow frequency. Optimum switching states could be derived for theproposed inverter, thus allowing the operation with inductive loadswithout short-circuit issues.
712 S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714
Fig. 11. Waveforms in the inverter output stage. Voltages Voh1 and Voh2 across the first and second CHB-2bs cells, respectively, and 49-level output voltage without filtering.
nt Ipr
cr
hapt
Fig. 12. Output voltage Vo and curre
The comparison involving the proposed approach and otheronventional multilevel topologies has shown the significanteduction in the number of on state semiconductors.
The theoretical analysis carried out in this work has determined
ow the power processed by the inverter is effectively distributed,s it was shown that the first and second cells are responsible forrocessing 5% and 95% of the output power, respectively. Withinhis context, the analysis of the switching frequency for the opera-
controlled in the primary winding.
tion with an ac–ac stage has shown that cells that process the higheramounts of power operate at lower frequencies, thus contributingto the minimization of switching losses.
Besides, an interesting behavior could be verified when inves-
tigating different values for the transformer operating frequency,even when it operates at 1800 Hz. In this case, the switching fre-quency for the switches in the first CHB-2bs cell is nearly the sameas that when the inverter operates with dc voltage sources. Con-
S.J. Mesquita et al. / Electric Power Systems Research 143 (2017) 703–714 713
rrent f
stfcaoss
airpiiohfil
A
U
R
[
[
[
[
[
[
[
[
[
[
Fig. 13. Output voltage and load cu
idering the analyzed range, the switches in the cell that processeshe highest amount of power have always presented switchingrequencies lower than the transformer operating frequency. Theentral switches of the aforementioned cell corresponding to S25znd S26z operate at a frequency that is 33% of the transformerperating frequency even at 1800 Hz. This characteristic operationhows that it is possible to reduce the inverter volume withoutignificant impact on switching losses.
It can be stated that the introduced inverter is promising forpplications to standalone PV systems and appropriate interfac-ng in dc–ac microgrids due to minimized losses and increasedobustness. The use of topologies with high resolution of the out-ut voltage employing few components is promising since there
s the possibility of eliminating the dc–dc converter to supply thenverter and regulating the load voltage by controlling the numberf levels only. The proposed structure is also able to operate withigh power density, which reduces the cost of implementing bulkylters and also introduces an approach that is also for adequate
ow-power applications.
cknowledgments
The authors acknowledge CAPES for the financial support andFC for providing overall support to this work.
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