Electrical Com Design

8/4/2019 Electrical Com Design

1/98

ELECTRICAL COMPONENTS FOR A FULLY

IMPLANTABLE NEURAL RECORDING SYSTEM

by

Cameron T. Charles

A thesis submitted to the faculty of

The University of Utah

in partial fulfillment of requirements for the degree of

Master of Science

in

Electrical Engineering

Department of Electrical and Computer Engineering

The University of Utah

August 2003


2/98

Copyright Cameron T. Charles 2003

All Rights Reserved


3/98

T H E U N I V E R S I T Y O F U T A H G R A D U A T E S C H O O L

SUPERVISORY COMMITTEE APPROVAL

of a thesis submitted by

Cameron T. Charles

This thesis has been read by each member of the following supervisory committee and by

majority vote has been found to be satisfactory.

Chair: Reid R. Harrison

Mark S. Miller

Richard A. Normann


4/98

T H E U N I V E R S I T Y O F U T A H G R A D U A T E S C H O O L

FINAL READING APPROVAL

To the Graduate Council of the University of Utah:

I have read the thesis of Cameron T. Charles in its final form and have found that (1) its format,

citations, and bibliographic style are consistent and acceptable; (2) its illustrative materials

including figures, tables, and charts are in place; and (3) the final manuscript is satisfactory to the

supervisory committee and is ready for submission to The Graduate School.

Date Reid R. Harrison

Chair: Supervisory Committee

Approved for the Major Department

V. John Mathews

Chair

Approved for the Graduate Council

David S. Chapman

Dean of the Graduate School


5/98

ABSTRACT

The human brain has long been a subject of study and fascination. There are certain tasks

for which our brains vastly outperform inanimate machines, and the brain is very computationally

efficient, dissipating 12 W of power versus > 50 W of power for a modern microprocessor. A

better understanding of how the brain functions has the potential to advance many branches of

engineering. In recent years, the advent of microelectrode arrays has allowed researchers to begin

understanding how the brain processes information. These arrays allow long-term simultaneous

recording of neural activity from many neurons simultaneously. The ideal system for long-term

multiunit recording would be a fully implantable device which is capable of amplifying the neural

signals and transmitting them to the outside world.

This work investigates several of the building blocks necessary for the micro-electronic

components of such a system. An overview is given of the components and requirements for a

fully implantable recording system. The bias circuitry for the electronics of a fully implantable

recording system is designed and implemented. This is done by surveying a number of designs

for each circuit component, evaluating each design against the requirements for a fully

implantable recording system, and then choosing the most suitable topology for design and

implementation. We also design and test a fully differential low-noise amplifier for use in these

systems. The amplifier is based on a previously reported single-ended version, and has the

advantage of rejecting interference caused by the digital circuitry of the recording system. The

fully differential amplifier is implemented with three different common mode feedback circuits.

Two common mode feedback circuits are standard designs, and the third is a novel design based


6/98

on floating gates. The floating gate common mode feedback circuit combines the advantages of

the two tested standard common mode feedback circuits, by combining a large allowable output

signal swing with continuous time operation.


7/98

TABLE OF CONTENTS

ABSTRACT....................................................................................................................................iv

1. INTRODUCTION...................................................................................................................1

2. FULLY IMPLANTABLE RECORDING SYSTEMS............................................................ 4

2.1 Overview of a Fully-Implantable Recording System..................................................... 42.2 Electrode Array and Tissue Interface ............................................................................. 52.3 Amplification and Signal Processing Electronics .......................................................... 7

2.4 Transmitter ...................................................................................................................102.5 Focus of this Work ....................................................................................................... 11

3. VOLTAGE REFERENCE.................................................................................................... 13

3.1 Voltage Reference Concepts ........................................................................................ 133.2 Voltage Reference Requirements ................................................................................. 153.3 Voltage Reference Topologies ..................................................................................... 163.4 Circuit Design...............................................................................................................183.5 Simulation Results........................................................................................................213.6 Experimental Results....................................................................................................22

4. CURRENT REFERENCE .................................................................................................... 27

4.1 Requirements................................................................................................................27 4.2 Architecture and Design............................................................................................... 284.3 Simulation Results........................................................................................................344.4 Experimental Results....................................................................................................36

5. FULLY DIFFERENTIAL LOW-NOISE AMPLIFIER........................................................ 42

5.1 Requirements for Low-Noise Biosignal Amplifiers..................................................... 425.2 Implementations of Low Noise Amplifiers.................................................................. 435.3 Amplifier Design..........................................................................................................45

6. COMMON MODE FEEDBACK CIRCUITS ...................................................................... 49

6.1 CMFB Circuit Principles..............................................................................................496.2 CMFB Circuit Designs.................................................................................................51

6.2.1 Continuous Time Version ........................................................................................ 526.2.2 Switched-Capacitor Version .................................................................................... 536.2.3 Floating Gate Version .............................................................................................. 54

6.3 Simulation Results........................................................................................................57


8/98

vii

6.4 Experimental Results....................................................................................................58

7. CONCLUSIONS...................................................................................................................64

Appendices

A. LOW NOISE AMPLIFIER FOR EEG ................................................................................... 65

B. BIPOLAR JUNCTION TRANSISTOR CHARACTERIZATION ........................................ 71

C. RESISTOR CHARACTERIZATION..................................................................................... 76

REFERENCES .............................................................................................................................. 81


9/98

LIST OF FIGURES

1. Block diagram of a fully implantable recording system..................................................... 5

2. Structure of single probe of the University of Michigan microelectrode array .................. 7

3. Assembled University of Michigan microelectrode array .................................................. 7

4. University of Utah microelectrode array ............................................................................ 8

5. Bandgap voltage reference block diagram........................................................................ 14

6. Schematic of bandgap voltage reference circuit core ....................................................... 19

7. Complete schematic of bandgap voltage reference........................................................... 20

8. Temperature simulation for voltage references ................................................................ 22

9. Voltage reference test chip photograph ............................................................................ 23

10.Measured voltage reference output variations with changing temperature ...................... 24

11.Measured voltage reference output variation for changing power supply........................ 25

12.Power supply rejection ratios for voltage references........................................................ 25

13.Standard current reference circuit.....................................................................................28

14.MOS splitter cell with simplification................................................................................ 30

15.Splitter cell chain with resistor simplification .................................................................. 32

16.Schematic of bias current generator core..........................................................................33

17.Schematic of bias current generator splitter chain............................................................ 34

18.Simulated current in splitter cell 5 with varying Vdd (revision 1).....................................35

19.Simulated current in splitter cell 12 with changing Vdd (revision 2) ................................36

20.Current reference test chip photograph.............................................................................37

21.Measured ratios of currents in consecutive splitter cells (revision 1)............................... 38


10/98

ix

22.Measured current in splitter cell 5 (revision 1)................................................................. 39

23.Measured current in splitter cell 12 (revision 2) ............................................................... 39

24.Measured current in splitter cells (revision 2), currents range from 7 A to 2 pA........... 40

25.Measured ratios of currents in consecutive splitter cells (revision 2)............................... 41

26.Supply currents vs. normalized noise for reported biomedical amplifiers........................ 44

27.Schematic of fully differential low noise amplifier .......................................................... 46

28.Incremental resistance of single MOS-bipolar element.................................................... 47

29.Schematic of operational transconductance amplifier used in low noise amplifier.......... 47

30.Resistor averaged CMFB circuit.......................................................................................50

31.Differential pair CMFB circuit ......................................................................................... 51

32.Continuous-time CMFB circuit ........................................................................................ 52

33.Schematic of switched capacitor CMFB circuit ............................................................... 53

34.Schematic of floating gate CMFB circuit ......................................................................... 54

35.Simplified schematic of floating gate programming circuitry.......................................... 56

36.Tunneling mechanism used to add electrons to the floating gate ..................................... 56

37.Transient simulation of the common mode output levels of each amplifier..................... 58

38.Die photograph of amplifier test chip ............................................................................... 59

39.Measured total harmonic distortion at 1 KHz for fully differential amplifiers................. 60

40.Measured common mode output levels of the amplifiers................................................. 61

41.Measured common mode output amplitude over frequency for each amplifier ............... 62

42.Measured oscillation frequency vs. power supply voltage for ring oscillator .................. 63

43.Schematic of LNA for EEG applications.......................................................................... 67

44.Schematic of operational transconductance amplifier used in EEG LNA........................ 67

45.Measured transfer function of EEG amplifier................................................................... 69

46.Measured EEG amplifier input-referred voltage noise spectrum ..................................... 69

47.Bipolar junction transistor implementation in a CMOS process ...................................... 72


11/98

x

48.Source current measurement for a unit-sized bipolar junction transistor ......................... 73

49.Beta coefficient characterization for unit-sized bipolar junction transistor...................... 74

50.Temperature coefficient characterization for BJT ............................................................ 75

51.Carbon resistor temperature coefficient fit ....................................................................... 77

52.Wire wound resistor temperature coefficient fit ............................................................... 78

53.Poly resistor temperature coefficient fit............................................................................ 79

54.Well resistor temperature coefficient fit ........................................................................... 79

55.Voltage sweep for well resistor......................................................................................... 80


12/98

LIST OF TABLES

1. Comparison of reviewed voltage reference topologies..................................................... 18

2. Simulated and experimental results for voltage references .............................................. 26

3. Experimental measurements of amplifiers........................................................................ 63

4. Operating point of OTA transistors for EEG amplifier .................................................... 70

5. Simulated and experimental characteristics of EEG amplifier ......................................... 70


13/98

ACKNOWLEDGMENTS

I would like to thank my parents for sponsoring my undergraduate education and

encouraging me to further my education.

I am deeply indebted to my advisor Prof. Reid Harrison for his patience and insight.

Much of the knowledge I gained during my time here was through conversations and interaction

with him. I also owe thanks to the National Science Foundation for funding this research.

I also thank my supervisory committee, Prof. Richard Normann and Prof. Mark Miller for

their comments and suggestions.

I thank my lab mates Anand, Anurag, Nate, James, and Ryan for providing daily

entertainment.

Thanks also to all the climbers who I spent time with during breaks from school work:

Chris, Barlow, Abbie, Eric, Alyssa, James, Matt and the WMC crew, and all the good folks at

The Front. Thanks also to my one non-climbing friend and compatriot, Sonia Matwin.

I have to thank my brothers for being my best friends, and finally I would like to thank

Roanne for being a princess and for having more faith in me than I have in myself.


14/98

1. INTRODUCTIONThe human brain has long been a subject of study and fascination. The advent of the

modern microprocessor has proven to be a great tool for modern science, and can perform some

tasks more effectively than a human brain. However, there are certain tasks for which our brains

vastly outperform inanimate machines (i.e. pattern recognition, performance in uncontrolled

environments). The human brain is also much more computationally efficient, dissipating 12 W

of power versus > 50 W of power for a modern microprocessor. For these reasons, a greater

understanding of how the brain functions has the potential to greatly advance many branches of

engineering.

The human brain is an incredibly complex structure, containing from 1010

to 1011

neurons, with each of these neurons communicating with approximately 103 other neurons. From

the early 1920s onward, it became possible to use microelectrodes to monitor the activity of a

single neuron, and this greatly accelerated the growth in our understanding of how the brain

functions. A variety of techniques have been developed which allow scientists to determine how

neurons act, how they communicate with each other, what kinds of neurotransmitters they use,

what molecular mechanisms underlie their excitability, and how they respond to sensory inputs.

One key principle that evolved from investigations of the organization of the nervous system is

that the brain is a massively parallel processor of sensory and motor information. In recent years,

the advent of microelectrode arrays has allowed researchers to begin understanding how the brain

processes information. These arrays allow long term simultaneous recordings of neural activity

from many neurons. The biggest road block in the advancement of the understanding of neural

circuits has been the lack of adequate instrumentation. To successfully carry out long term


15/98

2

multiunit recordings, the ideal system would be a fully implantable device which is capable of

amplifying the signals and transmitting them to the outside world.

This work investigates several of the building blocks necessary for the micro-electronic

components of such a system. Some of the requirements for these components are that they

consume very little power, and introduce minimal noise. The advent of VLSI (very-large scale

integration) silicon circuits has made miniaturization of the microelectronics possible down to a

scale where fully implantable recording units are now a reality. With further research their

capabilities will improve and they will become more widely used for neuroscience research.

We begin by giving an overview of the components and requirements of a fully

implantable recording system in Chapter 2. Key issues in the design and implementation are

discussed, and we highlight which of those issues this work will be addressing. In Chapter 3 we

discuss the requirements for a voltage regulator, and cover the design and testing of our

implementation. Chapter 4 starts by addressing the needs for a current reference, and then

provides details on our implementation. Chapter 5 discusses the use of fully differential

amplifiers in these applications, and presents a fully differential version of a previously reported

single-ended amplifier. Chapter 6 discusses common mode feedback circuits, and presents three

implementations for the fully differential amplifier discussed in Chapter 5, along with test results.

Finally, in Chapter 7, we discuss additional work which must be done to integrate this work into a

complete implantable recording system, and provide conclusions on what has been accomplished

by this work.

The main creative contribution of this work is the design, implementation, and testing of

the floating gate common mode feedback circuit discussed in Chapter 6. The results of this work

were published and presented at the Southwest Symposium on Mixed Signal Design in 2003 [67].

The second creative contribution involved the redesign of the low noise amplifier presented in

[12] for fully differential applications. The redesigned fully differential version is discussed in

Chapter 5. The final creative contribution was the redesign of the low noise amplifier presented


16/98

3

in [12] for electroencephalogram applications. The results of this work are pending publication in

the IEEE Journal of Solid State Circuits [50].


17/98

2. FULLY IMPLANTABLE RECORDING SYSTEMSThe development of instrumentation for simultaneous multi-point neural recording is of

paramount importance in furthering our understanding of neural processing techniques and how

neurons interact with each other. This chapter discusses the various components of a fully

implantable multi-electrode recording system, and the design issues surrounding each component.

The emphasis is placed on the electronic aspect of the system, as that will be the subject of

subsequent chapters.

2.1 Overview of a Fully-Implantable Recording SystemThere are many engineering disciplines which must be combined to produce a fully

implantable recording system (FIRS). The most prominent of these are electrical engineering,

mechanical engineering, and biomedical engineering. A block diagram of a FIRS is shown in

Figure 1.

The first components on the left are the electrodes. These electrodes are configured in an

array, and provide the interface between the biological signals being recorded and the electrical

components of the FIRS. The electrodes will be more fully discussed in Section 2.2 The next

two components perform the amplification and signal processing of the system. Each electrode

has an amplifier which increases the magnitude of the recorded signal while adding minimal

noise. The amplifiers feed into a multiplexer (MUX) which performs time domain multiplexing

on the signals to allow the information to be relayed to the outside world with minimal bandwidth


18/98

5

Figure 1: Block diagram of a fully implantable recording system

consumption. These electronic components are the subject of Section 2.3. The next component

is the transmitter (Tx), which is used to send the recorded signals to a receiver (Rx) in the outside

world. This component is also used to power the active circuitry in the FIRS, by receiving

electromagnetic radiation over an inductive link. The transmitter is discussed in Section 2.4

2.2 Electrode Array and Tissue InterfaceDesign challenges must be faced when creating a multi-electrode array. The first

requirement is that the array must be small to minimize tissue damage. The dimensions of the

complete array should be on the order of several millimeters. Another important requirement is

that the tip sizes of the electrodes must be very similar, so that the area (and thus the impedance

level) of each electrode site will be similar [1]. The design of the microelectrode array must also

take into account the problems presented by having the device implanted in living tissue for long

periods of time. The electrodes must be chemically inert so that they do not react with the tissue,

electrode

electrode

electrode

amplifier

amplifier

amplifier

MUX Tx Rx

DATA

POWER


19/98

6

and the FIRS must be encapsulated in hermetic packaging to protect the electronics from body

fluids.

Metal microelectrodes were originally used for neural recording applications [2], [3], but

they have several limitations. They are difficult to manufacture with reproducible tip sizes and

shapes, so the impedance varies significantly from electrode to electrode, and experiments using

them are not well controlled [4]. In recent years the focus has been on using lithographically

patterned thin films to manufacture microelectrodes. This allows a high level of control over

electrode size and the spacing between electrodes. Electrode arrays have been created from many

different materials ([5]-[8]), but those fabricated from silicon have been the most successful.

Silicon is biocompatible, and is capable of being micro-machined with the greatest precision of

all known materials [9]. Another advantage of using silicon is that designers can make use of the

extensive knowledge base of manufacturing techniques developed for integrated circuits.

There are several design centers for the fabrication of microelectrode arrays in North

America, and two of the major ones will be discussed here. One of these is the Center for

Integrated Sensors and Circuits in the Department of Electrical Engineering and Computer

Science at the University of Michigan [10]. Each probe in their array has a number of recording

sites spaced along its length, as shown in Figure 2. The probes are fabricated from a flat wafer of

silicon, which allows the microelectronics to be fabricated on the same piece of silicon as the

probe. A number of these probes are then combined using micro-assembly techniques to form an

array, such as the one shown in Figure 3. The probe and shank spacings are in the 100-200 m

range. The current process makes use of epoxy covered by silastic to encapsulate the device.

This encapsulation works adequately for short and intermediate term implants, but for long term

implants a fully hermetic seal will be needed, and ongoing research efforts are investigating

appropriate systems.


20/98

7

The other microelectrode array discussed here [11] was developed in the Biomedical

Engineering Department at the University of Utah, and is being marketed by Cyberkinetics, Inc.

(Salt Lake City, UT). The University of Utah microelectrode array is shown in Figure 4. Each

electrode is 1.5 mm long, and the interelectrode spacing is 400 m. The University of Utah

microelectrode array is machined from a block of silicon, so the electronics must be fabricated on

a separate piece of silicon. The arrays have a 4.2 mm x 4.2 mm glass/silicon composite base.

Electrical isolation between individual electrodes is provided by a glass dielectric. A micro-

machining process sharpens each needle, and the tip of each electrode is coated with platinum to

facilitate charge transfer. Electrical contacts are made on the back of the needles with insulated

gold wire, and the entire array (excluding the platinum tips) is encapsulated with polyimide.

2.3 Amplification and Signal Processing ElectronicsThere are many factors to take into consideration in the design of the amplification and

signal processing electronics for a FIRS. Perhaps the most fundamental requirements are that the

circuits to be implanted must be small and consume very little power. Specifically, they should

Figure 2: Structure of single probe of theUniversity of Michigan microelectrode

array

Figure 3: Assembled University ofMichigan microelectrode array


21/98

8

Figure 4: University of Utah microelectrode array

consume an area less than several millimeters in each dimension to minimize tissue damage, and

dissipate less than 5 mW so that the temperature rise in the surrounding tissue is less than 1 C

[1]. The more difficult requirement is the area constraint, since most of the reported amplifier

circuits make use of integrated capacitors that consume considerable area. For example, a

recently reported amplifier [12] for a FIRS would be limited to 24 amplifiers per chip (for 1.5 m

technology on a 4 mm2

die) by the area constraint, but would only be limited to 62 amplifiers per

chip by the power constraint.

Another fundamental requirement is that the FIRS signal processing components must

contribute minimal noise to the recorded signal. The signals being recorded are on the order of

tens of micro volts, so significant noise contribution from the electronics will overwhelm the


22/98

9

signal. The FIRS circuitry should have an input referred noise less than 5-10 Vrms, which is

similar to the noise already present in the recorded signal [1].

Additional amplifier design challenges are to reduce cross talk between channels,

perform impedance transformation (typical recording sites have 100 k -10 M of impedance,

making the signals very sensitive to leakage on the output leads [13]), and to reduce the distance

from the electrode to the front end amplifier (to reduce contamination by electromagnetic

interference).

Another problem for the amplifier component is the varying dc offsets present at the

electrode-tissue interface. The polarizability of some electrodes leads to large signal fluctuations

at low frequencies, which can cause amplifier saturation [14]. The open-circuit dc potential

between a buffered saline electrolyte and a gold electrode can be as high as +/- 50 mV [15]. The

most common solution is to use capacitors to AC couple the inputs and create a low frequency

cutoff [12], [13], [16]-[18]. The disadvantage of using capacitors is that they consume a large

amount of area, greatly increasing the size of the amplifier circuit. Other methods have also been

used to remove the dc offset, including correlated double sampling [19], and chopper modulation

[20].

Another consideration for relaying the recorded data to the outside world is the need to

minimize the number of channels being transmitted. In the case of a hardwired transmission

scheme this will reduce the number of leads, and in the case of an RF transmitter, this will reduce

the bandwidth required. The most common way to do this is with time division multiplexing.

The biggest problem with multiplexing is the additional noise injected from the clock circuitry.

Most of the interference occurs during clock transitions, including clock feed though from the

gate-drain overlap capacitance of the MOS switches and switching glitches coupled through the

power lines [21].

After insertion of the microelectrode array, not all of the electrodes will be near active

neurons. For this reason, some designs [13] include more electrodes than amplifiers, and have a


23/98

10

front end multiplexer for selecting the electrodes that will capture recordings. Only the selected

signals are then recorded and transmitted.

Another consideration for the FIRS is the circuitry used to bias the signal processing

electronics with the proper voltages and currents. A voltage reference circuit is needed to supply

a constant DC voltage which can be used to regulate a fluctuating power supply voltage down to

a stable level which can be used to power the signal processing circuitry. The transistors in the

analog circuitry must also have stable bias currents, in order to maintain stable transconductances.

This is particularly important for the amplifiers, since their bandwidth is determined by the bias

currents in the differential input pair. The bias currents supplied must be very small to minimize

the power consumption of the system. A current reference circuit is used for supplying these

stable bias currents. The requirements for the bias circuitry elements are that they have small

size, low power consumption, and the voltage and currents provided should be stable with

varying power supply voltages.

2.4 TransmitterThe final stage in the design of the FIRS is determining the means of powering the

implant and getting the data out. The simplest option uses a percutaneous plug to deliver power

and transmit data. This is an undesirable choice since the break in the skin provides a path for

infection to enter, putting the health of the implant recipient at risk.

Another straightforward method for powering the device would be to implant a battery,

however, this would require periodically replacing the battery, and is not a viable solution.

Currently, the most attractive option for powering an implantable device is to use an inductive

link. This is composed of two pancake shaped coils (inductors), one on the outside of the body

and one on the inside, which is part of the FIRS. These coils form a transformer through which

energy can be provided. One problem with these systems is that they generally have low

efficiencies. The receiver coil is usually much smaller than the transmitter coil (with a diameter


24/98

11

on the order of tens of millimeters), and the power transmission efficiency is low, with the FIRS

receiving less than 1% of the average emitted radio-frequency energy [22]. Another problem is

that the efficiency of the link is sensitive to the alignment of the coils relative to each other, so a

shift in the external coil can cause the power transmission to drop dramatically. Significant

research has been done in making the coils insensitive to misalignments ([23]-[26]). Another

method for powering the FIRS has been proposed recently, which involves using wireless near-

infrared power transmission to recharge an implanted lithium battery which then powers the FIRS

[27]. In this scheme, near-infrared light from an external laser diode is converted to electrical

power by a photodiode array implanted under the skin.

Several methods have been proposed for transmitting the recorded signal information to a

receiver outside the body. The most attractive option for minimal system complexity is to use

one inductive link both to power the FIRS and to transmit data from the device [28], [29]. One

way of doing this is to transmit the data using a form of amplitude shift keying called load shift

keying. This scheme uses the property of an inductive coupling in which a change of the

secondary (implanted) load is reflected onto the primary coil as a varying (reflected) impedance.

Other methods of transmission have also been proposed, including transcutaneous optical data

links [30], and a method in which current injected into the tissue by the implanted device was

used to produce voltage differences between different locations throughout the body, which are

then detected by surface electrodes [31].

2.5 Focus of this WorkThis work focuses only on the electronic components of the FIRS, discussed in Section

2.3. Specifically, Chapter 3 and Chapter 4 focus on developing bias circuitry for the electronic

components of the FIRS. These include voltage and current references, and a voltage regulator.

Efforts are made to minimize the area and power consumption of these circuits, for the reasons

outlined in the previous sections. Chapters 5 and 6 focus on the design of a low-power fully


25/98

12

differential amplifier for amplifying the signals before they are transmitted to the external

receiver. The fully differential design allows the amplifier to better reject any interference from

the digital components of the FIRS such as the multiplexer (design of the multiplexer is not

covered in this work.


26/98

3. VOLTAGE REFERENCEA voltage reference is an important part of any analog integrated circuit. Transistors in

analog integrated circuits must have stable bias currents in order to have stable

transconductances. Stable voltage references are usually required to generate these bias currents,

and are also used in other parts of analog circuits. For an analog circuit to operate reliably, the

reference voltage provided to the circuit must be stable over a wide range of temperatures and

power supply voltages. This chapter surveys various voltage reference topologies reported in

literature and chooses the one which is most appropriate for our application of a fully implantable

recording system. Transistor and component sizing is carried out, and simulation and test results

are reported.

3.1 Voltage Reference ConceptsAn ideal voltage reference circuit will supply a fixed DC voltage of known amplitude that

stays constant with changing temperature or external power supply voltage. Several approaches

have traditionally been used for accomplishing this, including: using a reverse biased zener diode

in breakdown mode, subtracting the threshold voltages of an enhancement transistor and a

depletion transistor, and eliminating the negative temperature dependence of a p-n junction with

the positive temperature dependence generated by a proportional to absolute temperature (PTAT)

circuit. The last approach is the most popular, and is used in all of the circuit topologies

considered here, so it will be discussed in this section.

A block diagram of standard bandgap voltage reference circuit is shown in Figure 5, with

the two voltage components which are added together to form the voltage reference.


27/98

14

Voltage Reference

KPTAT Generator

Figure 5: Bandgap voltage reference block diagram (K is a multiplier for the PTAT

component)

The first component of the voltage reference is the base-emitter voltage of a forward

biased bipolar transistor. The I-V relationship for this voltage is given by:

TkVq

SCBEeII

= (1)

HereIC is the collector current of the transistor,IS is the scale current, and VBE is the base-emitter

voltage. It can be shown that for constantIC, VBE has a -2.2 mV/K temperature dependence at

room temperature (25C).

The second component is the PTAT voltage, which can be formed by subtracting the

base-emitter voltages of two base-emitter junctions biased at different current densities. We can

show that the result of this subtraction is

=

1

2lnJ

J

q

TkVBE (2)

which clearly has a positive temperature co-efficient (J1 and J2 are the current densities of the

base-emitter junctions). The result of adding these components is


28/98

15

BEBEref VKVV += 2 (3)

where Kis a scaling constant that is adjusted to achieve zero temperature dependence at a specific

temperature.

This is the basic structure of the majority of the voltage reference circuit topologies that

are discussed here. See [32] or [33] for a more thorough review of bandgap voltage reference

concepts. Most of the designs use bipolar transistors available in CMOS processes to realize the

PTAT block, although MOS transistors operating in weak inversion and diodes are also used.

While this basic design compensates for the linear temperature dependence of a base-emitter

voltage, some designs use more complex circuitry to compensate for the quadratic temperature

dependence and thereby achieve reduced voltage variations over a larger temperature range.

3.2 Voltage Reference RequirementsThe most important requirement for a voltage reference in a fully implantable recording

system is that it be stable over a wide range of power supply voltages. Assuming the system is

powered by an inductive link, the coupling of the link will vary if the internal and external coils

shift relative to each other, so variations in the supply voltage received by the voltage reference

circuit will be likely. The other standard voltage reference requirement of being stable over a

range of temperatures is not as important for a fully implanted system, since the circuit will

remain at approximately 37 C (body temperature). Other requirements for the voltage reference

are that it be of minimal size and complexity, and that it consume very little power. The area

requirement stems from the need to keep the entire implantable unit as small as possible to limit

trauma caused by implantation, and the power requirement arises from the need to limit heating

effects on the tissue surrounding the implant. Additional requirements for the voltage reference

are that it should be possible to fabricate it in a standard CMOS process, and it should not require

any special post-processing techniques (i.e., laser trimming, etc.) to achieve the desired results.


29/98

16

3.3 Voltage Reference TopologiesThe first design considered is unique in that it makes use of MOS transistors operating in

weak inversion to realize the PTAT component of the reference [34]. This is possible since the I-

V characteristics of a MOS transistor in weak inversion is described by

( )TknVqDD

GSeL

WII

= 0 (4)

whereID is the drain current of the MOS transistor, ID0 is an intrinsic unit current, VGS is the gate-

source voltage, and n is the slope factor. This is an exponential relationship similar to that of the

bipolar transistor that is normally used. One drawback of this design is that the base-emitter

voltage component is generated from an npn bipolar transistor which requires a p-well process or

an additional p-base layer. This additional layer is not available in most standard CMOS

processes, so fewer processes can be used for implementation of the circuit.

The second design reviewed makes use of lateral bipolar transistors rather than the

vertical ones used in most designs [35]. The advantage of using lateral transistors is that they do

not need to have the collector tied to the substrate (as is the case with standard vertical BJT

transistors), which allows greater design flexibility. The lateral transistors used in this design can

be realized by biasing the gate of a MOS transistor well below its threshold voltage so that an

accumulation layer forms (preventing normal MOS transistor operation), and properly biasing the

other terminals to obtain a bipolar operating mode. The drawback of this approach is the negative

gate voltage required for proper operation. An alternative means of creating a lateral bipolar

transistor is to use an additional layer (p-base), however, this layer is not available in most CMOS

processes. This design improves on the traditional design by reducing the contribution of the

amplifier offset voltage to the final voltage reference. The offset voltage is not PTAT and thus

cannot be compensated for, so it is one of the major causes of error in a traditional voltage

reference circuit.


30/98

17

The third design creates a voltage reference that is floating, instead of being set with

respect to the positive or negative supply [36]. As a result, the common mode value of the

reference must be set by a common mode feedback circuit (CMFB), so this design would be

useful in a system where the voltage reference has to interface with other differential circuit

blocks that already have CMFB circuits. The extra circuitry required for the floating reference

adds complexity, and since this would not provide an advantage in our application, this design

will not be considered further.

The fourth design has been optimized to minimize all sources of error and realize a very

precise voltage reference [37]. In addition to the standard PTAT correction voltage, this design

makes use of a quadratic (PTAT2) temperature correction voltage to minimize the temperature

drift. This design employs a complicated two step trimming procedure where both capacitor

arrays and resistor strings are trimmed to achieve 12 bit accuracy in the reference voltage. This

circuit has the highest complexity of all of the designs reviewed here.

The next design reviewed is similar to the previous one in that it adds an additional

voltage component to compensate second order temperature variations not accounted for by the

standard PTAT correction term. It differs in that it uses current-mode correction to allow

operation with supply voltages down to 1.1 V [38]. A p-base layer is required to create bipolar

transistors with collectors not connected to the substrate, and it makes use of a JFET in its start up

circuit (a device that is not available in standard CMOS processes). It also makes use of a

complex multi-step trimming procedure to achieve a zero temperature coefficient at the desired

temperature.

The sixth design is a low voltage design that uses current-mode operation to allow lower

supply voltages [39]. In simulations, the circuit had an output of 0.84V, which is lower than a

conventional bandgap reference voltage by 0.46V. This design requires that native NMOS

transistors be available, since the threshold voltages of enhancement mode NMOS transistors are

too high to achieve the low voltage operation.


31/98

18

The last design reviewed uses a simple circuit topology which does not require an op-

amp (as most traditional designs do), while allowing low supply voltages and providing a good

power supply rejection ratio (PSRR) [40]. This design does not make use of any additional

layers, and the base-emitter voltages are realized by bipolar transistors that can be implemented in

any n-well CMOS process. Some advantages of this design are that it achieves good results

without trimming, and the circuit has a low level of complexity. An additional advantage is that

part of the circuit regulates the supply voltage down to a lower controlled voltage, so the output

will remain stable for changing power supply voltages. The performance and features of each

voltage reference reviewed is summarized in Table 1. The final design [40] was chosen for

implementation, since it came the closest to meeting the requirements outlined in Section 3.2.

3.4 Circuit DesignThis section provides details on the design carried out for the chosen circuit topology.

The approach taken for the transistor sizing was to choose a value for the currents in the

important circuit branches, then choose resistor sizes and device ratios to achieve a zero

Table 1: Comparison of reviewed voltage reference topologies

Design Implementable in

Standard CMOS

Process

Post-Processing

Required

Complexity Stability for

Changing

Power Supply*

Temperature

Coefficient*

[34] No No Low N/A 70 ppm/C (0C

to 65C)

[35] No Yes Low N/A 23 ppm/C (0C

to 70C)

[36] Yes No High N/A 21 ppm/C (0C

to 100C)

[37] Yes No High N/A 13 ppm/C (0C

to 70C)

[38] No Yes Moderate 408 ppm/V

(1.2V to 10V)

20 ppm/C

(15C to 90C)

[39] No No Low 1080 ppm/V

(2.2V to 4V)

59 ppm/C

(27C to 125C)

[40] Yes No Low N/A 85 ppm/C

(-40C to 85C)

*Temperature coefficients and power supply coefficients cannot be compared directly since different

papers used different temperature and voltage ranges in measuring them.


32/98

19

temperature coefficient at 37C, and then choose transistor sizes to insure that all devices are in

the active region.

The core of the bandgap circuit is shown in Figure 6. HereNis the ratio of the widths of

MOS transistors M1 and M3, and Mis the ratio of the emitter areas of bipolar transistors Q2 and

Q1. Additional feedback circuitry (not shown in this schematic, see Figure 7 for details) forces

the voltage atNode1 to equal the voltage atNode2, in turn forcing the currents inM1 andM2 to be

equal. Using these conditions, the bandgap voltage VBG, is derived as:

( )[ ] TBEBG VNMR

RNVV ++= 1ln

2

1

2 (5)

Here VBE2 is the base-emitter voltage of bipolar transistor Q2, which has a temperature coefficient

of -2.2 mV/C at 25C, and VT is the thermal voltage, which has a temperature coefficient of

+0.085 mV/C. Taking the derivative of (5) with respect to temperature, setting it equal to zero,

M3M1 M2

Q1 Q2

R1R2I

To control loop

M:1

1:N1:1

I

V_reg

Node1

Node3 Node2

V_bg

R2R1

Q2Q1

M2M1 M3

Figure 6: Schematic of bandgap voltage reference circuit core


33/98

20

and substituting in the temperature coefficients, we arrive at the following equation for the

transistor sizes and device ratios:

( )[ ] 88.251ln1

2 =+ NM

R

RN (6)

ChoosingM= 9.5 andN= 4 in this equation, we get R2/R1 = 1.78. So, choosingR1 = 10 k, we

calculate thatR2 = 17.8 k.

Figure 7 shows the complete schematic. The next step was to choose a drain current for

M1 andM2. A current of 10 A was chosen to minimize power consumption. The next step was

to perform steady state calculations for all the nodes of the circuit and adjust sizing and ratios to

insure that all devices were in the active region. The default sizing for transistors was W/L = 19.2

m/6.4 m, to provide good matching between devices. The final sizing for all devices is shown

on the schematic in Figure 7. Note that some of the device sizes differ from those calculated

above, due to optimizing after simulations were run.

L=8*l

mult=1

M9W=32*l

L=8*l

mult=1

M8W=32*l

L=8*l

mult=9

M14W=32*l

L=8*l

mult=1

M15W=32*l

L=8*l

mult=1

M6W=32*l

L=8*l

mult=1

M4W=32*l

L=8*l

mult=4

M3W=32*l

L=8*l

mult=1

M1W=32*l

L=8*l

mult=1

M2W=32*l

L=8*l

mult=1

M13W=32*l

L=8*l

mult=1

M12W=32*l

L=8*l

mult=1

M5W=32*l

L=8*l

mult=1

M7W=8*l

L=8*l

mult=1

M11W=32*l

L=8*l

mult=2

M10W=32*l

area=1

mult=9

Q1area=1

mult=1

Q2

R110000

R2

16800

V_reg

Node1

Node3 Node2

V_bgNode5

Node7

Node8

Node4

Node9

Node6

W=32*l

M9

mult=1

L=8*l

W=32*l

M8

mult=1

L=8*l

W=32*l

M14

mult=9

L=8*lW=32*l

M15

mult=1

L=8*l

W=32*l

M6

mult=1

L=8*lW=32*l

M4

mult=1

L=8*lW=32*l

M3

mult=4

L=8*lW=32*l

M1

mult=1

L=8*lW=32*l

M2

mult=1

L=8*l

W=32*l

M13

mult=1

L=8*l

W=32*l

M12

mult=1

L=8*l

W=32*l

M5

mult=1

L=8*l

W=8*l

M7

mult=1

L=8*l

W=32*l

M11

mult=1

L=8*l

W=32*l

M10

mult=2

L=8*l

Q1

mult=9

area=1

Q2

mult=1

area=1

10000

R11

6800

R2

Figure 7: Complete schematic of bandgap voltage reference (l = = 0.8m)


34/98

21

3.5 Simulation ResultsAccurate simulation results were difficult to obtain before a chip was fabricated, because

an accurate value for the resistance of the poly resistors was not known, and accurate parameters

for the bipolar junction transistors (BJTs) were not available. Simulations were carried out using

approximate resistance values and BJT parameters, but they did not accurately reflect the test

results. After testing and characterizing the chip, actual resistance values and BJT parameters

were extrapolated from the test data, and the circuits were re-simulated. This simulation data

matched the measured data very closely, and is the data that is reported here as revision 1.

Another version of the chip was then fabricated, using the test and simulation data from the first

revision to lay out resistors with more accurate values. This version had large performance

improvements over the first revision, and the results for this design are listed as revision 2.

Results of the temperature simulations are shown in Figure 8. The resistor ratioR2/R1 in

the first revision was too high, but test results allowed a more accurate ratio for the second

revision. Characterization of the first revision revealed that the value of the resistorR2 in the first

revision was 14 k, which is significantly greater than the target resistance of 6.8 k. These

resistor values differ from the calculated values in the previous section, which were estimated

using approximate BJT parameters. For the second revision, five voltage reference layouts were

created, with target resistances of 6.4, 6.6, 6.8, 7.0, and 7.2 k in an attempt to bracket the

desired value of 6.8 k. The temperature simulation for the second revision use the resistance of

6.8 k, and it can be seen from Figure 8 that the temperature variance is much smaller than for

the first revision. Revision one varies by 41 mV over the temperature range simulated (1353

ppm/C), while revision two varies by 3.6 mV over the temperature range (169 ppm/C).

Power supply simulations were also carried out on the voltage references. Both revisions

required a minimum supply voltage of 3 V to produce a stable output voltage. For the supply

voltage ranging from 3 V to 10 V, revision 1 varied by 19.5 mV (1873 ppm/V), while revision 2

varied by 2 mV (268 ppm/V), a significant improvement.


35/98

22

30 32 34 36 38 40 42 44 46 48 501.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

1.45

1.5

1.55

Temperature (degrees C)

Vo

ltage

Re

ference

Ou

tpu

t(V)

revision 1revision 2

Figure 8: Temperature simulation for voltage references

The power supply rejection characteristics of the voltage references were also simulated.

This is an important parameter for a voltage reference in an FIRS, since the power is transmitted

through an inductive link and it is likely that there will be some variance in the supply voltage.

Over the simulated range from 1 kHz to 100 kHz, the power supply rejection ratio (PSRR) of

revision 1 varied from -70 dB to -56 dB, while the PSRR for revision 2 showed significant

improvement, varying from -83 dB to -62 dB.

3.6 Experimental ResultsA photograph of the test chip including the voltage reference is shown in Figure 9. The

voltage reference is contained within the white box in the lower right hand corner of the chip.

The layout for all of the revisions is the same except for the size ofR2.


36/98

23

Figure 9: Voltage reference test chip photograph (layout of voltage reference is contained inthe white box in the lower right hand corner)

As mentioned in the previous section, only one version of the voltage reference was

fabricated for the first revision, but for the second revision there were five versions fabricated,

one with the target resistance, and two for bracketing purposes on either side.

Figure 10 shows the test results for the temperature variance of the voltage references.

The revision 1 voltage reference had a variation of 38 mV over the temperature range from 30C

to 50C, for a temperature coefficient of 1278 ppm/C. The revision 2 voltage references had

variations ranging from 2 mV to 3.5 mV, and temperature coefficients ranging from 94 ppm/C to

165 ppm/C. The temperature coefficients of each of the versions of the revision 2 voltage

reference did not match the simulation results exactly, this is likely due to the ~20% tolerance on

poly resistors in this process, which means that the coefficient with the middle resistance of 6.8


37/98

24

30 32 34 36 38 40 42 44 46 48 501.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

1.45

1.5

1.55

Temperature (degrees C)

Vo

ltage

Re

ference

Ou

tpu

t(V)

revision 1revision 2 (R

2= 6400 k)

revision 2 (R2

= 6600 k)

revision 2 (R2

= 6800 k)

revision 2 (R2

= 7000 k)

revision 2 (R2

= 7200 k)

Figure 10: Measured voltage reference output variations with changing temperature

k could be as high as 8.2 k or as low as 5.4 k, which is a much greater range than the range

of designed resistances.

Figure 11 shows the output voltages for each of the voltage references plotted against the

power supply voltage. The revision 1 voltage reference has a minimum supply voltage of 3.3 V,

while the minimum supply voltage for the revision 2 voltage references vary from 3.4 V to 3.7 V.

The variation in the output for supply voltages from 3.8 V to 10 V was 66 mV (7108 ppm/V) for

revision 1, and ranged from 48 mV to 55 mV (7138 ppm/V to 7930 ppm/V) for revision 2. The

output variations for changing supply voltages were much greater in the experimental results than

in the simulated results (see Table 2 for a comparison).

Figure 12 plots the power supply rejection ratio (PSRR) for each of the voltage references

at frequencies from 1 kHz to 100 kHz. The revision 1 voltage reference has a PSRR between 62


38/98

25

1 2 3 4 5 6 7 8 9 100.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Power Supply Voltage (V)

Vo

ltage

Re

ference

Ou

tpu

t(V)

revision 2 (R2

= 6400 k)

revision 2 (R2

= 6600 k)

revision 2 (R2

= 6800 k)

revision 2 (R2

= 7000 k)

revision 2 (R2 = 7200 k)

revision 1

Figure 11: Measured voltage reference output variation for changing power supply

103

104

105

45

50

55

60

65

70

75

80

Frequency (Hz)

Power

Supp

lyRe

jec

tion

Ra

tio

(dB)

revision 2 (R2

= 6400 k)

revision 2 (R2

= 6600 k)

revision 2 (R2

= 6800 k)

revision 2 (R2 = 7000 k)revision 2 (R

2= 7200 k)

revision 1

Figure 12: Power supply rejection ratios for voltage references


39/98

26

dB and 46 dB over this range, while the revision 2 voltage references have PSRR varying from 78

dB to 47 dB over this range. Experimental and simulated results for the voltage references are

summarized in Table 2.

Table 2: Simulated and experimental results for voltage references

Parameter Revision 1 Revision2

Simulation Experimental Simulation Experimental

Power Supply Range 3 to 10 V 3.3 to 10 V 3 to 10 V 3.4 to 10 V

Power Dissipation (5 V

supply)

660 W N/A 555 A N/A

Area N/A 0.060 mm2 N/A 0.044 mm2

Mean VBG 1.515 V 1.499 V 1.063 V 1.067 V

Temperature Coefficientfor 30C - 50C

1353 ppm/C 1278 ppm/C 169 ppm/C 94 ppm/C

Power Supply Coefficientfor 3 V 10 V

1873 ppm/V 7108 ppm/V 268 ppm/V 7138 ppm/V

PSRR

At 1 KHz -70 dB -57 dB -83 dB -78 dB

At 10 KHz -70 dB -62 dB -80 dB -66 dB

At 100 KHz -57 dB -46 dB -62 dB -47 dB


40/98

4. CURRENT REFERENCEAnother fundamental building block for integrated circuits is the current reference.

Transistors in integrated circuits must have stable bias currents in order to have stable

transconductances. This biasing is usually done by an on-chip current reference, which derives a

stable bias current from a voltage reference (such as the one discussed in the previous chapter).

The availability of stable bias currents is especially important for a fully implantable recording

system, where reliable bias currents must be available to keep the analog amplifiers in the proper

mode of operation. The current levels provided must be low to keep down the overall power

consumption.

4.1 RequirementsThe requirements for a current reference in a FIRS are similar to the requirements

discussed for the voltage reference. Area and power consumption must be kept to a minimum, to

minimize the overall size of the device and the resulting trauma from the implantation, and to

minimize heat dissipation which could damage the surrounding tissue. Stability with changing

temperature is less important, since in a fully implanted system the temperature of the device will

remain approximately constant at the body temperature of the host. One other important

requirement is that the current reference must be capable of supplying low bias currents without

making use of large resistors which consume a lot of chip area.


41/98

28

4.2 Architecture and DesignFigure 13 shows the schematic of a standard current reference circuit, using four

MOSFETs and one resistor. Transistor M3 has M times the W/L ratio of transistor M4.

Considering first the bottom two transistors, and assuming they are operating in the subthreshold

region, their drain currents will be given by the expressions:

( )

=

Tknq

RIV

D

G

eL

WMII

3

03 (1)

( )

=

Tknq

V

D

G

e

L

WII 04 (2)

whereID0 is an intrinsic unit current, VG is the absolute gate voltage of the transistors, and n is the

slope factor. The top transistorsM1 andM2 act as a current mirror, forcing I3 andI4 to be equal,

so if we equate them and solve for the currentI3 =I4 =IB:

( ) RVMI TB log= (3)

where VT is the thermal voltage, kT/q. The resistor and the size difference between the transistors

R

M3 M4

M2M1

I3 I4

VSS

VDD

Figure 13: Standard current reference circuit


42/98

29

force the current to this stable operating point, provided it is non-zero. There is another stable

operating point for IB = 0, and this requires us to add a startup circuit (discussed in the next

section) to ensure that the current does not remain at zero after power up. IfM3 andM4 operate in

the above threshold region, a similar procedure can be followed to derive the bias current as:

( )( )22 112 MRIB = (4)

where = CoxW/L, is the carrier mobility, and Cox is the oxide capacitance.

Some problems with this circuit are that it can be sensitive to variations in temperature,

and the relative tolerance on the current can be poor due to poor resistor tolerances in integrated

circuits. A CMOS temperature-compensated current reference is presented in [41] which uses a

number of transistors in place of the resistor to achieve better stability over temperature, and

improve the current tolerance. Due to the large number of transistors used in this implementation

(39), the area consumption is greater than other designs. Additionally, since temperature stability

is of secondary importance for our application, the extra area required for this implementation is

not a good tradeoff. A simplified resistorless current reference is presented in [42], however the

authors report that this design suffers from a low power supply rejection ratio (10% per volt) and

a large spread in the current reference outputs ( 30%).

Another problem with the standard circuit is that low current levels can only be achieved

with large resistors, which consume significant layout area. For implantable devices we require

low currents as well as low area consumption, and a design to satisfy these requirements is

presented in [43]. This design eliminates the resistor by using different thicknesses for the gate

oxides of transistors M3 andM4. The disadvantage of this approach is that it requires a process

with different gate oxide thicknesses, which are not normally found in standard CMOS processes.

An alternate solution to this problem, and the one we chose to implement, is presented in

[44]. This approach is to use the standard current reference circuit shown in Figure 13, and to

achieve low currents by using splitter cells to reduce the bias current down to the desired values.


43/98

30

An individual splitter cell is shown in Figure 14, along with a simplification where the transistors

are considered resistances with different values. The different resistance values are achieved by

sizing the transistors with different W/L ratios. In the implementation detailed in [44], the output

current derived from the circuit in Figure 13 is fed into a number of splitter cells (such as the one

shown in Figure 14) connected in series, and at each splitter cell stage the current is reduced by a

constant ratio.

To demonstrate why the substitution shown in Figure 14 is valid, consider the following.

A single MOS transistor has forward and reverse currents, and for a transistor operating in the

weak inversion region, the total current can be expressed as the following:

dgsg VVVV

rf eeL

Wee

L

WIII

== (5)

where If and Ir are the forward and reverse currents, Vg is the gate voltage, Vs is the source

voltage, Vd is the drain voltage, and is the subthreshold gate coupling coefficient. Now, in the

circuit on the left side of Figure 14, we can express the currents shown as:

111

1

VVVee

Be

BI gg

= (6)

211

2

VVVee

Be

BI gg

= (7)

A

BB

A

B BI2I1

T

I1 I2

TV1

V1V2

V2

VG

Figure 14: MOS splitter cell with simplification (A andB are the transistorL/Wratios)


44/98

31

2211 VVVV

eeA

eeA

T gg

= (8)

Solving expressions (6) and (7) for e-Vg

eV1

and e-Vg

eV2

and subbing into expression (8) yields the

following expression for T:

( )21 IIA

BT

= (9)

Now considering the circuit on the right side of Figure 14, we can write the following expressions

for V1 and V2:

11 IBV = (10)

22 IBV = (11)

Now it is clearly seen that Tis again given by the expression in (9). From this we can see that the

circuits are equivalent, and that changing L/W ratios of the MOS transistors serves a similar

function as changing the values of resistors.

An example of a chain of splitter cells using the resistor simplification is shown in Figure

15. For this derivation we assume that the splitter cells continue indefinitely, in which case we

can choose a point and replace the subsequent splitter cells with a resistance of:

( )BCAC += (12)

We now wish to derive the ratio between the currents in branches i and i+1, as labeled in Figure

15. It can be seen that:

B

CI

B

VI ii

== (13)

==+

B

CIIII ii 11 (14)


45/98

32

A

B C

AA

BB Ii Ii+1

I

Vi

Figure 15: Splitter cell chain with resistor simplification

Now we can find the ratioR as:

11 == +

C

B

I

IR

i

i (15)

Solving (15) for C, substituting into (12) and rearranging yields:

( ) RRBA 21= (16)

From this equation, we can choose a ratio R for currents in consecutive splitter cells, choose A

value ofB, and then calculate a value forA. We can then calculate a value for Cusing (15), and

then use these values for the W/L ratios in the transistors of the splitter cells. A more detailed

analysis of the splitter cells can be found in [32]. This approach allows us to make use of the

simple standard current reference, and since we reduce the generated bias current using the

splitter cells, we can achieve low bias currents without having to use large resistor values. An

additional advantage of this approach is that different bias currents are available at each splitting

stage.

The schematic of the implemented bias generator core is shown in Figure 16. Transistors

M1-M6 form the standard current reference which was shown in Figure 13. M3 and M4 are

cascode transistors which improve the power supply rejection. The capacitor is used to improve


46/98

33

L=8*l

mult=1

M16W=32*l

L=8*l

mult=1

M17W=32*l

L=8*l

mult=1

M12W=32*l

L=8*l

mult=1

M15W=32*l

L=8*l

mult=1

M13W=32*l

L=8*l

mult=1

M14W=32*l

C=10pF

L=8*l

mult=1

M6W=32*l

L=8*l

mult=1

M4W=32*l

L=8*l

mult=1

M5W=32*l

L=8*l

mult=1

M3W=32*l

L=2*l

mult=1

M8W=8*l

L=2*l

mult=1

M7W=8*l

L=64*l

mult=1

M2W=32*l

L=64*l

mult=1

M1W=32*l

L=40*l

mult=1

M9W=4*l

L=40*l

mult=1

M10W=4*l

L=40*l

mult=1

M11W=4*l

R117250

to splitter chain

mb

casc

bias

V_r

casc

bias

W=32*l

M16

mult=1

L=8*l

W=32*l

M17

mult=1

L=8*l

W=32*l

M12

mult=1

L=8*l

W=32*l

M15

mult=1

L=8*l

W=32*l

M13

mult=1

L=8*l

W=32*l

M14

mult=1

L=8*l

C=10pF

W=32*l

M6

mult=1

L=8*l

W=32*l

M4

mult=1

L=8*l

W=32*l

M5

mult=1

L=8*l

W=32*l

M3

mult=1

L=8*l

W=8*l

M8

mult=1

L=2*l

W=8*l

M7

mult=1

L=2*l

W=32*l

M2

mult=1

L=64*l

W=32*l

M1

mult=1

L=64*l

W=4*l

M9

mult=1

L=40*l

W=4*lM10

mult=1

L=40*l

W=4*l

M11

mult=1

L=40*l

17250

R1

Figure 16: Schematic of bias current generator core (l = = 0.8m)

stability and prevent oscillation. Transistors M7-M11 form the start up circuit, and prevent the

reference from remaining at the stable operating point with zero current. Upon power up,M7 is

on, which draws current though the current mirror and starts up the circuit. NextM8 is turned on,

which acts as a voltage divider withM9-M11 (which have very small W/L ratios). This drives the

gate ofM7 to GND, turning it off, so the circuit is no longer affected by the start up circuit.

TransistorM12-M17are used to connect the current reference to the splitter cells.

The splitter cell schematic is shown in Figure 17. Node mb on the right side of the

schematic in Figure 16 connects to node mb on the left side of the schematic of Figure 17. The

two transistors at the bottom of each splitter cell are used to mirror the current from the splitter


47/98

34

L=A*l

mult=1

M46

W=32*l

L=B*l

mult=1

M47

W=32*l

L=B*l

mult=1

M19

W=32*l

L=A*l

mult=1

M18

W=32*l

L=A*l

mult=1

M22

W=32*l

L=B*l

mult=1

M23

W=32*l

L=C*l

mult=1

M51

W=32*l

L=A*l

mult=1

M50

W=32*l

L=8*l

mult=1

M53W=32*l

L=8*l

mult=1

M49W=32*l

L=8*l

mult=1

M25W=32*l

L=8*l

mult=1

M21W=32*l

L=8*l

mult=1

M48W=32*l

L=8*l

mult=1

M20W=32*l

L=8*l

mult=1

M24W=32*l

L=8*l

mult=1

M52W=32*l

core

from

mb

biasbias bias

A1

B1

bias

vtest vtest vtest vtest

W=32*l

M46

mult=1

L=A*l

W=32*l

M47

mult=1

L=B*l

W=32*l

M19

mult=1

L=B*l

W=32*l

M18

mult=1

L=A*l

W=32*l

M22

mult=1

L=A*l

W=32*l

M23

mult=1

L=B*l

W=32*l

M51

mult=1

L=C*l

W=32*l

M50

mult=1

L=A*l

W=32*l

M53

mult=1

L=8*l

W=32*l

M49

mult=1

L=8*l

W=32*l

M25

mult=1

L=8*l

W=32*l

M21

mult=1

L=8*l

W=32*l

M48

mult=1

L=8*l

W=32*l

M20

mult=1

L=8*l

W=32*l

M24

mult=1

L=8*l

W=32*l

M52

mult=1

L=8*l

Figure 17: Schematic of bias current generator splitter chain (l = = 0.8m)

cells. The dashed lines in Figure 17 represent four-transistor splitter cells (identical to the ones

shown in the figure) which have been omitted from the schematic because of space constraints.

There are 9 splitter cells in the implemented circuit. In our design, the resistor value was selected

to give a current of 10 A as input to the splitter chain. In the splitter chain schematic,A has a

value of 75,B has a value of 10, and Chas a value of 9. These ratios divide the current down by

a factor of 10 at each splitter cell. These sizes reflect the sizing used in the first revision, a second

revision was created using different sizes for the splitter cells. Further discussion on the two

revisions will be provided in the following section.

4.3 Simulation ResultsSimulations were performed on the current reference circuit before fabricating a test chip.

The simulations showed the dividing characteristics of the splitter cells working properly for

higher current levels, but in splitter cells with currents below 1 nA, the current dividing was not


48/98

35

simulated properly. Simulations were also carried out for changing power supply voltages, and

from these simulations it was seen that the minimum power supply voltage was around 4 V. The

first revision was designed to have a dividing ratio of 10. A behavior that was observed in

simulation is shown in Figure 18. For splitter cells with larger currents, the current ramped up to

its final value at the minimum operating voltage of about 4 V, and then remained there or

increased gradually. For the cells with smaller currents, as shown in Figure 18 for splitter cell 5,

the current ramped up to a maximum at 4 V, and then declined rapidly for increasing power

supply ratios. It is not known why this occurred.

After acquiring experimental results for the first revision, a second revision was created

with a dividing ratio of 2. This was done to correct a change of the dividing ratio with successive

splitter cells, which will be discussed more fully in the next section on experimental results.

Simulations on this circuit revealed that the strange behavior of the low current cells with

3 4 5 6 7 8 9 101

2

3

4

5

6

7x 10

-10

Vdd

(V)

Idfor

Sp

litter

Ce

ll5(A)

Figure 18: Simulated current in splitter cell 5 with varying Vdd (revision 1)


49/98

36

increasing power supply voltages was less pronounced. The current in splitter cell 12 of the

second revision is shown in Figure 19 (this cell has the same current level as cell 5 of the first

revision).

4.4 Experimental ResultsA photograph of the test chip with the current reference is shown in Figure 20. The

current reference is contained within the white rectangle denoted by the vertical arrow. The

layout is essentially the same for revisions 1 and 2, the only change is to the size of the transistors

in the splitter cells, and the number of splitter cells. One change included in the second revision

was additional current mirroring transistors to amplify the currents in the last splitter cells. This

increased the current levels, and made the measurements less susceptible to noise.

3 4 5 6 7 8 9 100.7

0.8

0.9

1

1.1

1.2

1.3x 10

-9

Vdd

(V)

Idfor

Sp

litter

Ce

ll12(A)

Figure 19: Simulated current in splitter cell 12 with changing Vdd (revision 2)


50/98

37

Figure 20: Current reference test chip photograph (layout of current reference is containedin the white box in the lower left hand corner)

As mentioned in the previous section, a problem observed with the first revision was that

the dividing ratio increased from the desired 0.1 with each successive splitter cell. This trend is

shown in Figure 21, which plots the ratios of currents in successive splitter cells. It can be seen

that the ratio of currents in consecutive splitter increases with higher order splitter cells. The

different curves represent measurements taken from each of the five test chips received for the

first revision. It is thought that this is an effect of theA andB sized transistors in the splitter cells

not having the same dimensions, and this was confirmed by the second revision, where the A and

B transistors were sized the same (giving a splitting factor of 2), and this effect was not seen.


51/98

38

1 2 3 4 5 6 70.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Splitter Cell #

Ratioo

fCurren

tsinConsecu

tive

Ce

lls

test chip 5test chip 4test chip 3test chip 2

test chip 1

Figure 21: Measured ratios of currents in consecutive splitter cells (revision 1)

Figure 22 plots the strange behavior of higher order splitter cells that was observed in the

simulation. The plot shows the current in splitter cell 5 with changing power supply voltage (the

same cell that was displayed for the simulation results). The effect in the experimental results

was the same as observed for the simulations, and it was increasingly noticeable for higher order

cells.

Figure 23 plots the current in splitter cell 12 of the second revision for changing power

supply voltage. This is the same cell that was plotted for the simulation results. It is seen from

this plot that the minimum operating voltage is approximately 4 V. Comparing this plot to Figure

22 for the first revision reveals that the effect of the current dropping off for higher supply

voltages is greatly improved in the second revision.


52/98

39

3 4 5 6 7 8 9 102

3

4

5

6

7

8

9

10

11

12x 10

-10

Vdd

(V)

Ou

tpu

tCurren

t(A)

Figure 22: Measured current in splitter cell 5 (revision 1)

3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3x 10

-9

Vdd

(V)

Ou

tpu

tCurren

t(A)

Figure 23: Measured current in splitter cell 12 (revision 2)


53/98

40

Figure 24 plots the base 2 logarithm of the currents in the splitter cells of the second

revision with changing Vdd. From the plot it can be seen that the curves are evenly spaced,

meaning that the dividing ration remains at around 0.5, and that the current levels do not drop off

significantly with increasing power supply voltages. The currents in the splitter cells range from

7.3 A down to 2.2 pA.

Figure 25 plots the ratios of the currents in consecutive splitter cells for the second

revision. It is seen here that the ratio remains at approximately 0.5 for all of the splitter cells, as

demonstrated by the linear fit to the data. This is seen as in improvement when contrasted with

the data in Figure 21, where the dividing ratio steadily increased from 0.1 with successive cells.

3 4 5 6 7 8 9 10-45

-40

-35

-30

-25

-20

-15

Vdd

(V)

log

2(I

d)(A)

Figure 24: Measured current in splitter cells (revision 2), currents range from 7 A to 2 pA


54/98

41

0 2 4 6 8 10 12 14 16 18 20 220

0.1

0.2

0.3

0.4

0.5

Splitter Cell #

Ra

tioo

fCurren

tsinConsecu

tive

Ce

lls

measured datalinear fit

Figure 25: Measured ratios of currents in consecutive splitter cells (revision 2)


55/98

5. FULLY DIFFERENTIAL LOW-NOISE AMPLIFIERAmplifiers are the most critical component of the FIRS integrated circuitry, for several

reasons. From a noise standpoint, the signals being amplified have magnitudes on the order of

tens to hundreds of microvolts [1]. After the initial amplification, the signals will be at least two

orders of magnitude higher, so any noise injected by the remaining signal processing circuitry

will have much less significance. From a power and size perspective, a 100 channel recording

system would require 100 amplifiers (one for each channel), but only one MUX, transmitter, and

set of reference circuitry, so the bulk of the area and power consumption on the chip will be due

to the amplifiers. This makes the optimization of power consumption and layout size particularly

critical for the amplifier circuit.

5.1 Requirements for Low-Noise Biosignal AmplifiersThe first requirement for the amplifier is that it must have a very low intrinsic noise level.

The amplifiers add noise to the signal through thermal noise and 1/f noise sources in the

transistors. Since the signals being amplified are on the order of microvolts, the noise added by

the amplifier must be minimized to avoid overwhelming the signals to be amplified. In addition

to the noise sources intrinsic to the transistors, we must also consider interference noise from the

digital circuitry on the chip (i.e., the multiplexer). Switching transients can be coupled into the

analog circuitry through parasitic capacitances in the substrate or between interconnects. This

type of noise can be minimized through a fully differential architecture. The standard

requirement for noise is that the input referred noise level of the amplifier be less than the typical

extracellular neural background noise of 5-10 Vrms [45].


56/98

43

The next requirements relate to the area and power consumption of the amplifier. The

area of the amplifier must be minimized in order to minimize the overall size of the FIRS. This

will minimize trauma caused by the implant. Power dissipation is important because a heat flux

of 80 mW/cm2 can cause necrosis in muscle tissue [1], so the power consumption of a FIRS

should be kept below a level determined by this requirement for a given implant size. Low power

and low noise requirements are difficult to achieve simultaneously, since noise levels are

generally reduced as the power consumption of an amplifier is increased. For this reason, these

types of designs are often a compromise to trade off acceptable power and noise levels.

Another important requirement for bio-signal amplifiers is that they must be able to reject

large DC offsets. The open-circuit dc potential between a buffered saline electrolyte and a gold

electrode can be as high as +/- 50 mV [15], which would saturate the amplifier outputs if DC

signals were passed. Several methods have been used to accomplish this which will be discussed

in the next section.

The final requirement for the amplifier circuit relates to the cutoff frequency. Typical

neural action potentials have energy in the range from 100 Hz to 7 kHz [1], while local field

potentials can contain signal energy below 1 Hz [46]. For these reasons, the amplifier should

have a low frequency cutoff below 1 Hz, and a high frequency cutoff around 7 kHz. The low

frequency cutoff rejects the DC offsets at the electrode interface, and the high frequency cutoff

prevents unnecessary noise from being included in the output signal.

5.2 Implementations of Low Noise AmplifiersMany implementations of single-ended low noise amplifiers (LNAs) for biomedical

applications have been reported in literature ([1], [12], [13], [16]-[20], [45]-[49]). All of the

designs attempt to meet the requirements listed above, with varying degrees of success. A useful

way of comparing amplifier designs is with a noise efficiency factor (NEF) introduced in [48].

The NEF of a system is defined as


57/98

44

BWkTU

IVNEF

T

tot

inrms

=

4

2,

(1)

where Vrms,in is the total equivalent input-referred noise, BW is the bandwidth of the

system in Hz,Itot is the total current consumed, and UT is the thermal voltage. The ideal case is a

single bipolar transistor, which has a NEF of 1. All practical designs will have a higher NEF than

one. The NEF quantifies the

Date post:	07-Apr-2018
Category:	Documents
Upload:	karthiksmart
View:	223 times
Download:	0 times

Electrical Com Design

Documents