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Electrical Overstress (EOS)An Introduction to Electrically Induced Physical Damage

25 Mar 2019 | Stevan Hunter, Ashok Alagappan

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Copyright of DfR Solutions 2019

Agenda

Outline

02

Damage from EOS

EOS Overview01

06 EOS Mitigation

03

Types of Electrical Stress

04Causes of EOS

05Failure Mechanisms from EOS

2

Summary07



EOS Overview

3



Overview of Returned Semiconductor Units

• EOS ranks highest in the failure Pareto

• Accounts for most of the electrical failures from factories and field environment

• Semiconductor manufacturers report an average of 50% of all returns are for EOS− Electrically induced physical damage (EIPD) is observed

4

Ref: JEP174 Understanding EOS, 2016



Types of Electrical Stress

• EOS (Electrical Over Stress)

− Voltage beyond tolerance (Absolute Maximum Rating) resulting in a physical damage

• ESD (Electrostatic Discharge)

− Short event with very high intense energy dissipated into a chip which may result in physical damage

• Aging

− Degradation or drift in performance of the device over time

− Transistor degradation phenomenon such as Hot Carrier (HCI), Bias Temperature Instability (BTI)

• Wearout

− Stress induced break down of materials and structures

− Electromigration (EM) and Dielectric breakdown (TDDB) are wearout failure mechanisms

• Aging and wearout mechanisms are accelerated by thermal effects as well

5



What is EOS?

• An electrical device suffers electrical overstress when a maximum limit for either the voltage across, the current through, or the power dissipated in the device is exceeded

• EOS is a quantity of energy sufficient to cause permanent damage to an electrical structure, device, or system

− Physical damage may be catastrophic, causing immediate failure,

− or may be latent, resulting in an unpredictable reduction in product lifetime

• Short or long duration, minimal or extreme, random or periodic, transient or continuous, powered or unpowered

• Local stress from high current typically causes thermal runaway

− Electro-thermal damage

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ref JEDEC



ESD is a Subset of Electrical Overstress

• HBM (Human Body Model)

− Charged person contacts ESDS

− Lowest “withstand Voltage” on data sheet

• CDM (Charged Device Model)

− Device charged, then metal-to-metal contact

− Lowest “withstand Voltage” on data sheet

− Larger packages worse: high capacitance

• CBE (Charged Board Event)

− Substrate or printed wiring board charged, metal-to-metal contact

− Board capacitance can be very large

− Can be high energy, cause much damage

• CDE (Cable Discharge Event)

− Charged insulated cable, metal-to-metal contact

− Can be high energy

• HMM (Human-Metal Model)

− System-level human contact

Types of ESD

7

Static charge can build up through triboelectric activity, or as charge separation due to electric field



EOS and ESD

− Electrical Overstress

− For example: Lower voltage (<100v) and large peak current (>10A) that may occur over longer time frame (>1ms)

− EOS is a sufficient “quantity” of electrical stress to cause damage in a semiconductor device

− Causes quality issue in device

− May result in failure, now or later

• EIPD

− Electrically Induced Physical Damage

− Physical result of EOS

− May be observed on “Customer Returns”

− Electrically damaged items should be called EIPD! (not EOS or ESD)

− Electrostatic Discharge

− For example: Very High voltage(>500v), moderate peak current(~1 to 10A), occurring in short time(<1us)

− Rapid transfer of charge between objects

− Charge that was immobile suddenly moves

− Random ESD is happening all the time, all around us – usually OK

− ESD is a type of EOS

• ESDS

− “ESD Sensitive” items

− CMOS semiconductor devices are examples of ESDS

− Special effort required to protect ESDS

EOS ESD

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Damage from EOS

9



How Do We Know It’s EOS?

1. Electrical characterization can verify functionality or failure

2. If electrical failure, then physical Failure Analysis

− Microscope inspection, X-ray, deprocessing, polish cross section, FIB, SEM, EDX

3. EIPD, electrically induced physical damage is observed

− Materials changed due to high local stress

− i.e. burned films or package, melted metal lines, wire bond fused open, cracks, voids, dielectric damage, diffusion

4. Conclude that EOS caused the observed EIPD

− Damaged device due to electrical/thermal stress

− Root cause, how and what EOS, undetermined

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• Root Cause?

− HBM, CDM, CDE, CBE, HMM, Mis-handling, Hot Plug, poor Gnd, EMI, other EOS

− See ESD SP27 for recommendations on root cause discovery

11

Similar device, but

different EOS energy

Wire burned, and massive

junction damage

Metal melted, “fused” open

Similar products, one has corner damage, other

has edge and backside damage

Failure Analysis: EIPD, Causes Unknown



Electrical Overstress?

• What does EOS exceed?

− Physical limits of materials in localized region

− Limits specified by:

• Absolute Maximum Rating (AMR)

− AMR is the maximum stress that may be applied to a device, beyond which damage (latent or otherwise) may occur

− AMR can refer to voltage, current, temperature and any other operating parameter

− AMRs are determined by the semiconductor manufacturer

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Electrical Overstress: Exceeds AMR

• Many possible failure mechanisms

− Customer should not assume it’s OK to exceed AMR under any conditions

Walking wounded,

unpredictable

unreliability

Lifetime

shortens

Figure from JEP174

• Yellow line is probability of immediate device failure

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Product Datasheet

• Data sheet provides essential information on how to properly use the semiconductor product. Typical AMR’s include but not limited to:

− Maximum operating voltage

− Temperature and environment limits

− ESD “withstand voltages”

14

AMR’s are serious. They are not just “guidelines”!



• Ideally, manufacturer would list “true” AMR limits in detail

• Ideally, customer will preserve reliability by preventing EOS, never exceeding “true” AMR

• In reality, no ideal case exists

• Manufacturer lists AMR in a conservative and practical manner

• Customer can confidently preserve reliability by preventing EOS

− Never allow a condition above AMR, even for a brief time!

Practical EOS summary

15



Causes of EOS

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From 2013 survey by Industry Council on ESD Targets

1. Misapplication EOS

− Powered handling:

› Unintended overvoltage, power supply sequencing, poor insertion, incorrect biasing, noise on ground line, …

2. Absolute Maximum Rating EOS

− Applied V exceeds published AMR

3. ESD-related EOS

− Charged Board Events (CBE)

− Cable Discharge Events (CDE)

− Insufficient attention to ESD controls (ANSI-ESD S20.20)

4. Miscellaneous Causes of EOS

− …Everything from weak PCB design to mishandling

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Top 4 Reported EOS Root Causes

17



EOS Root Causes

18

• Non-exhaustive overview of

root causes

• Grouped in 3 categories

• Powered Handling

• Switching/AC Operation

• Unpowered handling



Where Can EOS Occur in the Supply Chain?

19

Fab Assembly Test DistributorTier 1

Customer

OEM

Customer

Semiconductor Manufacturer supply chain

(ESD) ESD ESD,

EOS

ESD ESD EOS

EMI

ESD EOS

EMI

Board-level System-level

HBMHBM,

CDM

CDM,

Mis-handling

EOS spikes

Protected while shipping

CDM, CBE

Mis-handling

EOS spikes

Hot Plug

Powered Handling

Power Sequence

High Fields. …

CBE, CDE,

Mis-handling

EOS spikes

Hot Plug

Powered Handling

Power Sequence

High Fields, …



Failure Mechanisms from EOS

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1. Thin dielectric breakdown

− Voltage (electric field) too high for the film

2. Current-driven thermal runaway

− Causes diffusion, melting, cracks, voiding, filaments, loss of adhesion, …

− Physical damage to:

› Semiconductor junction

› Thin film

› Bulk material

› Metal (including metal traces, bond wires, solder)

› Interface

3. Transistor latch-up

− Can cause current-driven thermal runaway

“Weak link” will fail first, then further damage may occur

Failure Mechanisms for EOS

21



Dielectric- - - - - - - - - - - - - - - - - - - - - - -

+ + + + + + + + + + + + + + + + + + + + + + +

• Overstressing the dielectric will exceed its breakdown voltage, VB, causing

current to flow in a microscopic location

• Thermal runaway, damaging semiconductor and dielectric materials

• Permanent damage to the dielectric: current leakage path or short

Thin Film Capacitor

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Semiconductor Junction Diode (cross section)

• If electrically overstressed, failure is expected at a materials interface or in ametal

• Structure can be damaged in multiple ways:

• A fast rise time high V event is likely to damage the pn-junction

• High current flow in a microscopic spot causing very high temperature

23

p-

type+

V

-

e- ine- out

e- (electrons) and

p+ (holes)

n-

type

Metal interconnect



(Wirebond, or add metal layers

for Cu pillar or solder bumps)

Dielectric

Metal

Metal

Metal

W

Si

Pad

Opening

Metal Silicide

• Overstressing interconnects causes high current flow, accelerating EM or melting,

leading to voids, filament formation and fusing open

Interconnect in the IC

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Gate Oxide

Gate electrode

Metal MetalMetal

Si

SiO2

Channel

• Overstressing the Gate Oxide exceeds its breakdown voltage, VB, causing current

to flow in dielectric, and permanent damage to the dielectric and conductors

• Overstressing Drain or Source causes high current flow (junction damage) and

damaging charge injection into the gate oxide

• Latchup can occur in EOS high V or I, causing thermal runaway

MOSFET Cross-section

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EOS Mitigation

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1) Manufacturer: Realistic, thorough specifications of AMR

− EOS is prevented during manufacturing and shipping

2) Customer: Understand AMR, prevent EOS

− Preserve reliability of the semiconductor product (JEP174, ESD S20.20)

3) Learn from past EOS mistakes

− Find and correct the root cause event(s) which created damage

− Customer and manufacturer communicate well and collaborate to find root cause (ESD SP27)

4) Continuous improvement in the industry by sharing of learning

Crucial topic: communication between customer and manufacturer

EOS Mitigation

27



Technology Scaling

• Emerging technology advances will reduce breakdown voltages and

continue to shrink design windows:

• AMR values expected to lower

• EOS damage and customer returns expected to increase unless

improved EOS prevention

EOS Concerns Increasing For Future Products

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SUMMARY

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• Electrical Overstress (EOS) causes physical damage in semiconductor structures (EIPD)

• Manufacturer provides limits, for component reliability

− AMRs, including HBM ESD and CDM ESD withstand voltages

− AMRs alert customers to operate product only within the limits, to preserve reliability

› AMR value is based on the weak link or least tolerant failure mechanism(s) for the product

• Customer is responsible for designing and operating within datasheet limits to preserve reliability of each component

− Many different failure mechanisms can result from EOS

− Latent damage from EOS is not detectable, but reliability is jeopardized: unpredictable unreliability

− EOS can occur in many ways, so constant diligence is required in prevention

− ESD is one form of EOS

• In case of suspected EOS causing failures, user must diligently seek the root cause

− Requires collaborative effort between customer and manufacturer to find and eliminate root cause

EOS and EIPD Summary

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Speaker Bio

Stevan Hunter, PhD, Reliability Engineering Consultant, ESD Control

Champion, and a Lean Six Sigma Instructor at ON Semiconductor Stevan Hunter, PhD, is Reliability Engineering Consultant with 40 years of experience in

Semiconductor engineering. He is company representative to EOS/ESD Association and

Industry Council and participates in committees of JEDEC Solid State Electronics

Reliability group. He enjoys conducting collaborative university research projects, and

teaches and advises as Faculty Associate at Arizona State University, BYU-Idaho and

University of Maryland CALCE. He is a Senior Member of IEEE and ASQ, and member

of IMAPS, AVS, ASEE and ATD.

208-317-4633

[email protected]

[email protected]

Ashok Alagappan, Senior Member, Technical Staff, DfR

Solutions

Ashok has 15 years of experience in Semiconductor design and manufacturing,

managing products through a range of activities from design to qualification. He

has worked with customers in a variety of high reliability applications from

aerospace to telecommunications to provide expert analysis and

recommendations for defining and improving reliability of electronics products

and IC components. He has developed tools to predict the lifetime of IC

components due to intrinsic wearout failure mechanisms, which are currently

implemented in Sherlock.

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