Red box Rules aRe foR pRoof stage only. delete befoRe final pRinting.

Electrical Overstress (EOS)D E V I C E S , C I R C U I T S A N D S Y S T E M S

Electrical Overstress (EOS)D E V I C E S , C I R C U I T S A N D S Y S T E M S

S T E V E N H . V O L D M A N

Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.

Look inside for extensive coverage on:

Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena

EOS sources in today’s semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures

EOS failures in both semiconductor devices, circuits and systems Discussion of how to distinguish between EOS events and electrostatic discharge (ESD) events, such as the human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events

EOS protection on-chip design practices and how they differ from ESD protection networks and solutions Discussion of EOS system level concerns in printed circuit boards (PCB) and manufacturing equipment Examples of EOS issues in state-of-the-art digital, analog and power technologies, including CMOS, LDMOS, and BCD

EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems

EOS testing and qualification techniques Practical off-chip ESD protection and system level solutions to provide more robust systems

Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This book teaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today’s modern world.

S T E V E N H . V O L D M A N , IEEE Fellow, Vermont, USA

V O L D M A N

Electrical Overstress (EO

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ELECTRICAL OVERSTRESS (EOS)

ESD SeriesBy Steven H. Voldman

Electrical Overstress (EOS): Devices, Circuits and SystemsISBN: 9781118511886

September 2013

ESD Basics: From Semiconductor Manufacturing to Product UseISBN: 9780470979716

October 2012

ESD: Design and SynthesisISBN: 9780470685716

March 2011

ESD: Failure Mechanisms and ModelsISBN: 9780470511374

July 2009

LatchupISBN: 9780470016428

December 2007

ESD: RF Technology and CircuitsISBN: 9780470847558

September 2006

ESD: Circuits and DevicesISBN: 9780470847541

November 2005

ESD: Physics and DevicesISBN: 9780470847534

September 2004

Upcoming titles:

ESD: Test and Characterization

The ESD Handbook

ESD: Analog Circuits and Design

ELECTRICAL OVERSTRESS (EOS)Devices, Circuits and Systems

Steven H. VoldmanIEEE Fellow, Vermont, USA

This edition first published 2014# 2014 John Wiley & Sons, Ltd

Registered officeJohn Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom

For details of our global editorial offices, for customer services and for information about how to apply forpermission to reuse the copyright material in this book please see our website at www.wiley.com.

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Library of Congress Cataloging-in-Publication Data

Voldman, Steven H.Electrical overstress (EOS) : devices, circuits, and systems / Steven Voldman.

pages cmIncludes bibliographical references and index.ISBN 978-1-118-51188-6 (hardback)1. Semiconductors—Failures. 2. Semiconductors—Protection. 3. Transients (Electricity) 4. Overvoltage.I. Title.TK7871.852.V648 2013621.3815—dc23

2013022183

A catalogue record for this book is available from the British Library.

ISBN: 978-1-118-51188-6

Set in 10/12pt Times by Thomson Digital, Noida, India.

1 2014

To My Mother’s Sister

My Aunt

Saundra “Sunny” Braitman

Contents

About the Author xvii

Preface xix

Acknowledgements xxiii

1 Fundamentals of Electrical Overstress 11.1 Electrical Overstress 2

1.1.1 The Cost of Electrical Overstress 21.1.2 Product Field Returns – The Percentage that is Electrical

Overstress 21.1.3 Product Field Returns – No Defect Found versus Electrical

Overstress 41.1.4 Product Failures – Failures in Integrated Circuits 41.1.5 Classification of Electrical Overstress Events 41.1.6 Electrical Over-Current 61.1.7 Electrical Over-Voltage 61.1.8 Electrical Over-Power 7

1.2 De-Mystifying Electrical Overstress 71.2.1 Electrical Overstress Events 8

1.3 Sources of Electrical Overstress 81.3.1 Sources of Electrical Overstress in Manufacturing

Environment 81.3.2 Sources of Electrical Overstress in Production

Environments 101.4 Misconceptions of Electrical Overstress 101.5 Minimization of Electrical Overstress Sources 111.6 Mitigation of Electrical Overstress 111.7 Signs of Electrical Overstress Damage 12

1.7.1 Signs of Electrical Overstress Damage – The ElectricalSignature 12

1.7.2 Signs of Electrical Overstress Damage – The VisualSignature 13

1.8 Electrical Overstress and Electrostatic Discharge 141.8.1 Comparison of High and Low Current EOS versus ESD Events 151.8.2 Electrical Overstress and Electrostatic Discharge Differences 151.8.3 Electrical Overstress and Electrostatic Discharge Similarities 171.8.4 Comparison of EOS versus ESDWaveforms 181.8.5 Comparison of EOS versus ESD Event Failure Damage 19

1.9 Electromagnetic Interference 201.9.1 Electrical Overstress Induced Electromagnetic Interference 20

1.10 Electromagnetic Compatibility 211.11 Thermal Over-Stress 21

1.11.1 Electrical Overstress and Thermal Overstress 221.11.2 Temperature Dependent Electrical Overstress 221.11.3 Electrical Overstress and Melting Temperature 23

1.12 Reliability Technology Scaling 231.12.1 Reliability Technology Scaling and the Reliability Bathtub

Curve 231.12.2 The Shrinking Reliability Design Box 241.12.3 The Shrinking Electrostatic Discharge Design Box 251.12.4 Application Voltage, Trigger Voltage, and Absolute

Maximum Voltage 251.13 Safe Operating Area 26

1.13.1 Electrical Safe Operating Area 261.13.2 Thermal Safe Operating Area 271.13.3 Transient Safe Operating Area 28

1.14 Summary and Closing Comments 28References 29

2 Fundamentals of EOS Models 362.1 Thermal Time Constants 36

2.1.1 The Thermal Diffusion Time 372.1.2 The Adiabatic Regime Time Constant 382.1.3 The Thermal Diffusion Regime Time Constant 382.1.4 The Steady State Regime Time Constant 39

2.2 Pulse Event Time Constants 392.2.1 The ESD HBM Pulse Time Constant 392.2.2 The ESD MM Pulse Time Constant 392.2.3 The ESD Charged Device Model Pulse Time Constant 402.2.4 The ESD Pulse Time Constant – Transmission Line Pulse 402.2.5 The ESD Pulse Time Constant – Very Fast Transmission

Line Pulse 412.2.6 The IEC 61000-4-2 Pulse Time Constant 412.2.7 The Cable Discharge Event Pulse Time Constant 42

viii CONTENTS

2.2.8 The IEC 61000-4-5 Pulse Time Constant 422.3 Mathematical Methods for EOS 42

2.3.1 Mathematical Methods for EOS – Green’s Functions 422.3.2 Mathematical Methods for EOS – Method of Images 452.3.3 Mathematical Methods for EOS – Thermal Diffusion Partial

Differential Equation 472.3.4 Mathematical Methods for EOS – Thermal Diffusion Partial

Differential Equation with Variable Coefficients 482.3.5 Mathematical Methods for EOS – Duhamel Formulation 482.3.6 Mathematical Methods for EOS – Integral Transforms

of the Heat Conduction Equation 532.4 The Spherical Model – Tasca Derivation 57

2.4.1 The Tasca Model in the ESD Time Regime 612.4.2 The Tasca Model in the EOS Time Regime 612.4.3 The Vlasov–Sinkevitch Model 62

2.5 The One-dimensional Model – Wunsch–Bell Derivation 622.5.1 The Wunsch–Bell Curve 662.5.2 The Wunsch–Bell Model in the ESD Time Regime 662.5.3 The Wunsch–Bell Model in the EOS Time Regime 67

2.6 The Ash Model 682.7 The Cylindrical Model – The Arkihpov–Astvatsaturyan–

Godovosyn–Rudenko Derivation 682.8 The Three-dimensional Parallelepiped Model – Dwyer–

Franklin–Campbell Derivation 692.8.1 The Dwyer–Franklin–Campbell Model in the ESD

Time Regime 752.8.2 The Dwyer–Campbell–Franklin Model in the EOS

Time Regime 752.9 The Resistor Model – Smith–Littau Derivation 762.10 Instability 79

2.10.1 Electrical Instability 792.10.2 Electrical Breakdown 802.10.3 Electrical Instability and Snapback 802.10.4 Thermal Instability 81

2.11 Electro-migration and Electrical Overstress 842.12 Summary and Closing Comments 84References 85

3 EOS, ESD, EMI, EMC and Latchup 873.1 Electrical Overstress Sources 87

3.1.1 EOS Sources – Lightning 883.1.2 EOS Sources – Power Distribution 903.1.3 EOS Sources – Switches, Relays, and Coils 903.1.4 EOS Sources – Switch Mode Power Supplies 90

CONTENTS ix

3.1.5 EOS Sources – Machinery 903.1.6 EOS Sources – Actuators 913.1.7 EOS Sources – Solenoids 913.1.8 EOS Sources – Servo Motors 913.1.9 EOS Sources – Variable Frequency Drive Motors 933.1.10 EOS Sources – Cables 93

3.2 EOS Failure Mechanisms 943.2.1 EOS Failure Mechanisms: Semiconductor

Process – Application Mismatch 953.2.2 EOS Failure Mechanisms: Bond Wire Failure 953.2.3 EOS Failure Mechanisms: PCB to Chip Failures 963.2.4 EOS Failure Mechanisms: External Load to Chip Failures 963.2.5 EOS Failure Mechanisms: Reverse Insertion Failures 97

3.3 Failure Mechanism – Latchup or EOS? 973.3.1 Latchup versus EOS Design Window 98

3.4 Failure Mechanism – Charged Board Model or EOS? 983.5 Summary and Closing Comments 99References 99

4 EOS Failure Analysis 1024.1 Electrical Overstress Failure Analysis 102

4.1.1 EOS Failure Analysis – Information Gatheringand Fact Finding 106

4.1.2 EOS Failure Analysis – Failure Analysis Report andDocumentation 106

4.1.3 EOS Failure Analysis – Failure Site Localization 1084.1.4 EOS Failure Analysis – Root Cause Analysis 1084.1.5 EOS or ESD Failure Analysis – Can Visual Failure

Analysis Tell the Difference? 1084.2 EOS Failure Analysis – Choosing the Correct Tool 112

4.2.1 EOS Failure Analysis – Non-Destructive Methods 1134.2.2 EOS Failure Analysis – Destructive Methods 1154.2.3 EOS Failure Analysis – Differential Scanning Calorimetry 1154.2.4 EOS Failure Analysis – Scanning Electron Microscope/Energy

Dispersive X-ray Spectroscopy 1164.2.5 EOS Failure Analysis – Fourier Transform Infrared

Spectroscopy 1164.2.6 EOS Failure Analysis – Ion Chromatography 1174.2.7 EOS Failure Analysis – Optical Microscopy 1174.2.8 EOS Failure Analysis – Scanning Electron Microscopy 1184.2.9 EOS Failure Analysis – Transmission Electron Microscopy 1184.2.10 EOS Failure Analysis – Emission Microscope Tool 1204.2.11 EOS Failure Analysis – Voltage Contrast Tools 1204.2.12 EOS Failure Analysis – IR Thermography 121

x CONTENTS

4.2.13 EOS Failure Analysis – Optical Beam Induced ResistanceChange Tool 122

4.2.14 EOS Failure Analysis – IR-OBIRCH Tool 1224.2.15 EOS Failure Analysis – Thermally Induced Voltage

Alteration Tool 1234.2.16 EOS Failure Analysis – Atomic Force Microscope Tool 1244.2.17 EOS Failure Analysis – Super-Conducting Quantum

Interference Device Microscope 1254.2.18 EOS Failure Analysis – Picosecond Imaging Current

Analysis Tool 1274.3 Summary and Closing Comments 129References 130

5 EOS Testing and Simulation 1335.1 Electrostatic Discharge Testing – Component Level 133

5.1.1 ESD Testing – Human Body Model 1345.1.2 ESD Testing – Machine Model 1365.1.3 ESD Testing – Charged Device Model 138

5.2 Transmission Line Pulse Testing 1405.2.1 ESD Testing – Transmission Line Pulse 1405.2.2 ESD Testing – Very Fast Transmission Line Pulse 142

5.3 ESD Testing – System Level 1435.3.1 ESD System Level Testing – IEC 61000-4-2 1435.3.2 ESD Testing – Human Metal Model 1445.3.3 ESD Testing – Charged Board Model 1455.3.4 ESD Testing – Cable Discharge Event 146

5.4 Electrical Overstress Testing 1485.4.1 EOS Testing – Component Level 1495.4.2 EOS Testing – System Level 149

5.5 EOS Testing – Lightning 1495.6 EOS Testing – IEC 61000-4-5 1505.7 EOS Testing – Transmission Line Pulse Method and EOS 151

5.7.1 EOS Testing – Long Pulse TLP Method 1525.7.2 EOS Testing – TLP Method, EOS and the Wunsch–Bell

Model 1525.7.3 EOS Testing – Limitations of the TLP Method for the

Evaluation of EOS for Systems 1525.7.4 EOS Testing – Electro-magnetic Pulse 153

5.8 EOS Testing – D.C. and Transient Latchup 1535.9 EOS Testing – Scanning Methodologies 154

5.9.1 EOS Testing – Susceptibility and Vulnerability 1545.9.2 EOS Testing – Electrostatic Discharge/Electromagnetic

Compatibility Scanning 1555.9.3 Electromagnetic Interference Emission Scanning Methodology 157

CONTENTS xi

5.9.4 Radio Frequency Immunity Scanning Methodology 1585.9.5 Resonance Scanning Methodology 1585.9.6 Current Spreading Scanning Methodology 158

5.10 Summary and Closing Comments 161References 161

6 EOS Robustness – Semiconductor Technologies 1666.1 EOS and CMOS Technology 166

6.1.1 CMOS Technology – Structures 1666.1.2 CMOS Technology – Safe Operation Area 1676.1.3 CMOS Technology – EOS and ESD Failure Mechanisms 1686.1.4 CMOS Technology – Protection Circuits 1736.1.5 CMOS Technology – Silicon On Insulator 1786.1.6 CMOS Technology – Latchup 179

6.2 EOS and RF CMOS and Bipolar Technology 1806.2.1 RF CMOS and Bipolar Technology – Structures 1806.2.2 RF CMOS and Bipolar Technology – Safe Operation Area 1816.2.3 RF CMOS and Bipolar Technology – EOS and ESD Failure

Mechanisms 1826.2.4 RF CMOS and Bipolar Technology – Protection Circuits 185

6.3 EOS and LDMOS Power Technology 1866.3.1 LDMOS Technology – Structures 1876.3.2 LDMOS Transistors – ESD Electrical Measurements 1896.3.3 LDMOS Technology – Safe Operation Area 1906.3.4 LDMOS Technology – Failure Mechanisms 1916.3.5 LDMOS Technology – Protection Circuits 1936.3.6 LDMOS Technology – Latchup 193

6.4 Summary and Closing Comments 194References 195

7 EOS Design – Chip Level Design and Floor Planning 1967.1 EOS and ESD Co-Synthesis – How to Design for Both EOS and ESD 1967.2 Product Definition Flow and Technology Evaluation 197

7.2.1 Standard Product Definition Flow 1977.2.2 EOS Product Design Flow and Product Definition 198

7.3 EOS Product Definition Flow – Constant Reliability Scaling 1997.4 EOS Product Definition Flow – Bottom Up Design 2007.5 EOS Product Definition Flow – Top Down Design 2007.6 On-Chip EOS Considerations – Bond Pad and Bond Wire Design 2027.7 EOS Peripheral I/O Floor Planning 202

7.7.1 EOS Peripheral I/O Floor Planning – VDD-to-VSS PowerClamp Placement in Corners 203

7.7.2 EOS Peripheral I/O Floor Planning – Distributed PowerClamp Placement 204

xii CONTENTS

7.7.3 EOS Peripheral I/O Floor Planning – Multi-DomainSemiconductor Chips 205

7.8 EOS Chip Power Grid Design – IEC Specification Power Grid andInterconnect Design Considerations 2067.8.1 IEC 61000-4-2 Power Grid 2077.8.2 ESD Power Clamp Design Synthesis – IEC 61000-4-2

Responsive ESD Power Clamps 2077.9 Printed Circuit Board Design 209

7.9.1 System Level Board Design – Ground Design 2097.9.2 System Card Insertion Contacts 2097.9.3 Component and EOS Protection Device Placement 210

7.10 Summary and Closing Comments 211References 211

8 EOS Design – Chip Level Circuit Design 2138.1 EOS Protection Devices 2138.2 EOS Protection Device Classification Characteristics 213

8.2.1 EOS Protection Device Classification – VoltageSuppression 214

8.2.2 EOS Protection Device – Current-Limiting Devices 2158.3 EOS Protection Device – Directionality 216

8.3.1 EOS Protection Device – Uni-Directional 2168.3.2 EOS Protection Device – Bi-Directional 217

8.4 EOS Protection Device Classification – I-V Characteristic Type 2178.4.1 EOS Protection Device Classification – Positive

Resistance I-V Characteristic Type 2188.4.2 EOS Protection Device Classification – S-Type I-V

Characteristic Type 2198.5 EOS Protection Device Design Window 220

8.5.1 EOS Protection Device versus ESD Device Design Window 2208.5.2 EOS and ESD Co-Synthesis 2218.5.3 EOS Activates ESD Circuitry 221

8.6 EOS Protection Device – Types of Voltage Suppression Devices 2228.6.1 EOS Protection Device – TVS Device 2228.6.2 EOS Protection Device – Diodes 2228.6.3 EOS Protection Device – Schottky Diodes 2238.6.4 EOS Protection Device – Zener Diodes 2238.6.5 EOS Protection Device – Thyristor Surge Protection Device 2248.6.6 EOS Protection Device – Metal Oxide Varistors Device 2258.6.7 EOS Protection Device – Gas Discharge Tube Devices 228

8.7 EOS Protection Device – Types of Current-Limiting Devices 2298.7.1 EOS Protection Device – Current-Limiting Devices – PTC

Devices 2308.7.2 EOS Protection Device – Conductive Polymer Devices 231

CONTENTS xiii

8.7.3 EOS Protection Device – Current-Limiting Devices – Fuses 2328.7.4 EOS Protection Device – Current-Limiting Devices – eFuse 2348.7.5 EOS Protection Device – Current-Limiting Devices – Circuit

Breakers 2358.8 EOS Protection – Across Board Supply and Ground Plane Using a

Transient Voltage Suppression Device and Schottky Diodes 2368.9 EOS and ESD Protection Co-Synthesis Network 2378.10 Co-Synthesis of EOS in Cables and PCBs 2378.11 Summary and Closing Comments 239References 239

9 EOS Prevention and Control 2409.1 Controlling EOS 240

9.1.1 Controlling EOS in a Manufacturing Environment 2409.1.2 Controlling EOS in a Production Environment 2419.1.3 Controlling EOS in a Back End Process 242

9.2 EOS Minimization 2429.2.1 EOS Prevention – Manufacturing Area Operation 2449.2.2 EOS Prevention – Production Area Operation 246

9.3 EOS Minimization – Preventive Actions in the Design Process 2469.4 EOS Prevention – EOS Guidelines and Procedures 2469.5 EOS Prevention – Ground Testing 2479.6 EOS Prevention – Connectivity 2479.7 EOS Prevention – Insertion 2479.8 EOS and Electromagnetic Interference Prevention – Printed

Circuit Board Design 2489.8.1 EOS and EMI Prevention – PCB Power Plane and

Ground Design 2489.8.2 EOS and EMI Prevention – PCB Design

Guidelines – Component Selection and Placement 2499.8.3 EOS and EMI Prevention – PCB Design

Guidelines – Trace Routing and Planes 2509.9 EOS Prevention – Desktop Boards 2519.10 EOS Prevention – On-Board and On-Chip Design Solutions 252

9.10.1 EOS Prevention – Operational Amplifier 2529.10.2 EOS Prevention – Low Dropout Regulators 2539.10.3 EOS Prevention – Soft Start Over-current and Over-voltage

Protection Circuitry 2549.10.4 EOS Prevention – Power Supply EOC and EOV Protection 255

9.11 High Performance Serial Buses and EOS 2579.11.1 High Performance Serial Buses – FireWire and EOS 2579.11.2 High Performance Serial Buses – Peripheral Component

Interconnect Express and EOS 2589.11.3 High Performance Serial Buses – Universal Serial Bus and EOS 259

xiv CONTENTS

9.12 Summary and Closing Comments 259References 259

10 EOS Design – Electronic Design Automation 26310.1 EOS and Electronic Design Automation 26310.2 EOS and ESD Design Rule Checking 263

10.2.1 ESD Design Rule Check 26410.2.2 ESD Layout Versus Schematic Verification 26510.2.3 ESD Electrical Rule Check 266

10.3 EOS Electronic Design Automation 26610.3.1 EOS Design Rule Checking 26710.3.2 EOS Layout Versus Schematic Verification 26810.3.3 EOS Electrical Rule Check 26910.3.4 EOS Programmable Electrical Rule Check 270

10.4 Printed Circuit Board Design Checking and Verification 27010.5 EOS and Latchup Design Rule Checking 273

10.5.1 Latchup Design Rule Check 27310.5.2 Latchup Electrical Rule Check 277

10.6 Summary and Closing Comments 282References 282

11 EOS Program Management 28511.1 EOS Audits and Manufacturing Control 28511.2 Controlling EOS in the Production Process 28711.3 EOS and Assembly Plant Corrective Actions 28711.4 EOS Audits – From Manufacturing to Assembly Control 28811.5 EOS Program – Weekly, Monthly, Quarterly, to Annual Audits 28811.6 EOS and ESD Design Release 289

11.6.1 EOS Design Release Process 29011.6.2 ESD Cookbook 29011.6.3 EOS Cookbook 29311.6.4 EOS Checklists 29511.6.5 EOS Design Reviews 297

11.7 EOS Design, Testing and Qualification 29711.8 Summary and Closing Comments 298References 298

12 Electrical Overstress in Future Technologies 30112.1 EOS Future Implications for Future Technologies 30112.2 EOS in Advanced CMOS Technology 302

12.2.1 EOS in FinFET Technology 30312.2.2 EOS and Circuit Design 303

12.3 EOS Implications in 2.5-D and 3-D Systems 30412.3.1 EOS Implications in 2.5-D Systems 305

CONTENTS xv

12.3.2 EOS and Silicon Interposers 30512.3.3 EOS and Through Silicon Vias 30712.3.4 EOS Implications in 3-D Systems 309

12.4 EOS and Magnetic Recording 30912.4.1 EOS and Magneto-Resistors 30912.4.2 EOS and Giant Magneto-Resistors 31112.4.3 EOS and Tunneling Magneto-Resistors 312

12.5 EOS and Micro-Machines 31212.5.1 Micro-Electromechanical Devices 31212.5.2 ESD Concerns in MEM Devices 31312.5.3 Micro-Motors 31412.5.4 ESD Concerns in Micro-Motors 314

12.6 EOS and RF MEMs 31612.7 EOS Implications for Nano-Structures 318

12.7.1 EOS and Phase Change Memory 31812.7.2 EOS and Graphene 32012.7.3 EOS and Carbon Nanotubes 320

12.8 Summary and Closing Comments 322References 322

Appendix A: Glossary of Terms 329

Appendix B: Standards 335

Index 339

xvi CONTENTS

About the Author

Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for“Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon GermaniumTechnology.” He received his B.S. in Engineering Science from University of Buffalo(1979), a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT), a seconddegree EE Degree (Engineer Degree) from MIT, a MS Engineering Physics (1986), and aPh.D in electrical engineering (EE; 1991) from University of Vermont under IBM’s ResidentStudy Fellow program.

He was a member of the IBM development for 25 years, working on semiconductordevice physics, device design, and reliability e.g., soft error rate (SER), hot electrons,leakage mechanisms, latchup, electrostatic discharge (ESD), and electrical overstress(EOS). Voldman has been involved in latchup technology development for 30 years. Heworked on both the technology and product development in Bipolar SRAM, CMOS DRAM,CMOS logic, Silicon on Insulator (SOI), BiCMOS, Silicon Germanium (SiGe), RF CMOS,RF SOI, smart power, and image processing technologies. In 2007, Voldman was a memberof the Qimonda DRAM development team, working on 70, 58, and 48 nm CMOStechnology. In 2008, he initiated a limited liability corporation (LLC), and he worked atheadquarters in Hsinchu, Taiwan, for Taiwan Semiconductor Manufacturing Corporation(TSMC) as part of the 45 nm ESD and latchup development team. He was a Senior PrincipalEngineer working for the Intersil Corporation on ESD and latchup development from 2009 to2011. Since 2011, he is presently independent under Dr. Steven H. Voldman LLC, providingconsulting, teaching, and patent litigation expert witness support. He is presently aconsultant for Samsung Electronics in Dongtan, South Korea, working on sub-20 nmtechnology.

Steve Voldman was chairman of the SEMATECH ESD Working Group from 1995 to2000. In his SEMATECH Working Group, the effort focused on ESD technologybenchmarking, the first transmission line pulse (TLP) standard development team, strategicplanning, and the JEDEC-ESD Association standards harmonization of the human bodymodel (HBM) Standard. From 2000 to 2012, as Chairman of the ESD Association WorkGroup on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the firststandard practice and standards for TLP and VF-TLP. He has been a member of the ESDAssociation Board of Directors, and Education Committee.

Steve Voldman initiated the “ESD on Campus” program which was established to bringESD lectures and interaction to university faculty and students internationally; the ESD onCampus program has reached over 40 universities in the United States, Singapore, Taiwan,Malaysia, Philippines, Thailand, South Korea, India, and China.

He teaches short courses and tutorials on ESD, latchup, patenting, and invention in theUnited States, China, Singapore, Malaysia, Taiwan, Sri Lanka and Israel. He is a recipient ofover 245 issued US patents, in the area of ESD and CMOS latchup.

Since 2007, he has served as an expert witness in patent litigation in over six litigationcases, associated with CMOS development, DRAM development, silicon-on-insulator,semiconductor devices, ESD, and latchup.

Steve Voldman has written articles for Scientific American and is author of the first bookseries on ESD, latchup, and EOS: ESD: Physics and Devices, ESD: Circuits and Devices,ESD: RF Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD:Design and Synthesis, and ESD Basics: From Semiconductor Manufacturing to Product Useand this text, Electrical Overstress (EOS): Devices, Circuits and Systems. He is also acontributor to the books Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, theInternational Chinese editions of the book ESD: Circuits and Devices and ESD: RFTechnology and Circuit are released as well as others in the near future.

xviii ABOUT THE AUTHOR

Preface

This text, Electrical Overstress (EOS): Devices, Circuits and Systems was initiated based onthe need to produce a text that addresses the fundamentals of electrical overstress (EOS)from the manufacturing environment, devices, components and systems. An understandingof the source of EOS, how to identify EOS, and provide EOS robust products are needed intoday’s electronic industry. As the manufacturing world evolves, semiconductor networksscale, and systems are changing, the needs and requirements for reliability and EOS robustproducts are changing. A text is required that connects basic EOS phenomena to today’s realworld environment.

Whereas significant texts are available today to teach experts on electrostatic discharge(ESD) on-chip design, there is a need for a fundamental understanding of EOS. This isnecessary for expert, non-expert, non-technical, and layman to understand the problemsfacing the world today. Today, real world EOS issues surround us; this occurs inmanufacturing environment, power sources, machinery, actuators, solenoids, soldering irons,cables, to lightning. When there is switching, poor grounding, ground loops, noise, andtransient phenomena, there will be a potential for EOS of devices, components, and printedcircuit boards. Hence, there is a need for experts and non-experts to understand what theissues that revolve around us are, and what we do to avoid them.

One of the key problems with this topic is the perception that EOS is difficult to quantifyand define. This perception was also true in the early days of ESD development. As a result,there have been no textbooks on EOS at this date, and yet it is understood that a significantpercentage of system and product field returns is EOS related.

A second key problem is the belief that it is difficult to distinguish ESD failures fromEOS. The reason that this distinction is important is to define the root cause of the device,component, or system failures. As a result, in this text, this will be re-emphasized.

A third key problem is that the techniques and methods to provide both EOS and ESDrobust products in the same lecture, tutorial, source, or textbook is never synthesized in onediscussion. This is also true that the discussion and training on electromagnetic compatibility(EMC) and ESD are typically taught separately.

This text has multiple goals.The first goal of the text is to teach the basics and concepts of EOS and relate them to real

world processes in semiconductor manufacturing, handling, and assembly.

The second goal of the text is to provide a strong technical base for quantification of EOS,highlighting both mathematical and physical analysis. In this fashion, it is critical tounderstand the role and relationship of thermal physics.

The third goal of the text is to draw a distinction between EOS and ESD. This will beachieved by focusing on the pulse waveform and time scales. The text will constantlyreinforce this distinction through the sources, to the mathematical models.

The fourth goal is to discuss the inter-relationship to other disciplines, such aselectromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup.

The fifth goal is to expose the reader to EOS testing and standards of both semiconductorchips and systems. In this section, we will again distinguish between the EOS and ESD testsand standards.

The fifth goal is to demonstrate how to protect semiconductor chips and systems from EOS.The sixth goal is to demonstrate how to protect semiconductor chips and systems from

both EOS and ESD events.The seventh goal is to teach EOS issues in different technology types for digital, analog,

and power electronics.The eighth goal is to highlight electrical design automation (EDA) methods to provide

EOS robust products. In this section, we will again draw distinctions of EDA solutions forEOS, ESD, and latchup.

The ninth goal is to discuss an EOS program management for manufacturing environ-ments from measurements to audits, to insure an EOS Protected Area.

The tenth goal is to provide a glimpse into the present and future with new nano-structuresand nano-systems that lie ahead. This will provide insight in what will be needed in thefuture, as well as the magnitude of the EOS concern in coming years.

This text, Electrical Overstress (EOS): Devices, Circuits and Systems contains thefollowing:

Chapter 1 introduces the reader to an overview of the language and fundamentalsassociated with EOS. In Chapter 1, the foundation for a discussion of EOS is established.Chapter 1 opens the dialog of defining EOS and its relationship to other phenomena, such aselectrostatic discharge (ESD), electromagnetic interference (EMI), electromagnetic compati-bility (EMC), and latchup. EOS is defined as well in terms of electrical over-current,electrical over-power, and other concepts. In our discussion, there is an emphasis ondistinguishing EOS from ESD. As a result, I will draw distinctions through the text ondifference of failure analysis, time constants, and other means of identification andclassification. A plan to define safe operating area (SOA) and its role in EOS is alsoemphasized.

In Chapter 2, the physical and mathematical basis for understanding EOS is provided. InChapter 2, the goal is to demonstrate the mathematics and physical models associated withpower-to-failure, time constants, and materials. This chapter will provide the tools necessaryto understand the equations and physical limits of the electrothermal models derived in thepast. A key distinction in this chapter, the ESD time regime from the EOS time regime willbe identified to draw attention to the different power-to-failure solutions for these processes.The primary reason for this in-depth discussion is to demonstrate that EOS phenomena canbe quantified and understood – which confronts the skeptics that this is not a science which is

xx PREFACE

quantifiable. In the next chapter, we will allow you to recover from the rigor of this chapter,provide practical connection to the real world, and catch your breath.

In Chapter 3, the text’s focus returns to a practical discussion on the sources and failuremechanisms associated with EOS. The sources will include machinery, solenoids, actuators,to cables and lightning. EOS failure mechanisms from device component failures, bond pads,bond wires, and packaging are identified. In this chapter, some focus on EOS specificfailures from ESD are again be highlighted.

Chapter 4 focuses on EOS failure mechanisms and failure analysis. The chapterhighlights failure analysis process, failure analysis techniques, and tools. Failuremechanism examples are shown from the different failure analysis tool results of bothEOS and ESD failures.

In Chapter 5, EOS and ESD testing techniques and testing standards are discussed. EOStesting methods discussed include system level tests, such as IEC 61000-4-2, and transientsurge standards relevant to EOS (IEC 61000-4-5). The chapter also discusses the ESD testsand standards, such as the human body model (HBM), machine model (MM), charged devicemodel (CDM), transmission line pulse (TLP), very-fast transmission line pulse (VF-TLP), aswell as system-like testing. System-like testing begins to transition toward EOS phenomena,(e.g., cable discharge event; CDE) and hence will be part of our discussion on testing.

Chapter 6 discusses EOS in different semiconductor technologies from CMOS, bipolar,LDMOS, to bipolar-CMOS-DMOS (BCD) technologies and the issues that arise in thedifferent application spaces. A focus will be on how the technologies can address power andEOS robustness issues.

The focus in Chapter 7 is EOS design. A key question that arises is, ‘how does EOSdesign differ from ESD design?’. A second key question is, ‘how do you design for both ESDand EOS in a given chip or system design?’. This chapter includes product definition,specifications, technology identification, to both top-down and bottom-up design methodolo-gies and floor planning. It also shows usage of circuit design to address over-current andover-temperature controls.

In Chapter 8, EOS protection devices are discussed. These include a plethora of elementsfrom snapback devices to voltage triggered devices. EOS protection is achieved usingtransient voltage suppression (TVS), thyristor surge protection devices (TSPD), metal oxidevaristors (MOV), conductive polymers, gas discharge tubes (GDT), fuses, circuit breakers,and other elements. These EOS protection elements are very distinct from those employedfor ESD protection.

In Chapter 9, system level problems and solutions are discussed. The focus is on EOScontrol in the production and manufacturing environment. The chapter addresses preventiveactions, controlling the back end process, to product area operations.

In Chapter 10, electronic design automation (EDA) techniques and methods for EOS arediscussed. Design rule checking (DRC), layout versus schematic (LVS), to electrical rulechecking (ERC) methods are used for both ESD and EOS checking and verification. In thischapter, methods being applied today for EOS environments are shown.

In Chapter 11, an EOS program management process is discussed. The chapter willdemonstrate topics on design reviews, checklists, corrective actions, audits, and the designrelease process to guarantee EOS robust products.

PREFACE xxi

In Chapter 12, EOS in future structures and nano-devices is discussed. The chapterdiscusses EOS issues in magnetic recording, FinFETs, graphene, carbon nano-tubes, tophase change memory. This concluding chapter takes a look at micro-motors, micro-mirrors,RF MEM switches, and many novel devices. EOS in silicon interposers and through siliconvia (TSV) in 2.5-D and 3-D systems is also highlighted.

This introductory text will hopefully open your interest in the field of electrical overstress(EOS), electrostatic discharge (ESD), electromagnetic interference (EMI), and electro-magnetic compatibility (EMC) – and teach how it relates to today’s world. To establish astronger knowledge of ESD protection, it is advisable to read the other texts ESD Basics:From Semiconductor Manufacturing to Product Use, ESD: Physics and Devices, ESD:Circuits and Technology, ESD: RF Circuits and Technology, ESD: Failure Mechanisms andModels, ESD: Design and Synthesis, and Latchup.

Enjoy the text, and enjoy the subject of EOS – just do not get stressed out over electricaloverstress (EOS).

Baruch HaShem

Dr. Steven H. Voldman

IEEE Fellow

xxii PREFACE

Acknowledgments

I would like to thank the years of support from the SEMATECH, the ESD Association, theIEEE, and the JEDEC organizations. I would like to thank the IBM Corporation, QimondaCorporation, Taiwan Semiconductor Manufacturing Corporation (TSMC), the IntersilCorporation, and the Samsung Corporation. I was fortunate to work in a wide number oftechnology teams, and with a wide breadth of customers. I was very fortunate to be a memberof talented technology and design teams that were both innovative, intelligent, and inventive.

I would like to thank the institutions that allowed me to teach and lecture at conferences,symposiums, industry, and universities; this gave me the motivation to develop the texts. Iwould like to thank faculty at the following universities: M.I.T., Stanford University,University of Central Florida (UCF), University Illinois Urbana–Champaign (UIUC),University of California Riverside (UCR), University of Buffalo, National Chiao TungUniversity (NCTU), Tsin Hua University, National Technical University of Science andTechnology (NTUST), National University of Singapore (NUS), Nanyang TechnicalUniversity (NTU), Beijing University, Fudan University, Shanghai Jiao Tung University,Zheijang University, Huazhong University of Science and Technology (HUST), UESTC,Universiti Sains Malaysia (USM), Universiti Putra Malaysia (UPM), Kolej DamansaraUtama (KDU), Chulalongkorn University, Mahanakorn University, Kasetsart University,Thammasat University, Korea University, and Mapua Institute of Technology (MIT).

I would like to thank for the years of support and the opportunity to provide lectures,invited talks, and tutorials the Electrical Overstress/Electrostatic Discharge (EOS/ESD)Symposium, the International Reliability Physics Symposium (IRPS), the Taiwan Electro-static Discharge Conference (T-ESDC), the International Electron Device Meeting (IEDM),the International Conference on Solid-State and Integrated Circuit Technology (ICSICT), theInternational Physical and Failure Analysis (IPFA), IEEE ASICON, and the IEEE IntelligentSignal Processing And Communication Systems (ISPACS) Conference.

I would like to thank my many friends for 22 years in the ESD profession – Prof. MingDou Ker, Prof. J.J. Liou, Prof. Albert Wang, Prof. Elyse Rosenbaum, Timothy J. Maloney,Charvaka Duvvury, Eugene Worley, Robert Ashton, Yehuda Smooha, Vladislav Vashchenko,Ann Concannon, Albert Wallash, Vessilin Vassilev, Warren Anderson, Marie Denison, AlanRighter, Andrew Olney, Bruce Atwood, Jon Barth, Evan Grund, David Bennett, Tom Meuse,Michael Hopkins, Yoon Huh, Jin Min, Jeffrey Dunnihoo, Keichi Hasegawa, Teruo Suzuki,

Han Gu Kim, Kitae Lee, Nathan Peachey, Kathy Muhonen, Augusto Tazzoli, GaudenzioMenneghesso, Marise BaFleur, Jeremy Smith, Nisha Ram, Swee K. Lau, Tom Diep, LifangLou, Stephen Beebe, Michael Chaine, Pee Ya Tan, Theo Smedes, Markus Mergens, ChristianRuss, Harold Gossner, Wolfgang Stadler, Ming Hsiang Song, J.C. Tseng, J.H. Lee, MichaelWu, Erin Liao, Stephen Gaul, Jean-Michel Tschann, Tze Wee Chen, Shu Qing Cao, SlavicaMalobabic, David Ellis, Blerina Aliaj, Lin Lin, David Swenson, Donn Bellmore, Ed Chase,Doug Smith, W. Greason, Stephen Halperin, Tom Albano, Ted Dangelmayer, Terry Welsher,John Kinnear, and Ron Gibson.

I would like to thank the ESD Association office for their support in the area ofpublications, standards developments, and conference activities. I would also like to thankthe publisher and staff of John Wiley & Sons for including this text as part of the ESD bookseries.

To my children, Aaron Samuel Voldman, and Rachel Pesha Voldman, good luck to both ofyou in the future.

To my wife Annie Brown Voldman – thank you for the support of years of work.And to my parents, Carl and Blossom Voldman.

Baruch HaShem

Dr. Steven H. VoldmanIEEE Fellow

xxiv ACKNOWLEDGMENTS

1 Fundamentals ofElectrical Overstress

FUSE-BLOCK“To all whom it may concern:Be it known that I, THOMAS A. EDISON, of Menlo Park, in the county of Middlesex

and State of New Jersey, have invented a certain new and useful Improvement inLightning Arresters (Case No. 644,) of which the following is a specification.

My invention relates to fusible safety-catches or lightning-protections for telephones,telegraph, and similar circuits in which the fusible wire is placed in an inclosing shell orchamber of insulating material; and my object is to prevent or diminish the liability tosurface creeping of lightning or other powerful current . . .”

United States Patent OfficePatent No. 438,30514 October 1890

Electrical overstress (EOS) has been an issue with the coming of the electrical age, whenelectricity and electrical product were first introduced into the mainstream of society. Withthe introduction of electrical power systems, the telephone, and electronics, inventions suchas circuit breakers and fuses became the first type of electrical overstress protection conceptsto avoid over-load of electronic systems.

In this text, electrical overstress (EOS) will be addressed for the modern age of new devices,components, and systems.Wewill first visit the 1970s where the interest in EOS arose due to agrowinginterest inthereliabilityandqualityofcomponentsandsystems.Intheendofthetext,wewill arrive at the future of “Nano-EOS” – EOS in nanotechnologies.

Electrical Overstress (EOS) : Devices, Circuits and Systems, First Edition. Steven H. Voldman.� 2014 John Wiley & Sons, Ltd. Published 2014 by John Wiley & Sons, Ltd.

1.1 ELECTRICAL OVERSTRESS

Electrical overstress (EOS) has been an issue in devices, circuit and systems for electronicsfor many decades, as early as the 1970s [1–12], and continues to be an issue today [13–83].Market segments from consumer, industrial, aerospace, military, and medical are all in-fluenced by this issue. The experience of EOS failures occurs at the device manufacturer,supplier, assembly, and the field. In the electronic industry, many products and applicationsare returned from the field due to “EOS” failure. To make progress in addressing theEOS issue, it is important to provide a framework for the evaluation and analysis of EOSphenomena. As part of this framework, it is important to apply a vocabulary and defini-tions. It is key to apply both physical and mathematical definitions to quantify theEOS conditions. It is equally important to establish a methodology of failure analysis andtesting. It is also critical to establish an awareness of the origins and sources of EOSconcerns. In the end, to provide better EOS robust products, it is important to define designpractices and procedures, as well as EOS control programs for manufacturing andproduction areas.

1.1.1 The Cost of Electrical Overstress

One of the key concerns of EOS is the cost. There are different types of costs associated withEOS. In this section, the cost associated with field returns will be discussed. In order toquantify the cost of EOS events on products, it is critical to categorize what percentage offield returns are in fact EOS related.

1.1.2 Product Field Returns – The Percentage that is ElectricalOverstress

Product field returns occur in all electronic components independent of the technologygeneration and period of time of evaluation. One of the key difficulties in the semiconductorindustry is the ability to track, record, and maintain a database of these field failures.

A key question in the electronic industry is what is the percentage of the field returns thatis due to electrical overstress (EOS)?

In the mid-1980s, the military established an in-house program to track, record, andcategorize field failures to answer this question [49]. The United States military and theReliability Analysis Center (RAC) in Rome, N.Y., jointly established the Field FailureReturn Program (FFRP), with the objective of providing feedback to the semiconductorindustry, and determine the root cause of failure. With establishing the root cause of failure,the corrective action can be initiated. The FFRP goals were as follows [49]:

� Identify high failure rate, or component problems.

� Identify their root causes of failure from failure analysis

� Feedback the information to the supplier, industry, or government organization forcorrective action.

2 FUNDAMENTALS OF ELECTRICAL OVERSTRESS

In this early reliability study, data from 24 different systems was collected and reviewed.In this review, 1650 parts were evaluated, of which the part numbers were from actual fieldfailures that were operational from two to 10 years. Table 1.1 shows the results of the fieldfailure categories [49].

From this study, 46% of the field returns were associated with electrical overstress (EOS).It was regarded from this study that a number of EOS issues were associated with poorsystem design, improper maintenance procedures, and improper operational procedures. Inthe second category, it was regarded that these failures were from inherent flaws and latentdefects. Of the field returns, only a small percentage was related to electrostatic discharge(ESD). Note that in some cases it was decided that it was not possible to determine if thefailures were EOS or ESD (Figure 1.1).

The results of this study are not significantly distinct from other future studies. It istypically quoted that EOS is a high percentage of field failures, and a certain percentagecannot distinguish EOS from ESD.

In more recent studies, C. Thienel’s study for the automotive industry called “Avoidingelectrical overstress for automotive semiconductors by new connecting concepts,” attributed6% of the failures to ESD and 94% were associated with EOS [77,79,80]. A large percentageof the fails were “no defect found” and approximately 32% were EOS/ESD failures.

Table 1.1 Field failure categories and percentages

Field failure category Field Failures (%)

Electrical overstress (EOS) 46IC design, fabrication, and assembly 25Retested without observed failure 17Electrostatic discharge (ESD) 6EOS or ESD 6

Figure 1.1 Failure categories pie chart

ELECTRICAL OVERSTRESS 3

1.1.3 Product Field Returns – No Defect Found versus ElectricalOverstress

In practice, product field returns are sent from the customers back to the source ofproduction. These “field returns” come back to the quality organization, where the root causeof the field failure is diagnosed. A large percentage of the field returns are labeled “no defectfound” (NDF) when the root cause cannot be observed. It is well known that many of thefield returns are electrical overstress (EOS) related.

1.1.4 Product Failures – Failures in Integrated Circuits

Failures occur in the production of integrated circuits (IC) impacting yield. Studies have shownthat the impact to IC productions from electrical overstress (EOS) and electrostatic discharge(ESD) can be up to 37% of the product failures (Table 1.2) [49]. In this study, it was found that25% of the product failures were associated with fabrication. For the assembly process, it wasfound that the magnitude of yield loss was on the order of 12%, and another 12% wasunknown. These percentages are dependent on the technology and controls in the foundry, butprovide use with a view of the impacts of the various issues that accompanies yield loss.

In this chapter, some fundamental definitions will be introduced and concepts to open thediscussion of (EOS). In future chapters, the text will proceed with the aforementioned topicsof EOS.

1.1.5 Classification of Electrical Overstress Events

Electrical overstress (EOS) is such a broad spectrum of phenomena, it is important toestablish classifications of EOS. The definition of EOS includes electrical response tocurrent, voltage, and power.

Electrical phenomena is categorized into different definitions, which will be discussedin depth in future sections. Common categorization include electrostatic discharge (ESD),electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchupissues (Figure 1.2) [84–89]. At times, all of these are included in the definition of EOS; yetothers separate these categories as separate items to distinguish them for the purpose ofdetermining cause–effect relationships, as well as root cause. For example, although ESDis a form of EOS, it is established in the semiconductor industry to distinguish them. Oneof the reasons this is done is due to determining the root cause of failure.

Table 1.2 Failures in IC production

Cause of yield loss Percentage (%)

Electrostatic discharge/electrical overstress 37Fabrication 25Assembly 12Unknown 12

4 FUNDAMENTALS OF ELECTRICAL OVERSTRESS