ELECTRONIC CIRCUITS - NASA · This Compilation contains articles on newly developed electronic...

NASA SP-5972 (07)January 1976

TECHNOLOGY UTILIZATION

ELECTRONIC CIRCUITS

A COMPILATION

NATIONAL AERONAUTICS AND SPACE ADMINISTRATION

https://ntrs.nasa.gov/search.jsp?R=19760013284 2018-08-30T23:19:42+00:00Z

Foreword

The National Aeronautics and Space Administration has established aTechnology Utilization Program for the dissemination of information ontechnological developments which have potential utility outside the aerospacecommunity. By encouraging multiple application of the results of its research anddevelopment, NASA earns for the public an increased return on the investment inaerospace research and development programs.

Compilations are now published in nine board subject groups:SP-5971: Electronics - Components SP-5976: Mechanics

and Circuitry SP-5977: MachinerySP-5972: Electronics Systems SP-5978: FabricationSP-5973: Physical Sciences TechnologySP-5974: Materials SP-5979: Mathematics andSP-5975: Life Sciences Information SciencesWhen the subject matter of a particular Compilation is more narrowly defined, itstitle describes the subject matter more specifically. Successive Compilations in eachbroad category above are identified by an issue number in parentheses: e.g., the (03)in SP-5972 (03).

This Compilation contains articles on newly developed electronic circuits andsystems. It is divided into two sections: Section 1 on circuits and techniques ofparticular interest in communications technology, and Section 2 on circuits designedfor a variety of specific applications.

Additional technical information on items in this Compilation can be requestedby circling the appropriate number on the Reader Service Card included in thisCompilation.

The latest patent information available at the final preparation of thisCompilation is presented on page 42. For those innovations on which NASA hasdecided not to apply for a patent, a Patent Statement is not included. Potential usersof items described herein should consult the cognizant organization for updatedpatent information.

We appreciate comment by readers and welcome hearing about the relevanceand utility of the information in this Compilation.

NOTICE* This document was prepared under the sponsorship of the National Aeronautics and SpaceAdministration. Neither the United States Government nor any person acting on behalf of the UnitedStates Government assumes any liability resulting from the use of the information contained in thisdocument, or warrants that such use will be free from privately owned rights.

For sale by the National Technical Information Service, Springfield, Virginia 22161

ContentsPage

SECTION 1. COMMUNICATIONS CIRCUITS AND TECHNIQUESAutomatic Pulse-Code-Modulation (PCM), Data-Polarity Inversion 1Four-Phase Differential Phase Shift Resolver 2Digital Phase-Locked Loop 4Binary Code to Ratio Code Conversion Circuit 6FM Transmitter With Precise Modulation Index Control: A Concept 8Phase-Detecting, Self-Directing Digital Couplers: A Concept 10Asynchronous Delta Modulator Replaces Clocked Systems 11UHF PIN Diode Switches 12Flexible Playback Speed Control for Tape Recorded Data 14Error-Decoding Algorithm 15

SECTION 2. SPECIALIZED CIRCUITS FOR INSTRUMENTATIONActive Tuned Circuit 16Low-Frequency Peak Detector 17Input Circuit for Thermal-Conductivity Gas-Chromatograph Detector 18Inverted, Voltage-Controlled Oscillator 20Integrable Power Gyrator 22Low-Noise Instrumentation Amplifier for Low-Frequency Applications . . . . 24Rapid Battery Activation and Cell-by-Cell Voltage Measurement 25Scatterometer Preprocessor Svstem 25Solid-State Power Switch 26Impulse Commutating Circuit With Transformer To

Limit Reapplied Voltage 28Overload Control Circuit for Reversing Split-Phase Motors 30Pulse-Generating Network for Magneto Plasma Dynamic Thrusters 31High-Speed Analog Switch for CRT-Display

Stroke-Waveform Generators 32Image Enhancer for Airborne Scanners 33Improved Electron-Gun Beam Delection and Focusing 34Video Peak/Average Detector 36Fast Low-Power-Drain Logic Circuits 37Random Automatic Sequencing Without a Memory 38Complementary MOS Four-Phase Logic Circuits 40

PATENT INFORMATION 42

Section 1. Communications Circuits and Techniques

AUTOMATIC PULSE-CODE-MODULATION [PCM],DATA-POLARITY INVERSION

PCMSycnWord Sync

Amplifier

ComplementSync

DecisionAmplifier

Sync Pulse

Sync

Pulse

.PCM System

CounterShift

Register

Normal-PolarityLevel

Converter

Note: All Resistances in Ohms

O Manual Polarity

-5 V = Normal Polarity0= Inverted Polarity

-5V

Figure 1. PCM Polarity-Inversion System

One kind of noise that can occur in a PCM recoverysystem is the inversion of polarity (i.e., "0" and "1"bits are switched). When this occurs, the recoverysystem will become improperly synchronized and datawill be lost. The resynchronization of conventional

+10 Vdco

R. <i "2 *•8.2K <

f

Input R]

2.2 K

Note:

I>>

All Resistances In Ohms

R I Test3.3K| V

J0,k.

c,- 0.015 MF

k

2N1 308

Point

Output

INPUT0 Vdc

-10 Vdc-10 Vdc

0Ground

OUTPUT0 Vdc

+10 Vdc+ 5 Vdc

LOAD

No LoadLoad

Figure 2. Normal-Polarity-Level Converter

PCM systems requires several steps by the operator:When the sync is lost, the polarity is switchedmanually; if this resynchronizes the system, the job isrestarted and the polarity is switched manually at thetime of the data-polarity inversion.

An improved signal-conditioning circuit causes therecovery-system polarity to change automatically inresponse to data-polarity inversion, thus preventingloss of data. The system is shown in Figure 1. ThePCM data are conditioned by a signal conditioner andthen are decoded. If the polarity of the data inverts,the complement sync decision amplifier recognizes thesync word and issues a pulse. This pulse sets aflip-flop, which changes the output level of thenormal-polarity-level converter (Figure 2). This levelshift causes the signal conditioner to invert the dataautomatically. The sync decision amplifier recognizesthe PCM sync word and issues a pulse indicating gooddata.

Source: W. J. Goulding ofRockwell International Corp.

under contract toJohnson Space Center

(MSC-17866)

No further documentation is available.

ELECTRONIC CIRCUITS

FOUR-PHASE DIFFERENTIAL PHASE SHIFT RESOLVER

BIT PAIRCH1 CH2

0011

0101

PHASE SHIFTADDED

0°

90180270°

(00rMultipleThereof

Channel 2 Bit Stream

Channel 1 Bit Stream

i IB IB

May BeAnalog

Switches

Add Clock (Delayed SlightlyFrom Bit Clock)

Sinusoidal4-PhaseOutput

At f

BandpassFilter

SqSi

May BeSummingJunction

Sine Wave

Figure 1. Adding Encoder/Modulator

Four-phase differential phase shift (DPSK) systemsrequire a phase reference tn resolve phase uncertaintyduring demodulation. Of the systems currently used,locally generated phase references introduce a phaseuncertainty; references derived from a single receivedbit are noisy; and transmitted phase references use upa portion of the bandwidth and signal power,resulting in a reduction in the signal-to-noise ratio.

Two similar systems have been developed, both ofwhich resolve phase uncertainty without transmittingreference signals or compromising the signal in anyway. In both methods the signal is impressed on thecarrier as a differential, rather than an absolute,phase shift. A transmitter-encoder uses a two-bitaccumulating adder to put a phase-shift code on aselected phase of the subcarrier. At the receiver, afour-phase demodulation and logic process unambig-uously resolves the differential phase shift of the inputcarrier. Two receiving methods have been developed.In one method, a two-bit subtracter extracts thereference code and, in the second method, a decoderwith a more general algorithm is used for thedecoding.

In both systems, the signal is encoded upon trans-mission as shown in Figure 1. At the input to theencoder, the two synchronized bit streams are applied

to the input of a two-bit adder. Also input to the adderare two bits representing the accumulated sum of allpast inputs. The four outputs A, A, B, and B arecombined logically in the quadriphase modulator withthe four outputs from the four-phase generator. It isthe phase shift and not the absolute phase that is theimportant parameter. The four-phase output from themodulator passes through a bandpass filter to removeunwanted harmonics and can be transmitted directlyover a telephone line or as a carrier (or subcarrier) inan RF transmission link.

At the reception point, the signal is demodulated asshown in Figure 2. The frequency of the incomingsignal is doubled twice (multiplied by four), bysquaring and filtering, to give a signal at four timesthe carrier frequency (4f0). Since sine waves at thesame frequency separated by 360° are indistinguish-able, the fourth-harmonic signal, divided by four, isphase-invariant and may be used as a phasedemodulator reference. At this point there is anunavoidable uncertainty in phase. However, thereference phase can be made to match the carrierphase within 90°. A 45° phase shift places the de-modulator reference-phase equidistant between two ofthe received phases.

COMMUNICATIONS CIRCUITS AND TECHNIQUES

Cos (4 OJct •)• 2nJT) = Cos (4 Wet)

nilCos (CJct + — ) -

2(4-Phase Input)

• M Square I *BPF2fo

Square HPhase

1 BPF4fo

/

/fc

Bandpass FilterOr

Phase Locked LoopAt 4f0

Frequency

-5-4

CarryNot Used

Figure 2. Demodulator/Subtracting Decoder

Logic "1"I I n p u t

|so ^ Channel 2Carry Output

, Channel 1Output

It is not necessary to determine the absolute phaseof the reference signal; an unambiguous signal may beconstructed by detecting the differential phase shift ofthe carrier between successive bit periods. Onemethod of doing this is shown in Figure 2. A two bitaccumulating subtracter is used to decode the signal.Signal conditioners and bit synchronizers are used toremove noise and produce two synchronized binary bitstreams that are input to the subtracting decoder. Inthe decoder, the "exclusive-or" gate performs a countcorrection to produce an output identical to theoutput of the accumulating adder in the encoder.

The input data can be retrieved by taking successivedifferences between the bit pair output from the countcorrector and the previous bit pair stored in the shiftregister. Subtraction is accomplished with a binarytwo-bit adder.

Another decoding technique (not shown) uses aphase resolver with a more general algorithm in placeof the two-bit subtracter. As before, the two one-bitshift registers serve as a one-bit-period memory. Theoutputs of the bit synchronizers are compared with

the outputs of the shift registers. A transition logicdetects differences between the input phase statussignals and the stored phase status signals and inputsa signal representing this change to the resolver logic.

The resolver logic forms phase shift indicatorsignals which are decoded into output data bits. Theoutput data bits are assigned in accordance with theencoding performed at the transmitter.

Both of these systems transmit and receive datawithout ambiguity and allow unique identification oftwo data channels without transmitting identificationsequences.

Source: P. M. Hopkins andW. M. Wallingford of

Lockheed Electronics Co.under contract to

Johnson Space Center(MSC-14065)

Circle 1 on Reader Service Card.

ELECTRONIC CIRCUITS

DIGITAL PHASE-LOCKED LOOP

Analog phase-locked loops usually include analogfiltering elements, voltage-controlled oscillators, andintegrators. These components are subject to drift andnonlinearity, and lack precise repeatability fromsystem to system. The digital phase-locked loopshown in Figure 1 overcomes these problems.

An exclusive OR gate receives an input signal andthe loop output signal. The duty cycle of the errorsignal Ve (see Figure 2) is representative of the phasedifference between the input (Vin) and output (Vout)signals. Selection of one of two clocks (Vj or ¥3)depends upon the state of Ve. When Ve is "0", theoutput of AND gate 1 is Vt and the output of ANDgate 2 is "0". When Ve is "1", the output of ANDgate 1 is "0", and the output of AND gate 2 is V2. Theresulting waveshape, Vc, is fed into an accumulator(e.g., a divide-by-K counter) which produces Vou^.

The phase lag between Vjn and Vout may berepresented by a parameter a, equal to the fraction of

90° by which Vout deviates from a 90° phase lag ofVin. (Thus if a is "0", Vout lags Vin by 90°.) Theoutput frequency as a function of a is shown inFigure 3. The loop adjusts Vout until the outputfrequency equals the input frequency and thus locksthe loop at a phase lag of

a-90° =f2+f, - 2K fjn

90°

Where fjn is the input frequency, andclock frequencies as shown in Figure 1.

and f2 are

VjnO

Figure 1. Phase-Locked Loop


Vint

/ 2—j

1 IJ [ • Time

aT/4-H

v°utf I I -•Time

-a)1 t-v-t l~l -•Time

• Time

• Time

Figure 2. Signal For Phase-Locked Loop

-•Time

Figure 3. Plot of fout Vs. a

Source: Rodger A. CliffGoddard Space Flight Center

(GSC-11623)


ELECTRONIC CIRCUITS

BINARY CODE TO RATIO CODE CONVERSION CIRCUIT

Bina ry CcIn

5-Bit

BinDecY .

S

f-

5

>deput

Adc

L

aryode

Jer < <

A1 B

CD 400 8A

S1

" ~ ~~~ '~f

|0 |0

f-

^^^^»

1

C

~CM

r D C B A

DEC -6

3 2 1 0

I

f7 ^ '

5__—

_D C B A D C B A

DEC - 7 DEC - 8

7 0 7 0

^

cout

in

A

<N<<4^

A

£

S2~

CMCD<•«

CO

<• • •

CO «m << <^•i • •

r̂CD<

in in< CD< <• ••

4 B4 A3 B3 A2 B2 A1 B1

CinCD 400 8A ^ —

4 S3 S2 S1

^D C B A

DEC - 9

7 0iiuii 1 1 1 ii 1 1 1 MI1 1 1 1

L

COV

7

1

I— I ASS ""

•«• m>- >-

DC B /

DEC- 1

Note: DEC 1 through 10 are CD4028ANOR Gates are (1/4) CD4001A

r

\0

CNJ

>-

O

^S4

r

^

iXo

' AS5

— 1

T—

X

IO~TO"VJ

><

D C B A

DEC - 1

3 2 1 0

f ^D C B A

DEC - 2

' 0

? '

D C B A

DEC -3

7 0

* 3

r \i

D C B A

DEC - 4

7 0

i

p>X

/1

•*r irX >

D C B

DEC -

i in ii i INI 111 mill ii - 1 1 1 1 1 1

H — h H — h t̂ •.1 r —i

A

5

.JpgCOXo

BinaryDecoderX

L01

32 NOR Gates

O2 2-of-32 Code Output (Negative True)

Conversion Circuit:9-Bit Binary Code to 2-of-32 Ratio Code

O32


Certain digital data are most efficiently transmittedas a binary code but are most efficiently decoded as aratio code (m of n lines true). Therefore an interactivedigital circuit has been designed to convert binary-encoded data into ratio-encoded data without alteringthe data content. The circuit as designed to convert a9-bit binary code to a 2-of-32 ratio code is shown inthe figure.

The circuit employs complementary MOS integra-ted circuits and may be considered to contain fourfunctional blocks composed of 1C logic elements asfollows:

1. One 5-bit adder;2. Two 5-bit binary decoders: X and Y; and3. NOR gate array.

The input code is a 9-bit binary number on lines IIthrough 19 (with the most significant bit on line 19).Lines 15 through 19 are presented as 1X1 through 1X5to binary decoder X. This decoder places a logic 1signal on one of the 32 output lines (OX1 throughOX32) and a logic 0 on the other 31 lines. A differentoutput line is high for each of the 32 possible combi-nations of logic levels on the five input lines (1X1through 1X5).

Lines 15 through 19 are also presented as AB1through AB5 to the adder. The second numberpresented to the adder comprises a hard-wired 0 bit asAA1, and lines II through 14 are presented as AA2through AA5. The carry-bit input to the adder is ahard-wired 1. The adder carry output is ignored sothat the adder output on lines AS1 through ASSrepresents the modulo 32 sum of the two inputnumbers plus one.

Lines AS1 through ASS are presented as IY1through IY5 to binary decoder Y. The action of thisblock is similar to that of binary decoder X and resultsin a 1 level on one of 32 lines (OY1 through OY32).Lines OY1 through OY32 and OX1 through OX32 arecombined by 32 NOR gates which output a single setof 32 lines (01 through 032) carrying the desired2-of-32 ratio code. The output is in inverted form (twolines 0 and 30 lines 1).

Source: Victor Auerbach ofRCA Corp.

under contract toGoddard Space Center

(GSC-11646)


ELECTRONIC CIRCUITS

FM TRANSMITTER WITH PRECISE MODULATIONINDEX CONTROL: A CONCEPT

The modulation index (peak-to-peak deviationdivided by bit rate) of a PCM/FM modulator dependson both the amplitude and the frequency of themodulating wave. Thus the index is difficult to controlprecisely. A new PCM/FM transmitter has beenproposed which can closely control a selected indexand thus conserve the RF spectrum. The modulatorcan be used with coherent and noncoherent detectors.

The transmitter (Figure 1) includes two carrierquadrature modulators fed by sine and cosine waves.

The FM signal is generated from the output of the twomodulators. An FM signal s(t) may be represented as:

s(t) = A cos [ojct+/JM(t)]where M(t) = /JmWdr,

/} = the modulation index, andcue = the angular frequency of the

carrier word.

Using a trigonometric identity, this expression may berewritten as:

s(t) = [cos coct cos /3M(t) - sin cuct sin flM(t)].

Divide By2

t

ddt

I T 11Square-Wave

Clockfc= Bit Rate

1Data Source

NRZ-L

1 11-BitDelay

Mod2

Gate passes ± impulseswhen Modulo 2 is plus,but does not pass impulseswhen Modulo 2 is zero.

Cosine 90° COS 0)ct

Figure 1. FM Transmitter for Precise Modulation Index = 0.5


Data Sequence

g,(t)

9i(t)

1.4

Time (Seconds)

0.2 0.3 0.4 0.5 0.6 0.

-5

Figure 2. Waveforms for Quadrature Modulators(Modulation Index = 0.5)

As shown by this equation, the FM signal can beformed by the superposition of independently-generated sine and cosine signals. Figure 2 shows thewaveforms, ga(t) = - sin /JM(t) and g2(t) = cos /3M(t),required for an FM transmitter with a modulationindex of 0.5. These waveforms are related to the bitrate as shown in Figure 2.

Source: J. Neil Birch ofThe Magnavox Co.

under contract toGoddard Space Flight Center

(GSC-11594)


10 ELECTRONIC CIRCUITS

PHASE-DETECTING, SELF-DIRECTING DIGITAL COUPLERS: A CONCEPT

</ NR1

1/2-BitDelay

—\\\

S, S

& i-S

RS Flip-Flop

1/2-BitDelay

NS1 \>—

Phase-Detecting, Self-Directing Digital Coupler

Present data-bus coupling devices require controllines or address decoding circuits to select and controlthe mode of operation; either transmission orreception. A phase-detecting, self-directing digitalcoupler could operate autonomously as a transmitteror a receiver, as required, and therfore could beutilized in many applications as a line buffer, a lineextender, or for modular add-ons.

The circuit is shown in the illustration. Thedirection of signal flow is determined by digital 1Ccircuits which sense the input-to-output transit delay.Input/output amplifiers (D^D^ are automaticallyenabled or disabled by the sensing circuit according tothe signal direction.

Suppose, initially, that no signals are flowing ineither direction. Under these conditions points A and

B are normally high (logic 1), and the outputs ofNAND gates NR1 and NS1 are thus held at 1 by thecapacitor-coupled inverting networks. The negative-going edge of a signal at A or B, whichever occursfirst, will then drive NS1 or NR1, respectively, with apulse generated by the coupling capacitor. Gates NR1and NS1 set the state of the RS flip-flop which in turncontrols amplifiers Dt and D2. A phase differencebetween input and output signals, sufficient to insuredetection, is generated by the 1/2-bit data delay units.This pulse delay technique utilizes the delay betweeninput and output signals to sense signal direction.Thus if a signal arrives at A, the RS flip-flop is set toenable amplifier Dt and to disable amplifier D2.Exactly the reverse action occurs if a signal arrivesfirst at B.

COMMUNICATIONS CIRCUITS AND TECHNIQUES 11

The concept has excellent modularity and flexibi-lity. The various sections can be removed andreplaced without affecting the operations of the othersections. Enable/disable control lines are eliminated,and the total length of data transmission is limitedonly by the delay of the coupler and the transmissionline.

Source: G. R. Enoki andL. E. Alderman of

Rockwell International Corp.under contract to

Marshall Space Flight Center(MFS-24426)


ASYNCHRONOUS DELTA MODULATOR REPLACES CLOCKED SYSTEMS

An asynchronous delta modulator has beendesigned for use in communications systems. Themodulator system converts analog audio signals intotrains of digital pulses. It operates in an asynchronous

Squaring Amplifier

Input Output

Integrating Amplifier

ASYNCHRONOUS DELTA MODULATOR

Squaring Amplifier Integrating Amplifier

Input Output

ASYNCHRONOUS DELTA DEMODULATOR

mode requiring no clock pulses and thus, at the samebit rate as a clocked or synchronous delta modulator,provides a higher degree of intelligibility.

The circuit (see figure) consists of an add network,a squaring amplifier, and an integrator. With noinput signal, the circuit operates as a bistableoscillator with a characteristic free-running fre-quency. This frequency appears as a square wave atthe output. With an input signal applied, thesquaring amplifier tends to remain at one stable statefor longer periods of time, in order to conform to thecharacteristics of the input signal. The outputfrequency is therefore lower than the free-runningfrequency.

The advantages of the asynchronous delta modu-lator over a clocked delta modulator are: (a) its abilityto maintain the same levels of intelligibility for a givenbit rate and (b) its lower noise level, due to theelimination of undesirable noise caused by clocktransitions. It therefore should be of interest tomanufacturers of digital communications equipment.

Source: J. A. Webb ofLockheed Electronics Co.


(MSC-13812)

Functional Block Diagram of Asynchronous DeltaModulator and Demodulator Circle 4 on Reader Service Card.


UHF PIN DIODE SWITCHES

ResonantInductive Choke

Port 2 Port 3

Port 1 Port 4

Figure 1. UHF SP4T PIN Diode Switch

Single-pole-double-throw (SPDT) and single-pole-4-throw (SP4T), ultrahigh-frequency (UHF), power-switching circuits have been constructed usingcathode-connected rectifying diodes. The circuitsinclude the associated inductors and capacitors, and ahigh-impedance conduction line. These switches areconstructed using strip-line techniques and aresuitable for ultralow loss, high-efficiency, high-power,broadband switching applications.

Figure 1 shows the schematic of the UHF SP4T PINdiode switch. DC bias is supplied to the series diode

through an inductive choke, consisting of a high-impedance section of transmission line connected tothe center conductor of the strip-line. The dc return issimilarly provided by grounding the input through ahigh-impedance line which forms a choke to block theRF. When the diode is forward biased, RF is passed.When the diode is reverse biased, high isolation isachieved. The switch is constructed in air-dielectricstrip transmission line. A special beryllium oxideshunt mounting technique is employed to heat sinkthe PIN diode to the case for good thermaldissipation.

COMMUNICATIONS CIRCUITS AND TECHNIQUES 13

Vs Switching Bias

Port 1 ResonantInductive v

Choke x

Port 2

~ /DC Ground

Input

Figure 2. UHF SPOT PIN Diode Switch

The schematic of the UHF SPDT PIN diode switchis shown in Figure 2. The design for this switch is verysimilar to that of the SP4T switch described earlier.

Test reports show the insertion loss to be less than0.3 dB for the SP4T switch and less than 0.2 dB forthe SPDT switch. Isolation is greater than 20 dB forboth switches. Although the design application calledfor operation over narrow bands centered at 401.9 and463.825 MHz, tests showed that both switches couldoperate from 370 to 500 MHz. Junction temperaturemeasurements proved that the glass axial-lead PINdiodes could handle the required 40 watts. Theswitches have been operated at power as high as 60watts without failure. Each switch requires only 125mW of dc power to operate.

These devices have proved, superior to ferritedevices or conventional diode switches in insertionloss, isolation, and efficiency. In addition, they aresmaller in size, weigh less, and are insensitive totemperature and magnetic effects.

Source: M. A. Ikemoto andR. C. Chapman ofPhilco-Ford Corp.under contract to

Goddard Space Flight Center(GSC-11678)



FLEXIBLE PLAYBACK SPEED CONTROL FOR TAPE RECORDED DATA

Tape recorded data can normally be played backonly at speeds differing from the recording speed byfactors of 2 (e.g., 1/2, 1/4, 1/8 ... of the recordedspeed). If some other playback speed is required, anexternal generator is usually used to control therecorder oscillator during playback. The use of suchexternal equipment, as opposed to direct multipli-cation of internal frequencies, introduces errors dueto the variances between the recorder oscillator andthe external oscillator.

A new technique allows the playback speed to beany desired fraction of the recording speed. Duringrecording, a track is designated as a pseudo controltrack. It can be any unassigned track or the normalcontrol track. A sine wave is recorded on the pseudocontrol track, as selected from the following formula:

FP = FN • -|-

where Fp = the pseudo control track frequency,FN = the inherent frequency of the recorder

control track,R = the desired record-to-playback speed

ratio, andK = a constant selected from the table shown

(at right).

As an example, assume the data are recorded at 60ips with a control frequency of 100 kHz, and aplayback speed 1/22 (3-3/4 ips) of the recordingspeed is desired. The pseudo control track frequencyis

Fp = (100 kHz) - = 137.5 kHz.

RangeofR

1 to 2

2 to 4

4 to 8

8 to 16

16 to 32

32 to 64

64 to 128

K

1

2

4

8

16

32

64

DesiredRecordSpeed(IPS)

1206030157-1/23-3/41-7/8

1206030157-1/23-3/4

1206030157-1/2

120603015

1206030

12060

120

PlaybackSpeed(IPS)

1206030157-1/23-3/41-7/8

6030157-1/23-3/41-7/8

30157-1/23-3/41-7/8

1.57-1/23-3/41-7/87-1/23-3/41-7/8

3-3/41-7/81-7/8

Table for Selection of Constant K

Source: R. A. Hall and R. J. Leifeld ofMcDonnell Douglas Corp.

under contract toMarshall Space Flight Center

(MFS-22972)



ERROR-DECODING ALGORITHM

15

A new error-decoding algorithm provides betterperformance than either sequential or Viterbidecoding of comparable complexity. The amount ofcomputation required is independent of the constraintlength. This allows the use of large values withresulting low-error probability at lower signal-to-noiselevels.

The algorithm is self-starting and recovers from adecoding failure without the transmission of a knownmessage. Since the constraint lengths can be largeenough to span short periods of time, the algorithmwill not be susceptible to fading signals. It is capable

of operating at data rates up to the channel capacity.A prototype decoder has been successfully operated atdata rates of 11 megabits per second.

Source: R. B. Blizard ofMartin Marietta Co.


(MSC-13823)


16

Section 2. Specialized Circuits for Instrumentation

ACTIVE TUNED CIRCUIT

r

Active Tuned Circuit

The circuit shown in the figure is a narrow-band,high-Q, selectively tunable circuit that may easily bedesigned as either a filter, an amplifier, or anoscillator. The low-noise temperature-stable circuitcan be designed for any frequency near the transitionfrequency, F^, of any selected transistor withoutrequiring inductors. Accordingly, the design lendsitself both to high-frequency and to lower frequencyapplications.

In the figure external signal-source Es is applied tothe resistive divider Rt and R2, and to the base of thefirst transistor Q,. Near Ft the impedance presentedat the emitter of Q! is the equivalent of a low-Qinductor. The emitter of Qt is connected to resistor

R3, capacitor Ct, and the base of transistor Q2, and itsimpedance is a combination of negative resistance andcapacitive reactance. The combination of these twoeffects provides a circuit that is well suited formicroelectronic fabrication. The design may be usefulas a low-cost means of reducing the size and weight offilter and oscillator circuits.

Source: Leonard L. KleinbergGoddard Space Flight Center

(GSC-11340)


SPECIALIZED CIRCUITS FOR INSTRUMENTATION 17

LOW-FREQUENCY PEAK DETECTOR

DC Standard

DC Reference

AcquisitionLight

OSignal Input

O O—Output

VoltageInput

Jfdt

IntegratorOutput °~

) Reset VoltageJ_

Input (B)

UniversalCounterFunction

(Time A to B)

Input (A)

_L

Application of Low-Frequency Peak Detector

A new dc measurement device consists ofoperational amplifiers coupled to discrete solid-statecomponents, to generate variable-width low-frequency pulses and to measure integrator currentgain and low-frequency amplitude changes. Normalinstrumentation alone, such as oscilloscopes, Penmotors, and meters, do not offer the accuracy of thenew device.

The equipment (shown in the figure) must be soconnected that uncaging the integrator simultane-ously starts the counter. When the integrator outputequals the dc reference voltage applied to thelow-frequency peak detector, the peak detector outputswitches from negative to positive saturation, stoppingthe counter with a positive-going pulse approximately30 volts in amplitude. The integrator gain (G) is givenby

TiMEwhere time is measured in seconds. The acquisition(AQS) lamp (UT) is lighted whenever the signal inputis greater than the dc reference voltage.

In general, the loop gains of control systems orelectronic networks having dc amplifiers and dcintegrators can be measured with great accuracy in amatter of minutes. The typical accuracy obtainable isapproximately 0.2 percent. The circuit shown in thefigure also can be used to measure control-systemintegrator dc gains and the amplitude of low-frequency positive or negative pulses, with pulse-widths greater than approximately 10 ms and positiveor negative dc peak amplitude.

Source: L. Wright, Jr., D. E. Pack,and D. H. Vickery, Jr., of

Lockheed Electronics Corp.under contract to




INPUT CIRCUIT FOR THERMAL-CONDUCTIVITYGAS-CHROMATOGRAPH DETECTOR

Constant-TemperatureFeedback Loops Differential

Amplifier andFilter

Figure 1. Input Circuit for Thermal-ConductivityGas-Chromatograph Detector

The input circuit of a sensitive gas-chroma-tographic detector has a considerable influence on theoverall performance of the instrument, includingreliability, response, signal/noise ratio, dynamicrange, linearity, the effects of power supply drift, andelectronics temperature drift. A new input circuit hasbeen designed, using a variation on the conventionalwheatstone bridge circuit. It has greater linearity thanconventional input circuits, does not need criticaladjustments, and resists power supply drift. Thiscircuit can be miniaturized and is adaptable tofully-automated remote operation.

Instead of placing the sample and referencethermistors each into one of the two lower arms of thesame Wheatstone bridge, as is normally done, twoindependent resistor bridges are used (Figure 1): onecontaining the reference thermistor, the other thesample thermistor. The output of each bridge isconnected to a separate operational amplifier(op-amp) in a feedback configuration which balancestemperature induced changes in the thermistorresistance by varying tne current flow through the

bridge and thus the voltage drop across thethermistor. In this way the thermistor resistance, theratio of the voltage drop to the current flow, may bekept constant. In this case the circuit is designed tolock the resistance of the sample and referencethermistors at a constant value of 800 ohms,corresponding to a thermistor temperature of 30° C(86° F).

The resultant output signals from the sample andreference bridges are connected to a differentialop-amp and filter circuit with high common-moderejection. As the reference thermistor is maintained insteady-state gas flow conditions, only the differentialsignal resulting from the action of the samplethermistor is amplified.

The operating point of the circuit is highly stablebecause the circuit loadline intersects the thermistorV-I characteristic at almost a right angle (Figure 2).Although the response is less than could be obtainedwith a loadline intersecting at a more acute angle, thechoice taken here is completely free from latchup


o>

8 K Q

.8000

A r

Helium

4 6

Current (mA)

10 12

Figure 2. Static V-l Characteristic of 0.013-in. Diameter ThermistorBead Suspended in a Flow/through Gas Cavity.(The 800-Ohm Leadline Shown Dashed)

states. The output does not reflect supply voltagevariations (a problem in conventional circuits),because of the common-mode rejection of theoperational amplifiers in the constant-temperaturefeedback loops. Thus there is no special requirementfor supply regulation.

Analysis is significantly simplified. The detector/electronics are described by the equation

VVR = K(TT-TD)+PL

where V is the thermistor voltage, R is its resistance,K is a constant proportional to the thermal conduc-tivity of the carrier-plus-unknown, Tj and TD arethermistor and detector temperatures, and PL is straypower loss through the thermistor supports. In

operation, using a helium carrier, R, Tj, and TD areconstants and PL is negligible. K and V make smallexcursions around the operating point, whichaccounts for the linearity of the detector response.Finally, operation of the thermistors at a fixedtemperature permits close specification of thermistormatching at that temperature.

Source: Daniel Webster McMorrisof TRW, Inc.

under contract toLangley Research Center

(LAR-11452)

No farther documentation is available.


INVERTED, VOLTAGE-CONTROLLED OSCILLATOR

-vb

v,

Figure 1. Inverted, Voltage-Controlled Oscillator

The inverted, voltage-controlled oscillator circuitshown in Figure 1 contains two operational amplifiers(Aj and A^, a switching transistor (Qi). a capacitor(C), a reverse protection diode (Dj), and threeresistors (Rj, R2, and R^. The control voltage Vt canbe varied over some range, typically 0.1 to 10 volts.This voltage is fed through resistor Rl to the invertinginput of amplifier A!. Transistor Ql in the off stateallows voltage Vl to appear at the negative input of At

and in the on state Qx shorts the inverting input of Ajto common.

The transistor, Q1; is controlled by the output ofamplifier Aj. When the voltage at the inverting inputof AI is positive, V2is negative; when it is negative, V2

is positive. This causes the output of amplifier Al tolatch in either the positive or the negative state. Theoutput V2 changes state only when the differencevoltage between the inputs changes sign. This signchange is caused by the second amplifier A2.Amplifier A2 is used as an integrator, with theintegration rate controlled by the level of V2. Theoutput, V3, of this integrator is fed to the positiveinput of At. The circuit will now oscillate with thewaveforms shown.


V2 When V, = V

1/2 V-

V2 When V, = 1/2 V+va

0-

-vh

-1/2 t

Figure 2. Output Waveforms

The relationship between the input voltage and theoutput frequency may be seen in Figure 2. The graphV3 shows the output of the integrator as a function oftime. Note that the large triangular wave and thesmall triangular wave have the same slopes. With thisin mind, assume that Vt is equal to Vx volts. Theintegrator will integrate between 0 and +VX volts andwill cycle over a period T. Now if Vt is reduced toV/2, the period T is reduced by one-half. Thus theperiod of oscillation is directly proportional to theinput voltage V^ and since the reciprocal of thefrequency is equal to the period, V^ must be inverselyproportional to the frequency. Graph V2 shows thesame relationship for voltage V2.

The circuit is an efficient means of converting ananalog signal to an inverse digital signal. It isconstructed from a small number of components andwould therefore be economical to produce. It shouldbe of interest to those concerned with informationtransfer systems.

Source: James R. CurrieMarshall Space Flight Center

(MFS-22924)



INTEGRABLE POWER GYRATOR

Input

ComplementaryOutput Stage

O Output

out

O 0V

Simplified Circuit Diagram Of The Noninverting VCCS

Gyrators have been in existence for some time now.Synthesis of gyrators by different methods such as avoltage-controlled current-source (VCCS) approach,decomposition of the Z-matrix, approaches usingoperational amplifiers, etc., has produced gyratorshaving very low efficiency on the order of 1 percent.The result has been that these gyrators cannot handlesignals above several milliwatts without excessivedissipation of dc power.

A further study of the Y-matrix (VCCS) approachand the Z-matrix configuration has led to develop-ment of efficient, dependable high-quality gyrators.The basic configuration used for the Y-matrix gyratorcomprises two essentially similar VCCS's in a loopwith one producing a 180° phase reversal and theother producing zero phase change. This circuit isreciprocal, and the input signal may drive either theamplifier with phase reversal or the one without.

The basic circuit of the noninverting VCCS isshown in the figure. It consists of the differentialamplifier, the complementary output stage, and thecurrent/voltage converter connected in a feedbackloop. The current/voltage converter performs thesame function as the ordinary gyration resistor inconventional gyrators: it produces a voltage that isproportional to the output current. This voltage is fedback to the differential amplifier: This type offeedback is called current proportional voltagefeedback which stabilizes the VCCS transconductanceand, at the same time, enhances the output resistanceof the output stage and the input resistance of thedifferential amplifier. The configuration providesstable transconductance and high input and outputresistances which are all necessary for a high qualityY-matrix gyrator.


In general, high efficiency of the circuit is providedby the following:1. Class B output stage2. Small current flow through gyration resistors RI

and R4 as compared with the output current3. Current flow through the differential amplifier and

of the transistors Qj and Q2 is small compared tothe output current.

Performance of this current with a 10-V supplyvoltage may be summarized as follows:1. Voltage amplification factor = 6002. Transconductance = 1.8 millisiemens3. Output resistance = 300 kilohms4. Input resistance > output resistance5. Efficiency = 38 percent.

The inverting VCCS is essentially similar to thenoninverting one. However, to invert the phase, theinputs of the differential amplifier have to beinterchanged. Since the feedback has to stay negative,further phase reversal in the feedback path isnecessary. This is accomplished by insertion ofanother differential amplifier connected as an inverter(amplification factor = -1). Because the efficiency ofthe inverting VCCS is also 38 percent, efficiency of thecomplete circuit is 19 percent - a significantimprovement over the previous 1 percent.

The Z-matrix gyrator incorporates the same basicbuilding blocks of the Y-matrix type but combinesthem in a different way. As in the case of theY-gyrator, the output of each differential amplifier isconnected to a complementary output stage which in

turn is connected to a current/voltage converter. Thecurrent/voltage converter produces a voltage that isproportional to the current flowing into the corre-sponding port (input or output) of the gyrator (seefigure). This voltage, however, is not fed back to thedifferential amplifier, but drives either directly or byinsertion of an inverter (voltage gain = -1) to thenoninverting input of the other differential amplifier.In order to ensure a low output resistance and a highinput resistance, the output voltage at each port of thegyrator is fed back to the inverting input of thecorresponding differential amplifier.

Results from either approach have been favorable.With further improvements in design details,efficiency of the new gyrators may now approach thetheoretical limit of 78.5 percent. This will allowhandling of signals of considerable power withmoderate dc power dissipation. Improvements inquality factor Q have reached 300 for Y-matrix and1300 for Z-matrix gyrators. Finally, both designs arecomparatively easy to integrate by implementing thesame technology as used with conventional oper-ational amplifiers.

Source: E. Hochmair ofNational Academy of Sciences


(MFS-22342)



LOW-NOISE INSTRUMENTATION AMPLIFIER FORLOW-FREQUENCY APPLICATIONS

+12.6 V

FN1201

14.7 M

Detector

FN1201

•Resistors are ±1% Metal FilmLow-Drift (100 ppm/°C)

10 K-

4.7 M

Notes:All Resistor Values Are OhmsAll Capacitor Values Are piFAll Diodes Are IN3600All Operational Amplifiers

Are SSS725B

.6 V

Low-Noise Instrumentation Amplifier

The instrumentation amplifier shown in the figurecan recover low-frequency, low-amplitude geophysicalsignals. The characteristics of the amplifier includelow 1/f noise, high common-mode rejection, highinput impedance, and high gain stability for changesin temperature and supply voltage.

A matched pair of field-effect transistors, selectedfor low 1/f noise, and a current source comprise thedifferential-input section of the amplifier. The secondstage of the amplifier is a differential-input,differential-output stage made with commercialamplifiers. The cross-coupled feedback from thesecond stage to the input section establishes the gainof the first two stages. The final stage of the amplifieris a signal subtracter.

The amplifier has a midband gain of 1815. Gain isdown 3 dB at 1.5 and 500 Hz. The common-moderejection is greater than 90 dB from 4 to 500 Hzwithout resistor trimming. Equivalent input noisevoltage is 14 nV/\ff from 20 to 500 Hz, with 1/f noiseevident below 20 Hz. Equivalent input noise voltageincreases to 35 nV/\ff at 5.78 Hz, the signalfrequency for which the amplifier was designed.

Source: Dale M. Sipma and Charles S. Martin ofHughes Aircraft Co.


(LAR-11407)



RAPID BATTERY ACTIVATION AND CELL-BY-CELLVOLTAGE MEASUREMENT

A device has been developed to simultaneouslyactivate batteries and evaluate their performance.Previous methods required a separate activationprocedure, either cell by cell, using a syringe, or on anactivation rack. Such methods required more timeand could not provide a cell-by-cell electrical checkduring activation.

The new device combines these two operations. It isclamped on top of the battery, forming a vacuum-tight seal between itself and the battery cells. Aprobe-plate makes contact with each cell terminal. Apreviously measured quantity of electrolyte then ispoured into the compartments located immediately

above each cell. The top of the device is placed intoposition and is sealed with rapid-connect/disconnectclamps. A vacuum is applied to force electrolyte intoeach cell. At the same time the vacuum is applied,voltage measurements are made on each cell to noteany irregularities.

Source: W. J. Britz and W. A. BoshersMarshall Space Flight Center

(MFS-22749)


SCATTEROMETER PREPROCESSOR SYSTEM

The well-known techniques used in microwave-processor spectrum unfolding and spectral analysis(doppler filtering) can now be applied to resolveproblems in microwave scatterometry. A microwavesignal preprocessor is now developed to preprocess thedata from several scatterometers. Its advantages arethat it reduces the computer preprocessing time,permits a quick-look display, and verifies the data; italso eliminates analog-to-digital conversion.

Functionally the preprocessor can be considered asa two-part system: (1) a signal manipulation section,comprising a single sideband modulator mixer and alow-pass filter network, and (2) a processor-and-display section, consisting of a digitizer and a multi-plexer. Sideband modulation unfolds the spectrum ofthe outputs of several scatterometers, which is thenanalyzed by mixing and low-pass filtering with a set of

generated frequencies. This spectral analysis is thennormalized, multiplexed and digitized for recording,and finally projected as a real-time display. As asubstantial improvement in the state of the art, thistechnique can be useful to engineers and techniciansconcerned with the design and maintenance ofairborne ground-mapping and doppler radars.

Source: R. E. Chapman, K. L. Dienes, D. G. Killion,H. C. Loewer, and W. F. Smith of

Teledyne Ryan Aeronautical1


(MSC-13734)



SOLID-STATE POWER SWITCH

Input

Figure 1. Darlington, PNP-NPN Compound Amplifier

A new solid-state power switching circuit providesan efficient means of switching power to high-currentloads. The switch provides a low-impedance pathbetween the power source and the load.

The dc power switch shown in Figure 1 is aDarlington, pnp-npn compound amplifier consistingof three transistors. Resistors R1 and R2 provide bias.The switch is a combination of two common transistorcircuits. Qt and Q2 form a direct-coupled pnp-npncompound amplifier with feedback, with Qt and Q3 ina Darlington amplifier configuration. The inherentadvantages of each circuit result in a very efficientpower switch that could be used in solid-state remotepower controllers, circuit breakers, relays, and relateddevices.

The design takes advantage of the low collector-to-emitter voltage (Vce) of a simple saturated transistorat low and rated load currents and the Darlingtonefficiency at higher load currents. When the loadcurrents are at rated values or below, the primarypower transistor Qi operates in the saturated state(Figure 2) with a low Vce, (typically 200 mV or less).

The base-to-emitter junction of transistor Q2 is inreverse bias, blocking Q3 collector current. Thustransistor Qj obtains the necessary base currentthrough the emitter-base junction of Q3.

Using typical circuit voltage values

VCCl = 200 mV,Vbe, = 700 mV, andVCg3 < 100 mV,

the base-to-emitter voltage of Q2 is -600 mV. Thebase-to-emitter junction of transistor Q2 is thereforereverse biased. Area 1 of Figure 3 shows the low VCCl

values exhibited when the compound power switch isoperating in the saturated state.

When VCCl increases enough to forward-bias thebase-to-emitter junction of Q2, collector current isconducted through Q2 and Q3. VCCl must be greaterthan 800 mV before the base-to-emitter junction of Q2

will be forward biased. To be fully conducting,however, Vbe2 must be on the order of 700 mV.

Vce,(SaturatedMode)

out

r i'load! <> R|0ad

I

4

Figure 2. Compound Amplifier in Saturated Mode


TransitionRegion

VC6l (Volts)

1.5-

1.0-

0.5-

Satu ratedMode

CompoundMode

lload (Amperes)

Figure 3. VC6l Versus l|oad Characteristics

Therefore, the voltage between the collector and theemitter of transistor Qj must be approximately 1.5Vdc to benefit fully from the efficiency of thecompound switch. The resultant increase in the basecurrent of Qi further inhibits the rapid increase ofVCCl. This is a result of diverting the base current ofQ! through Q2 to the load.

The effect is to maintain Qi at a relatively low VCCl

for high or overload currents. Furthermore, the Q2

and Q3 collector currents flow through the poweroutput terminal (Eou^) to the load to increase theefficiency of the power switch. Unlike conventionalswitches, this mode of operation reduces power lossescaused by a major increase in the base current of Qi,due to the additional conduction through thecollector-to-emitter junction of Q2. This increasedcurrent flows through the load resistor and does notreduce the efficiency of the compound switch. TheVCCl characteristics of the compound amplifier in fullconduction are shown in area 2 of Figure 3.

The significant advantages of the compound powerswitch over conventional switches are higher effi-ciency, higher input impedance, and higher overallswitch gain. These advantages result in furtherdesirable qualities, such as a reduction of thermalstresses within the components, a smaller physicalpackage, a reduced loading of base drive circuits, andeasier feedback control.

Source: D. E. WilliamsMarshall Space Flight Center and

L. C. Maus ofSperry Rand Corp.


(MFS-22880)



IMPULSE COMMUTATING CIRCUIT WITHTRANSFORMER TO LIMIT REAPPLIED VOLTAGE

From SourceL1

SCR1

/•C

s

T7

i

^A^A>

^W>12

LSCR3 ~A

i i

CapacitorRechargeCircuit

i

o'

k SCR4 J

»\ T v v v T ""

CurrentSensor

- SCR2To Load

Figure 1. Basic Commutating Circuit

A new circuit to achieve commutation of aswitching silicon controlled rectifier (SCR) has beendeveloped to open a circuit with currents flowing up tovalues of 30 amperes. This circuit utilizes a newconcept of switching, which halves both current andvoltage in the middle of the commutating cyclethereby lowering the size and weight requirements.

The commutating circuit has performed success-fully throughout the temperature range of 218 to373 K (-67 to 212° F). It can be turned on or off bycommand and will remain on in the absence of a loaddue to the continuous gate.

A schematic diagram of the commutating circuit isshown in Figure 1; its operation is illustrated in Figure2. In operation, SCR 1 carries the load current.Capacitor C is precharged to 450 volts in the polarityshown. A manual shut down or trip level overcurrentis sensed at the time t0. SCR 2 is triggered on at thistime dumping the capacitor across LI and driving theanode of SCR 1 negative so that it stops conductingalmost instantly. The current flowing through LIcontinues to flow but now goes through SCR 2. Whenthe voltage on SCR 1 comes up to zero at time tj, thevoltage has been negative on SCR 1 long enough tokeep SCR 1 from conducting with no gate even thoughthe voltage on the anode is now reapplied in thepositive direction.

At time t2, the voltage on the capacitor is zero andthe current through the inductor is at maximum. SCR3 is now gated on. Until this time, L2 has been in anopen circuit with no current flow. Now that currentcan flow through L2, the magnetic field in theinductor is the same but the number of windings hasdoubled so that the current, almost instantly, goes tohalf the peak value. The oscillation of the circuitcontinues at half the frequency. The current flowsthrough LI and L2 in series, which have capacitorvoltage across them, so that SCR 2 now has half thecapacitor voltage across it, in reverse. Thus, it isturned off. The same voltage is applied to SCR 1; i.e.,half of the voltage that would be applied if SCR 3 didnot conduct. This permits lower ratings for SCR 1.

As the oscillation continues, the current goesthrough zero and SCR 4 is gated on to permit thecurrent to flow in the opposite direction. This is attime t3. The capacitor is now charged to a voltagerepresenting the energy of its initial charge plus theenergy stored in the inductor LI at time t0, exclusiveof losses. At time t4, the voltage across SCR 1 is backdown below source voltage, the capacitor voltage isgoing through zero, and SCR 4 is carrying maximumcurrent. By time ts, the capacitor is nearly recharged(except for losses), SCR 3 is turned off, current ceases


+300 V -

SCR1Voltage °

-150 V -

CapacitorCurrent

CapacitorVoltage

Figure 2. Principal Waveforms of Commutating Circuit

to flow and the voltage on SCR 1 goes back to sourcevoltage. The circuit is now reset and is nearly ready tobe turned on again. In reality, the charge on thecapacitor will be built up to its final precharge valueby the capacitor recharge power supply before it isdesirable to turn the circuit on again. The wholecommutation cycle takes place in less than1/2-millisecond and occurs with no reference to thereturn circuit of the power source so that minimumtransient disturbances are caused.

The commutation circuit is ideal for use in directcurrent switching where SCR's are used as theprinciple switching element, because the networkinterrupts the supply and load current immediatelyupon initiating the commutation cycle. The circuitdoes not induce transient current in the supply or load

and limits the transient voltages. This solid stateinnovation should have potential use in spacecraft andaircraft electrical systems, in transportation systems,and in hazardous areas such as mining. Thecommutation scheme can also be extended to choppercircuits where the voltage is controlled by switchingand filtering.

Source: J. H. McConvilleMartin Marietta Corp.

under contract toLewis Research Center

(LEW-11849)



OVERLOAD CONTROL CIRCUIT FOR REVERSING SPLIT-PHASE MOTORS

Limit Switch(Extend)

115 Vac

CentrifugalSwitch ) Motor

Winding

Overload Control Circuit

A non-flight-rated seat-positioning system incorpo-rated into a flight simulator utilizes two split-phasemotors on each seat: one for tilt and one for forward-and-aft travel. If the motors are direct wired to theseat position switch, current surges and circuit-breaker activation may result if the direction of seattravel is rapidly reversed.

A novel circuit provides an inexpensive solution tothis problem. When the seat positioning switch isactivated, the centrifugal switch in the motor (seefigure), together with relays, causes the motor todecelerate prior to reversing direction. If the seatswitch is positioned FWD, relay K2 closes, heavy-dutyrelay K3 latches, and the motor drives the seatforward. The centrifugal switch then opens, and thusrelay K2 opens. The motor begins to decelerate.

Now assume that the seat switch is positioned AFT.Relay Kt closes and relay K3 opens. The motorcontinues to decelerate until the centrifugal switchcloses again, at which time relay K2 closes and relay

K3 again latches. The motor reverses direction; andthe seat moves AFT until the centrifugal switch againopens, causing the motor to again decelerate and relayK2 to open. The seat switch is then returned to theOFF position, and relays KI and K2 open.

The problem could also be solved by installingservomotors rated to handle the peak loads. However,this would be significantly more expensive. Thiscircuit could be used in other situations to permit theuse of available motors not rated to handle the peakloads, which occur during field-reversed times/periods.

Source: F. R. Yerian and W. F. Iceland ofRockwell International Corp.


(MSC-19405)



PULSE-GENERATING NETWORK FOR MAGNETOPLASMA DYNAMIC THRUSTERS

Although there are existing networks that generatedesired pulse shapes, the experimental network shownin Figure 1, using a closely packed spiral pattern ofcapacitors, is exceptionally compact and light. Itstores enough energy so that the full potential ofquasi-steady magneto plasma dynamic (MPD) thrust-ers is realized (high-power operation for a long-enough period to establish steady operating condi-tions). In addition, the network may have applicationin high-powered pulse laser systems.

A substantial reduction in the size and weight ofsuch circuits can be obtained by eliminating the bulkyand heavy induction coils ordinarily required. For agiven total length of conductor, circuit inductance canbe increased by arranging the leads in a spiral so thatthe current in each of the loops is in the samedirection about the centerpoint. By stacking thecapacitors as closely together as possible, the size ofthe conductor loops is reduced, while the number ofturns used in forming the connections is increasedcorrespondingly. The result is a net increase ininductance with a minimal increase in conductorlength beyond what is required to connect thecapacitors. Thus, in addition to savings in weight andbulk, there is a reduction in resistive power loss.

To Load

t1T_LT1

1T1T1T

1

i

?~~

1

4=T

1T1T17

1+

_TT+-T-

|To Load

1 "

Figure 1. Experimental Pulse-Generating NetworkWith Capacitors Connected in a SpiralPattern That Increases Bus-Bar Inductance

Figure 2. Arrangement of Conductors ConnectingThree Rows of Capacitors in a MannerThat Increases Network Inductance

With circuits that depend on bus-bar geometry forinductance, pulse shaping is accomplished by movingthe connection point of the flexible capacitor leads todifferent locations on the bus bar. When theconnection spacing is widened, more of the bus bar isutilized for inductance in that particular mesh. Theaction is similar to that obtained with the rail-and-slide type of adjustment that is used with theladder-type networks.

A pulse generator, with a nominal 5000 jouledischarge, was constructed from 60 electrolyticcapacitors arranged as those in Figure 2. Itsdimensions were 107 cm (42 in.) long and 46 cm (18in.) in diameter when enclosed in a protectivecanister. The generator weighed about 140 kg (308Ib). With an initial charge of 400 volts, the dischargecurrent was 25 to 30 kiloamps for about a millisecond.When operating at one pulse per second, the numbersof pulses required to reach a temperature of 50° C(122° F) were 4500 and 700, for charge levels of 200and 400 volts respectively.

Source: A. C. Ducati ofGeotel, Inc.


(LAR-11033)



HIGH-SPEED ANALOG SWITCH FOR CRT-DISPLAYSTROKE-WAVEFORM GENERATORS

DigitalX-Slope

Input

DigitalY-Slope

Input

XWaveform

YWaveform

DigitalVideo NInput

High-

DelayLine

Speed Switch

VideoOutput

Stroke-Waveform Generator Using DAC Switches

The slow switching transients of a digital-to-analogconverter (DAC) limit its applicability as a switch inalphanumeric-waveform generator circuits to thosethat produce symbols in an average time of 10microseconds or more. A faster analog switchingsystem for a high-speed stroke-waveform generatorfor CRT display is shown in the figure. The circuit canbe incorporated into both existing and new designs forhigh-speed alphanumeric-generator and vector-generator circuits using DAC switching and widebandanalog integrators.

The principal switching element of the device is adigital-to-analog converter (DAC) that produces aswitched stroke slope current that is applied to an

impulse filter. The filter attenuates spikes before thecurrent enters the integrator. The circuit increasesspeed in digital-to-analog switched integration by afactor of five. It produces symbols in an average timeof 2 microseconds per character, or 100 nanosecondsper stroke, with low distortion.

Source: M. E. Casciolo ofUnited Aircraft Corp.


(MSC-14547)



IMAGE ENHANCER FOR AIRBORNE SCANNERS

BUFFER

VideoIn

0 /1 V7

UnprocessedVideo In

Output

ORT

BUFFER

-EZDOutput

Base

ORT/ W/i I

BUFFER

Output

-^VWW ^) /ORT

f^w^r.

Image Enhancer

The image enhancer diagramed in the figure en-ables contrast enhancement of selected portions ofa video transmission to provide magnified thermalresolution over a wide range of temperature.Temperature differences of 0.01° C (0.02° F) can beresolved over a 100° C (180° F) range. All signalsbelow an output reference threshold (ORT) areinhibited; all signals above the ORT are amplifiedaccording to the gain setting on each of the threeamplifiers. All signals above a maximum permissibleamplitude set on each of the three amplifiers areclipped.

Threshold and gain adjustments are stable sincethey are contained within feedback loops. Quantita-tive information is obtained after post-flight calibra-tion due to gain stability and temperature accuracy.This is the first known use of such a device on infraredscanners.

Source: R. W. O'Neill andR. F. Merkel of

Lockheed Electronics Co.under contract to




IMPROVED ELECTRON-GUN BEAM DEFLECTION AND FOCUSING

0.25-^F CapacitorCharge Level

Time

Pulsing Points

Figure 1. High-Voltage Power-Supply Commutation Voltage

When a high-current electron gun is aimed at apoint target and pulsed, the accelerating potentialprovided by the power source drops, due to theno-load to full-load current demand. Figure 1 showsthe three-phase commutation waveform of the high-voltage power supply. A 0.25-(^F capacitor at theoutput charges up to its peak value when no current isdrawn. When the beam is pulsed, drawing current,the capacitor loses its charge and the voltage drops.After this initial drop, the voltage is dependent on theoutput impedance, that is, the current drawn and thecommutation voltage of the power supply. Thus, if thebeam is pulsed at three different points, as shown inFigure 1, the voltage drops in these three cases aredifferent, since they occur at three different phases ofthe commutation voltage.

The drop in voltage has two effects: (1) change inbeam focus and (2) deflection of the beam. Because ofthe uneven voltage drops, there is no point at which anoperator can direct and focus the beam. Referring to

Figure 1, if the beam is focused and directed when thepulse occurs at point 2, both the focus and thedirection are different when the pulse occurs at points1 or 3. Conventional methods of correcting thisproblem, by adding additional capacitors to theoutput of the power supply, are expensive. Also, in theevent of a short circuit or arcing inside the electrongun, the capacitor discharge can damage the gun orthe associated wiring. This system monitors theoutput voltage drop, and the beam is cut off when apredetermined voltage drop is reached. Thus, thevoltage drop is held to a constant and manageablelevel, and the aim of the electron gun is improvedunder pulsed conditions.

Figure 2 illustrates the circuit used to achieve beamequalization. The cathode voltage is attenuated 1000times and ac coupled, blocking the dc component sothat only the fluctuation of voltage is passed. Thisvoltage variation is amplified and applied to a Schmitttrigger, which can be adjusted to fire at a particularcathode voltage. The output of the Schmitt trigger isapplied to a gate via a monostable multivibrator, theoutput of which is normally a logic 1. When theexternal pulser applies a logic 1, it is passed throughthe gate and inverted to produce a pulse at the outputof the level changer/amplifier, which turns on thebeam.

When the voltage at the input of the Schmitt triggerfalls to a level determined by the variable resistor onits input, the trigger fires, changing the state of themultivibrator and closing the gate. This ensures thatthe cathode voltage always falls to the same potentialand minimizes defocusing and drift. The multi-vibrator remains set for 10 milliseconds. This delayserves to prevent the gate from being enabled again onthe same external trigger pulse. This could occur ifthe cathode voltage is allowed to rise to the pointwhere the Schmitt trigger resets, before the externalpulse ends.


>+5 V

AC-Coupled IHigh Voltage(Attenuated 1000 Times)

V

100

100PF

I <> 2.2 K<> <

\ ]

I

I>> 1.5 K

-^WV-n

t1 — II — '

4.7 K<<

I>> 2.2 K

^VW-i

I i

\

•>.4 K<•f

~l

270 pF

680

SCHMITT TRIGGER

To GridPulsingNetwork

MonostableMultivibrator

Note: All Resistances in Ohms.

Level Changerand Amplifier

Figure 2. Beam Equalization Circuit

It should be noted that the total energy in the beamwill vary for each pulse. For a particular application,the energy variation should be observed and, if theminimum available energy is less than that required toperform a particular function, the beam current canbe increased. In many applications this variation ofenergy is of no particular significance.

Source: S. K. Dalai ofWyle Laboratoriesunder contract to

Langley Research Center(LAR-11475)



VIDEO PEAK/AVERAGE DETECTOR

Peak

CameraVideo Signal

Input Output

Note: All Resistances in Ohms -6.3 V

Video Peak/Average Detector

A new circuit detects either peak or average signals.The mode of operation can be switched by asingle-pole, double-throw switch. The circuit (shownin the figure) can be used in automatic light-controlsystems for television cameras, where the video outputmust be constant over large ranges of input light level.

The main advantage of this circuit is that it does notrequire the conventional double-pole, double-throwswitch. In addition, an operational amplifier (op-amp) with feed-back makes the device precise andtemperature stable. The detector is basically aunity-gain, inverting amplifier with feedback. Com-ponents shown in the figure, but not described, areused for biasing and stabilization.

In the peak mode one side of capacitor Ct isgrounded. When a positive-going video signal isapplied to the input, the other side of Cj is chargednegatively by the op-amp through transistor Qj. Thecharging process stops when the output is the negativeequivalent of the positive input peak. Between peaksthe voltage on Q decays through R2 and Rj and notthrough Q1( because Q! emitter has no positivereturn. Thus Qt acts as a rectifier. R3 sets the chargetime so that when a minimum-width input pulse isreceived the circuit cannot detect it. In practical terms

this limits the portion of a scene highlight that can bepeak detected.

In the average mode, Ct is connected in parallelwith the feedback resistor R2. Then the circuit acts asa low-pass filter, and the output is a dc potential equalto the input average.

A positive voltage return path for the emitter of Qt

is not necessary. This path is provided by R2 into theinverting input of the operational amplifier. Theelimination of a positive voltage return for Qj emittermakes the circuit unique. It allows Ql to play a dualrole: a rectifier in the peak mode, an emitter-followerin the average mode. Thus no additional switching isrequired at Q_I. In addition, since the output of thedetector is the feedback point, temperature variationsin the emitter-base drop of Qt are automaticallycompensated.

Source: J. D. Bingley ofRCA Corp.


(MSC-14482)


SPECIALIZED CIRCUITS FOR INSTRUMENTATION

FAST LOW-POWER-DRAIN LOGIC CIRCUITS

-1.5V

I = 10 mA

37

To Other Inputs

^

Input AO—

Input Bo—

DRIVESTAGES

-OA-B Out

-O A-B Out

'240 240 240 240

Note: All Resistances Are in Ohms.T

AND - NAND Gate

The AND-NAND gate logic circuit in the figure hasa fast (in the nanosecond range) response time, a low(in the milliwatt range) power drain, and does not usetunnel diodes. Tunnel diode circuitry, althoughexhibiting low power drain and fast response time, isdifficult to manufacture because of the severetemperature limitations imposed by the tunnel diode.

In addition to the 240-ohm output impedancecircuit in the figure, a bistable version of the samelogic family as well as an AND-NAND gate with a50-ohm output impedance and a power drain of7.2 mW have been investigated. The circuits may beconstructed using a power supply with opposite

polarity. Instead of npn transistors, pnp transistorsare used to obtain signals of opposite polarity.

Two features of the circuits are believed to be new:(1) the use of current switching with a feedbackarrangement, giving a snap-on effect, and (2) theoperation of a fast, reliable logic circuit with a singlesupply voltage as low as 1.25 V.

Source: Giro A. CancroGoddard Space Flight Center

(GSC-11366)



RANDOM AUTOMATIC SEQUENCING WITHOUT A MEMORY

+15 V

100 K

100 K

SD1-WNoiseDiode

CommandWord

CommandPulses

CommandEnable

Note: All Resistances Are in Ohms.

Digital Pulses WithRandom Sizes;-0.5 to 5 V)

TIT-—1 1TTTFixed Word

BinaryCounter

Random Automatic Sequence Circuit


The circuit illustrated in the figure randomly selectsone of 16 modes each time power is applied to asystem, without the use of a nonvolatile memory orpermanently applied power. This circuit was designedto keep a system operating in the event of a computerfailure. Three lines connect the system to thecomputer. All three lines must be operating in orderto inhibit the random-word generator. If one or moreof these lines fail, the sensing logic triggers amonostable multivibrator that turns on a noisegenerator for several milliseconds. Each time it isoperated, the noise generator provides a differentnumber of pulses to a four-stage counter, producing adifferent 4-bit word each time.

The 4-bit word is shifted into a fixed-lengthcommand register after the monostable multivibrator

pulse has terminated; the other bits in the commandregister are transferred from a fixed, preset wordregister at the same time. These other bits containsystem parameters that remain fixed during therandom selection of system modes. The circuit hasapplication as a random-number generator forstatistical applications, such as the automatic randomselection of production items for acceptance testing.

Source: Jules J. Dishler and David F. Stout ofMartin Marietta Corp.


(LAR-11080)

No farther documentation is available.


COMPLEMENTARY MOS FOUR-PHASE,LOGIC CIRCUITS

'9 ho

(htr\ '

0- .»..-..-. (

__ 13 14 -

ir2

— &J

....::.::

JL ......

*THn-

tii 1 1 o11 i i

. tl^ t t A - • -

Figure 1. Complementary Four-Phase Clock Waveforms

Logic circuits often use a four-phase clocking tech-nique in conjunction with p-channel MOS (metaloxide semiconductor) devices to charge and dischargecapacitors without providing a direct path from thepower supply to ground. This arrangement savesconsiderable power compared to circuits having a loadresistor between the power supply and ground.However, the p-channel, four-phase circuit hasseveral disadvantages. Since it requires a four-phaseclock, it cannot be used as a subassembly in a single-phase clock system without making prior provision forthe clock generation. In addition, p-channel, four-phase circuits require two power supply voltageswhich makes it difficult to interface these circuits withother types.

A complementary four-phase logic can provide afour-phase clock signal from a single-phase clock andrequires only one power supply voltage.

The circuit uses complementary MOS devices asswitches which charge and discharge capacitors inaccordance with circuit requirements, but without adirect connection between the power supply andground. Figure 1 shows the four-phase clock wave-forms, and Figure 2 is a schematic of the four-phasecircuits.

The Type 2 circuit described in detail as an exampleoperates as follows: during clock time t! to tz (Figure1), <t>! turns transistor Q3 (Figure 2 - Type 2) on andholds transistor Q2 off. This changes capacitor C2 to+Vrj)]> From time t3 to t4, <J>i turns Q3 off and <J>2

turns Q2 on. If at this time the input to Qt (LOGIC2)is a logic "1" (+VDD). 0.2 and Qt will form aconductive path which discharges C2 to ground orlogic "0". If, however, the input to Qt is a logic "0"(ground is zero volts), then C2 remains charged to+VDD (logic "1"). The voltage on C2 or the output of


VDD + VDD

LOGIC! , |Q12

0-11

Out I

i_JQio|N —L- N -- <ko |

A ,h—'&o |N

LOGIC4 Q7

Type 1 Type 2 Type 3 Type 4

Figure 2. Complementary Four-Phase Circuits

this circuit then remains unchanged and is validduring time t4 to t9. This circuit thus operates as aninverter which is precharged during tj to t2, evaluatedduring t3 to t4, and valid during t4 to t9.

The Type 3 circuit operates in a similar manner andis also an inverter; it is precharged during t3 to t4,evaluated during t5 to tj, and valid during t4 to t9.Circuit Type 4 is similar to Type 2, and Type 1 similarto Type 3.

The four-phase clock waveform can be generated bythe circuit from a single phase input. This can be donebecause the complementary inverter has a finite andpredictable propagation delay. Thus, the output of

the inverter is the inverse of the input, but is delayedby a small time. The output of a number of inverterscan be joined in series and connected to logic gates toproduce the required four-phase clock pulses shownin Figure 1.

Source: H. L. Petersen and D. K. Kinell ofLockheed Missiles and Space Co.


(MSC-14240)


42

Patent Information

The following innovations, described in this Compilation, have been patented orare being considered for patent action as indicated below:

Four-Phase Differential Phase Shift Resolver (Page 2) MSC-14065and

Complementary MOS Four-Phase Logic Circuits (Page 40) MSC-14240These inventions are owned by NASA, and a patent application has been filed.

Inquiries concerning nonexclusive or exclusive license for their commercialdevelopment should be addressed to:

Patent CounselJohnson Space CenterCode AMHouston, Texas 77058

Digital Phase-Locked Loop (Page 4) GSC-11623This invention is owned by NASA, and a patent application has been filed.

Inquiries concerning nonexclusive or exclusive license for its commercial developmentshould be addressed to:

Patent CounselGoddard Space Flight CenterCode 704.1Greenbelt, Maryland 20771

Phase-Detecting, Self-Directing Digital Couplers: A Concept (Page 10) MFS-24426and

Flexible Playback Speed Control for Tape Recorded Data (Page 14) MFS-22972and

Inverted, Voltage-Controlled Oscillator (Page 20) MFS-22924and

Integrable Power Gyrator (Page 22) MFS-22342and

Rapid Battery Activation and CeO-by-Cell Voltage Measurement(Page 25) MFS-22749

andSolid-State Power Switch (Page 26) MFS-22880

Inquiries concerning rights for the commercial development of these inventionsshould be addressed to:

Patent CounselMarshall Space Flight CenterCode CC01Marshall Space Flight Center, Alabama 35812

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