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Electronic System Level Design Introduction to SystemC Maziar Goudarzi
Electronic System Level
Design
Introduction to SystemC
Maziar Goudarzi
2009 ESL Design 2
Today Program
SystemC (ver. 1.0)History
Highlights
Design methodology
A simple SystemC example
2009 ESL Design 3
SystemC
v0.90Sep. 99
SystemC History
SynopsysATG
Synopsys“Fridge”
Synopsys“Scenic”
UCIrvine
1996Frontier Design
A/RT Library1991
SystemC
v1.1
Jun. 00
Abstract Protocols
IMEC
1992
CoWare“N2C”
1997
VSIA SLD Data Types Spec (draft)
SystemC
v1.0Apr. 00
Fixed Point Types
SystemC History (cont’d)
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SystemC
v1.1
Jun. 00
SystemC
v2.0 specFeb. 01
SystemC
v2.0 LRM
Jun. 03
SC 2.1
TLM 1.0
Jun. 05
IEEE Std.
1666-2005
Dec. 05
SystemC
v2.2
Apr. 07
TLM
v2.0 Lib.
Jun. 08
TLM 2.0 LRM
v2.0.1 Lib
Jul. 09
Abs. portsDyn. processTimed events
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SystemC Highlights
Modules
Processes
Ports
Signals
Rich set of port and signal types
Rich set of data types
Clocks
Cycle-based simulation
Multiple abstraction levels
Communication protocols
Debugging support
Waveform tracing
Features as an ESL Design language
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Conventional
System Design Methodology
C/C++ System Level Model
Analysis
Results
Refine VHDL/Verilog
Manual Conversion
Simulation
Synthesis
Rest of Process
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Conv. System Design
Methodology (cont’d)
Problems
Errors in manual conversion from C to HDL
Disconnect between system model and HDL model
Multiple system tests
C/C++ System Level Model
Analysis
Results
RefineVHDL/Verilog
Manual Conversion
Simulation
Synthesis
Rest of Process
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SystemC Design Methodology
SystemC Model
Simulation
Refinement
Synthesis
Rest of Process
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SystemC Design
Methodology (cont’d)
Advantages
Refinement methodology
Written in a single language
Higher productivity
Reusable test benches
Executable (compiled) event-driven simulation
Compare to interpreted simulation
Compare to compiled simulation
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SystemC (ver. 1.0)
programming model
A set of modulesinteracting through signals.
Module functionality is described by processes.
Mod 1 Mod 2
Mod 3
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SystemC Programming Model
(cont’d)
System (program) debug/validation
Test bench
Simulation, Waveform view of signals
Normal C++ IDE facilities
Watch, Evaluate, Breakpoint, ...
sc_main() function
instantiates all modules
initializes clocks
initializes output waveform files
starts simulation kernel
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SystemC Programming Model
(cont’d)
SystemC is C++
Any C++ statement is allowedcout, cin, file I/O, etc
In principle, any C++ compiler can be used
MS VC++ 6.0 (VS-2008, 20xx!) for windows
GCC for Linux
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SystemC Basic Building Block
SC_MODULE( <module_name> ) {
// declaring port types
sc_in<int> in;
// definition of processes
void entry() {
// circuit functionality
}
SC_CTOR( <module_name> ) {
// declaring processes
SC_METHOD(entry);
sensitive<<in;
}
};
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General Structure of SystemC
Models
SC_MODULE( inverter ) {
sc_in<bool> in;
sc_out<bool> out;
void entry() {
out = !in.read();
static cntr=0;
cout<<cntr++<<“\n”;
}
SC_CTOR( inverter ) {
SC_METHOD(entry);
sensitive<<in;
}
};
int sc_main(int, char*[])
{
inverter not_gate(“A_NOT_GATE”);
sc_clock an_alternating_signal;
not_gate.in( an_alternating_signal );
sc_start(5);
}
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A Simple Example:
Defining a Module
Complex-number Multiplier(a+bi)*(c+di) = (ac-bd)+(ad+bc)i
ComplexMultiplier
(cmplx_mult)
ab
c
d
e
f
SC_MODULE(cmplx_mult) {
sc_in<int> a,b;
sc_in<int> c,d;
sc_out<int> e,f;
...
}
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Example: Defining a Module
(cont’d)
SC_MODULE(cmplx_mult) {
sc_in<int> a,b;
sc_in<int> c,d;
sc_out<int> e,f;
void calc();
SC_CTOR(cmplx_mult) {
SC_METHOD(calc);
sensitive<<a<<b<<c<<d;
}
};
void cmplx_mult::calc()
{
e = a*c-b*d;
f = a*d+b*c;
}
ComplexMultiplier
(cmplx_mult)
ab
c
d
e
f
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Completing the Design
M2
ComplexMultiplier
ab
cd
ef
M1
input_gen
M3
display
clk
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Test Bench:
input_gen module
SC_MODULE(input_gen) {
sc_in<bool> clk;
sc_out<int> a,b;
sc_out<int> c,d;
void generate();
SC_CTOR(input_gen) {
SC_THREAD(generate);
sensitive_pos(clk);
}
};
void input_gen::generate()
{
int a_val=0, c_val=0;
while (true) {
a = a_val++;
wait();
c = (c_val+=2);
wait();
}
}
M2
ComplexMultiplier
a
b
c
d
e
f
M1
input_gen
M3
display
clk
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Test Bench:
display module
SC_MODULE(display) {
sc_in<int> e,f;
void show();
SC_CTOR(display) {
SC_METHOD(show);
sensitive<<e<<f;
}
};
void display::show()
{
cout<<e<<„+‟<<f<<“i\n”;
}
M2
ComplexMultiplier
ab
cd
e
f
M1
input_gen
M3
display
clk
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Putting it all together:
sc_main function
#include <systemc.h>
int sc_main(int, char*[])
{input_gen M1(“I_G”);cmplx_mult M2(“C_M”);display M3(“D”);
sc_signal<int> a,b,c,d,e,f;sc_clock clk(“clk”,20,0.5);
M1.clk(clk.signal()); M1.a(a); M1.b(b);M1.c(c); M1.d(d);
M2.a(a); M2.b(b); M2.c(c); M2.d(d); M2.e(e); M2.f(f);
M3.e(e); M3.f(f);
sc_start(100);return 0;
}
M2
ComplexMultiplier
ab
cd
e
f
M1
input_gen
M3
display
clk
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How to Compile & Run It?
1. Compile SystemC class library to generate systemc.lib (required just once)
2. Create a MS VC++ project & add your source files
3. Add systemc.lib to your project4. Add c:\systemc-2.0.1\include to the
default “include directory” (in project-settings)5. Enable “Run-Time Type Information (RTTI)”
(in your project-settings)6. Compile & run. Enjoy SystemC!
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The Generated Output
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What we learned today
What’s SystemC
SystemC advantages
SystemC programming model
Modeling hardware in SystemC
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Other notes:
SystemC Installation
SystemC source files
http://www.systemc.org
Course web-page under “resources” tab
Our reference version: SystemC 2.2.0 unless otherwise specified
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Other Notes
Exercise (do before next lecture):
Download and compile SystemC 2.2.0 sources
Compile and run (simulate) today simple example
