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Introduction to CMOS VLSI Design Circuits & Layout
Introduction toCMOS VLSI
Design
Circuits & Layout
Circuits and Layout Slide 2CMOS VLSI Design
Outline CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams
Circuits and Layout Slide 3CMOS VLSI Design
CMOS Gate Design Activity:
– Sketch a 4-input CMOS NAND gate
Circuits and Layout Slide 4CMOS VLSI Design
CMOS Gate Design Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
DY
Circuits and Layout Slide 5CMOS VLSI Design
Complementary CMOS Complementary CMOS logic gates
– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS
pMOSpull-upnetwork
outputinputs
nMOSpull-downnetwork
Pull-up OFF Pull-up ONPull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
Circuits and Layout Slide 6CMOS VLSI Design
Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
Circuits and Layout Slide 7CMOS VLSI Design
Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS
Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel
A
B
Y
Circuits and Layout Slide 8CMOS VLSI Design
Compound Gates Compound gates can do any inverting function Ex:
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
Y = (A.B + C.D)’
Circuits and Layout Slide 9CMOS VLSI Design
Example: O3AI Y = ((A+B+C).D)’
Circuits and Layout Slide 10CMOS VLSI Design
Example: O3AI Y = ((A+B+C).D)’
A B
Y
C
D
DC
B
A
Circuits and Layout Slide 11CMOS VLSI Design
Signal Strength Strength of signal
– How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0
– But degraded or weak 1 pMOS pass strong 1
– But degraded or weak 0 Thus nMOS are best for pull-down network
Circuits and Layout Slide 12CMOS VLSI Design
Pass Transistors Transistors can be used as switches
g
s d
g
s d
Circuits and Layout Slide 13CMOS VLSI Design
Pass Transistors Transistors can be used as switches
g
s d
g = 0s d
g = 1s d
0 strong 0Input Output
1 degraded 1
g
s d
g = 0s d
g = 1s d
0 degraded 0Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
Circuits and Layout Slide 14CMOS VLSI Design
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
Circuits and Layout Slide 15CMOS VLSI Design
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
g = 0, gb = 1a b
g = 1, gb = 0a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1, gb = 0
g = 1, gb = 0
Circuits and Layout Slide 16CMOS VLSI Design
Tristates Tristate buffer produces Z when not enabled
EN A Y0 00 11 01 1
A Y
EN
A Y
EN
EN
Circuits and Layout Slide 17CMOS VLSI Design
Tristates Tristate buffer produces Z when not enabled
EN A Y0 0 Z0 1 Z1 0 01 1 1
A Y
EN
A Y
EN
EN
Circuits and Layout Slide 18CMOS VLSI Design
Nonrestoring Tristate Transmission gate acts as tristate buffer
– Only two transistors– But nonrestoring
• Noise on A is passed on to Y
A Y
EN
EN
Circuits and Layout Slide 19CMOS VLSI Design
Tristate Inverter Tristate inverter produces restored output
– Violates conduction complement rule– Because we want a Z output
A
YEN
EN
Circuits and Layout Slide 20CMOS VLSI Design
Tristate Inverter Tristate inverter produces restored output
– Violates conduction complement rule– Because we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
Circuits and Layout Slide 21CMOS VLSI Design
Multiplexers 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X
0
1
S
D0
D1Y
Circuits and Layout Slide 22CMOS VLSI Design
Multiplexers 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1Y
Circuits and Layout Slide 23CMOS VLSI Design
Gate-Level Mux Design How many transistors are needed?
1 0 (too many transistors)Y SD SD
Circuits and Layout Slide 24CMOS VLSI Design
Gate-Level Mux Design How many transistors are needed? 20
1 0 (too many transistors)Y SD SD
44
D1
D0S Y
4
2
22 Y
2
D1
D0S
Circuits and Layout Slide 25CMOS VLSI Design
Transmission Gate Mux Nonrestoring mux uses two transmission gates
Circuits and Layout Slide 26CMOS VLSI Design
Transmission Gate Mux Nonrestoring mux uses two transmission gates
– Only 4 transistorsS
S
D0
D1YS
Circuits and Layout Slide 27CMOS VLSI Design
Inverting Mux Inverting multiplexer
– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
Circuits and Layout Slide 28CMOS VLSI Design
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Circuits and Layout Slide 29CMOS VLSI Design
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes– Or four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
Circuits and Layout Slide 30CMOS VLSI Design
D Latch When CLK = 1, latch is transparent
– D flows through to Q like a buffer When CLK = 0, the latch is opaque
– Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
Circuits and Layout Slide 31CMOS VLSI Design
D Latch Design Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
Circuits and Layout Slide 32CMOS VLSI Design
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
Circuits and Layout Slide 33CMOS VLSI Design
D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
Flop
CLK
D Q
D
CLK
Q
Circuits and Layout Slide 34CMOS VLSI Design
D Flip-flop Design Built from master and slave D latches
QM
CLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
Circuits and Layout Slide 35CMOS VLSI Design
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
Circuits and Layout Slide 36CMOS VLSI Design
Race Condition Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late– Sees first flip-flop change and captures its result– Called hold-time failure or race condition
CLK1
D Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2
Circuits and Layout Slide 37CMOS VLSI Design
Nonoverlapping Clocks Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew We will use them in this class for safe design
– Industry manages skew more carefully instead 1
11
1
2
22
2
2
1
QMQD
Circuits and Layout Slide 38CMOS VLSI Design
Gate Layout Layout can be very time consuming
– Design gates to fit together nicely– Build a library of standard cells
Standard cell design methodology– VDD and GND should abut (standard height)– Adjacent gates should satisfy design rules– nMOS at bottom and pMOS at top– All gates include well and substrate contacts
Circuits and Layout Slide 39CMOS VLSI Design
Example: Inverter
Circuits and Layout Slide 40CMOS VLSI Design
Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40
Circuits and Layout Slide 41CMOS VLSI Design
Stick Diagrams Stick diagrams help plan layout quickly
– Need not be to scale– Draw with color pencils or dry-erase markers
Circuits and Layout Slide 42CMOS VLSI Design
Wiring Tracks A wiring track is the space required for a wire
– 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track
Circuits and Layout Slide 43CMOS VLSI Design
Well spacing Wells must surround transistors by 6
– Implies 12 between opposite transistor flavors– Leaves room for one wire track
Circuits and Layout Slide 44CMOS VLSI Design
Area Estimation Estimate area by counting wiring tracks
– Multiply by 8 to express in
Circuits and Layout Slide 45CMOS VLSI Design
Example: O3AI Sketch a stick diagram for O3AI and estimate area
– Y = ((A+B+C).D)’
Circuits and Layout Slide 46CMOS VLSI Design
Example: O3AI Sketch a stick diagram for O3AI and estimate area
– Y = ((A+B+C).D)’
Circuits and Layout Slide 47CMOS VLSI Design
Example: O3AI Sketch a stick diagram for O3AI and estimate area
– Y = ((A+B+C).D)’
