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C. E. Stroud Combinational Logic Design (1/06) 1

Elementary Logic Gates

A Z

01

10

ZA

Inverter

(NOT Gate) AZ

B

AND Gate

010

001

1

0

A

11

00

ZB

OR Gate

110

101

1

0

A

11

00

ZB

AZ

B

Name

Symbol

Truth

Table

Logic

EquationZ = A = A Z = A B = AB Z = A + B

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C. E. Stroud Combinational Logic Design (1/06) 2

Other Elementary Logic GatesNAND Gate

(NOT AND)

110

1011

0A

01

10ZB

NOR Gate(NOT OR)

010

0011

0A

01

10ZB

ZA

BA

BZ

Name

Symbol

Truth Table

Logic EquationZ = (A B) = AB Z = (A + B) = A+B

AB

Z AB

Z

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C. E. Stroud Combinational Logic Design (1/06) 3

Using Truth Tables to Prove Theorems DeMorgans Theorems

011

001

010

100ZYX

011

101

110

100ZYX

T8a: (X+Y) = XY T8b: (XY) = X+Y

X

Y

Z

NAND

X

Y Z

X

Y

Z

NOR

X

YZ

alternate

logic symbols

X

Y

Z

NOR

X

Y

Z

NAND

a NOR gate is

equivalent to

an AND gate

with inverted

inputs

a NAND gate is

equivalent to

an OR gate

with inverted

inputs

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C. E. Stroud Combinational Logic Design (1/06) 4

Other Logic GatesExclusive-OR Gate

aka XOR Gate

110

101

1

0

A

01

00

ZB

010

001

1

0

A

11

10

ZB

Exclusive-NOR Gate

aka XNOR or NXOR Gate

ZA

B Z

A

B

Z = AB = AB + AB Z = AB = A B + AB

also denotedZ = A B

A Z

11

00

ZA

BufferName

Symbol

TruthTable

Logic

EquationZ = A

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C. E. Stroud Combinational Logic Design (1/06) 5

Interesting Properties of Exclusive-OR Controlled inverter

X0=X

X1=X

XOR with one input inverted = XNOR

X

Y=X

Y=(X

Y) XNOR with one input inverted = XOR

(XY)=(XY)=XY

Constant outputXX=0

XX=1

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C. E. Stroud Combinational Logic Design (1/06) 7

Functionally Complete Set of Gates If any digital circuit can be built from a set of

gates, that set is said to befunctionally complete Functionally complete sets of gates:

AND, OR, & NOT

NANDNOR

Multiplexers

To show a set of gates is functionally complete,we must show that you can construct AND, ORand NOT functions

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C. E. Stroud Combinational Logic Design (1/06) 8

Functionally Complete Set of Gates

A Z=A

The NAND gate is

functionally completeWe can build any digital logic

circuit out of all NAND gates

Same holds true for the NORgate and the multiplexer

The XOR & XNOR are not

functionally complete

Z=ABA

B

Z=A+B

using DeMorgans Theorem

A

B

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C. E. Stroud Combinational Logic Design (1/06) 9

Gate-level Representations SOP expressionsAND-OR

With inverters for

complemented literalsZ=ABC+ABC+ABC+ABC

aka 2-level AND-OR logicrepresentation

POS expressionsOR-AND

With inverters forcomplemented literals

Z=(A+B+C)(A+B+C)(A+B+C)(A+B+C)

aka 2-level OR-AND logicrepresentation

Z

A

B

C

A

B

C

Z

8 gates

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C. E. Stroud Combinational Logic Design (1/06) 10

Gate Level Representation

from Boolean equationZ = (((AB)C)+D)= ((AB)C)+D

B

D

A

ZC

A (AB)

((AB)C)

D

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C. E. Stroud Combinational Logic Design (1/06) 11

Circuit Analysis Going from gate-level totruth table

Apply 0s & 1s to inputs to get outputs

Boolean equation

Move equations to output

Z=(A+B)C+ABC=AC+BC+ABC

Z

A

BC

A+B(A+B)C

ABC

B

A

C

1

0

10

0

1

1

0

Z

111

011

101001

110

010

100

000

CBA

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Circuit Analysis We can implement different circuits for same logic function that are

functionally equivalent(produce the correct output response for allinput values)

Which implementation is the best? Depends on design goals and criteria

Area analysis

Number of gates, G (most commonly used)

Number of gate inputs and outputs, GIO (more accurate) Bigger gates take up more area

Performance analysis (worst case path from inputs to outputs)

Number of gates in worst case path from input to output, GdelMore accurate delay measurement per gate

Propagation delay = intrinsic (internal) delay + extrinsic (external) delay

Relative prop delay,Pdel= # inputs to gate (intrinsic) + # loads (extrinsic)

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Circuit Analysis Example From previous example:

Z=(A+B)C+ABC# gates: G = 7

# gate I/O: GIO = 19

Gate delay: Gdel= 4

worst case path: BZ

Prop delay:Pdel= 12 worst case path: BZ

Z

A

B

C

A+B(A+B)C

ABC

B

A

C

2

2

2 1+1

1+1

1+1

2+1

2+1

3+1

2+0

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C. E. Stroud Combinational Logic Design (1/06) 14

Circuit Optimization Obviously we want smallest, fastest circuit

Some Basic Goals:Minimizing # product terms minimizes # of AND

gates and # inputs to OR gate in a 2-level SOP

(AND-OR) representation

Minimizing # literals in each product term

minimizes # inputs to its AND gate We can use postulates & theorems, but

It would be nice to find a more reliable procedure