ELEN0040 – REPETITION 1

Boolean algebra

Reminders

■ F : Boolean function❑ Boolean variables (binary) : 0/1❑ Logic operators : AND, OR, NOT

Reminders

■ F : Boolean function❑ Boolean variables (binary) : 0/1❑ Logic operators : AND, OR, NOT

algebraic expression :

X . Y X Y Xtruth table : 0/1logical circuit :

AND OR NOT

Reminders

■ F : Boolean function❑ Boolean variables (binary) : 0/1❑ Logic operators : AND, OR, NOT

■ Goal : simplify the circuit equivalent to F❑ fewer components❑ smaller electronic board❑ Gain in reliability❑ Gain in speed

® Lower cost and better performance

The basic identities

1 variable

1. X + 0 = X2. X . 1 = X3. X + 1 = 14. X . 0 = 05. X + X = X

6. X . X = X7. X + X = 18. X . X = 09. X = X

Rem : X=X’=~X

The basic identities

Multiple variables

10. X + Y = Y + X11. X + (Y + Z) = X + Y + Z12. X . (Y + Z) = X . Y + X . Z13. X . Y = Y . X14. X . (Y . Z) = X . Y . Z15. X + (Y . Z) = (X + Y) . (X + Z)

→ X + (X . Y) = X . (X + Y) = X

The basic identities

De Morgan’s Theorem

X1 + X2 + … + Xn = X1 . X2 . … . Xn

X1 . X2 . … . Xn = X1 + X2 + … + Xn

Consensus Theorem

X.Y + X.Z + Y.Z = X.Y + X.Z(X + Y) . (X + Z) . (Y + Z) = (X + Y) . (X + Z)

Exercise 13

■ a) X + XY

■ b) X . (X+Y)

■ c) ABC + ABC + ABC

Exercise 13 (cont.)

■ d) ABC + ABC + ABC + ABC + ABC

Exercise 13 (cont.)

■ e) (A+C+D) (A+C+D) (A+C+D) (A+B)

Exercise 13 (cont.)

■ f) (A+B) . (A+B) =

Your turn!

■ g) (CD+A) + A + AB + CD =

■ h) [(X+Z) . (X+Z) . Y] + [(X+Z) + (Y+Z)] =

Determine the negation of F (= F) in 2 different ways

■ Truth table : 0 « 1

■ Apply De Morgan on the boolean expression of F

Exercise 14

■ F =

■ F =

Truth TableA B C F F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

NOTOR

ANDOR

Exercise 15a

■ F = BC + A(B+C)

■ F =

Truth TableA B C F F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Additional exercises (15b – 15c)

■ F = (M + N) . (M + P) . (N + P)

■ F = [ (AB) . A ] . [ (AB) . B ]

Implement in an optimal way

■ Edit/Simplify the boolean expression

■ Schematize using logical gates

■ Minimize (compromise):❑ The number of levels ® delay❑ The number of gates ® size

Single logical gates with networks of pull-down switches

INV 2-NAND = A.B 2-NOR = C+D 2-NAND+INV=2-AND

Series : logical « AND » // : logical « OR »

Rem: CMOS technology: 2 transistors to build 1 switch

Implement in an optimal manner

■ Edit/Simplify the boolean expression

■ Schematize using logical gates

■ Count:❑ The number of levels❑ The number of transistors

■ INV : 2 transistors■ n-NAND, n-NOR : 2n transistors■ n-AND (= n-NAND + INV),

n-OR (= n-NOR + INV) : 2n + 2 transistors

Exercise 16a

■ F1 = AB + AB + AC

Exercise 16b

■ F2 = (A + B) (CD + CD)

Exercise 16c

■ F3 = (RST) (R+S+T)

Universal gates : NAND and NOR

■ NAND : F = A.B = A + B

■ NOR : F = A + B = A.B

AB

F AB

F

AB

F AB

F

F = SUM [OF PRODUCTS]

F = PRODUCT [OF SUMS]

How to make an inverter with a NAND/NOR gate ?

EX. 19 Implement the circuit using NAND gates

EX. 20 Implement the circuit using NOR gates

EX.21 Under which conditions X=1 MEM=0 ?

EX.22 Under which conditions X=1 ?

XOR and NXOR■ XOR A.B + A.B = A B

■ NXOR A.B + A.B = A B

AB

AB

The result of a XOR gate with n input variables is 1 if and only if an odd number of input variables are equal to 1.

XOR = PARITY TEST

EX.23 Show that A xor B xor C = A xor ( B xor C )

A B C F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A xor B xor CA B C F0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

A xor (B xor C)