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Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
CMOSManufacturing
Process
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
CMOS Process
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
CMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Patterning on Si
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Semiconductor fabrication (1)
2
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Semiconductor Fabrication (2)
1
4
3
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Semiconductor Fabrication (3)
3 3
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Semiconductor Fabrication (4)
END
4
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Circuit Under Design
This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Circuit Layout
Inverter 2 Inverter 1D1
D2 D4
S2
D3
S4
S1 S3
GND
Vdd
G1
G2 G4
G3
pMOS-2pMOS-1
nMOS-2nMOS-1
IN1 OUT2OUT1 IN2
IN2=OUT1
B4B2
B3B1
Inverter 1nMOS-1pMOS-1
Inverter 2nMOS-2pMOS-2
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Start Material
Starting wafer: n-type withdoping level = 10 13/cm3
* Cross-sections will be shown along vertical line A-A’
Si n-type
nMOS
pMOS
A
A’A A’
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
N-well Construction
(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist
Si n-type
photoresist
silicon nitridesilicon dioxide
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
N-well Construction
(4) Expose resist using n-well mask
Si n type
Exposed resist
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
N-well Construction
(5) Develop resist(6) Etch nitride and(7) Grow thick oxide
Si n type
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
N-well Construction
(8) Implant n-dopants(phosphorus)
(up to 1.5 m deep)
thick oxide
n-well
Si n type
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
P-well Construction
Repeat previous steps
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Grow Gate Oxide
Gate oxide55 nm thin
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Grow Thick Field Oxide
Uses Active Area mask
Is followed by threshold-adjustingimplants
Field Oxide0.9 m thick
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Polysilicon layer
Polysilicon Deposition
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Source-Drain Implantsn+ source-drain implant(using n+ select mask)
photoresist
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
n+ source-drain implant(using n+ select mask)
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Source-Drain Implants
p+ source-drain implant(using p+ select mask)
Si n type
n-well p-well
pMOS nMOSGB SD BGS D
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Contact-Hole Definition
(1) Deposit inter-level Dielectric(SiO2) — 0.75 m
(2) Define contact openingusing contact mask
Si n type
n-well p-well
pMOS nMOS
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Aluminum-1 Layer
Aluminum evaporated (0.8 m thick)
followed by other metal layers and glass
GBG
SD BGS D
IN
OUT
pMOS nMOS
Vdd GND
IN OUT
nMOS
pMOS
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Advanced Metalization
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Intel 0.09 m Generation
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Downsizing MOSFET below 0.1 m
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Design Rules
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Design Rules
Interface between designer and process engineer
Guidelines for constructing process masks Unit dimension: Minimum line width
» scalable design rules: lambda parameter» absolute dimensions (micron rules)
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Intra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Transistor Layout
1
2
5
3
Tra
nsis
torTransistor
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Via’s and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995Manufacturing ProcessManufacturing Process
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5