© Copyright 2018 Xilinx
Presented By
Tony McDowell
System Software & SoC Solutions – Product and Technical Marketing
Embedded Software Strategy &
Development
© Copyright 2018 Xilinx
If Microsoft ever does applications for
Linux it means I've won.
-Linus Torvalds, 1998
When software developers drive
hardware design it means adaptable
SoC’s have won.
-Xilinx, 2018
© Copyright 2018 Xilinx
ARM Cortex-A72
PSM - Services
Hypervisor (Optional)
AI
Engine
Loader ROM
ARM Cortex-R5
PMC Loader Firmware
PMC - Services
ARM Trusted Firmware
U-Boot
Linux
NoC PLPMC /
PSM
ARM Cortex-A53
Hypervisor (Optional)
BootROM
ARM Cortex-R5
FSBL
PMU Firmware
ARM Trusted Firmware
U-Boot
Linux
PL GPU PMU
ARM Cortex-A9
BootROM
FSBL
U-Boot
Linux
Programmable Logic
© Copyright 2018 Xilinx
How Do You Want to Do This?
______ _ _ _ | ___ \ | | | | (_) | |_/ /__| |_ __ _| | _ _ __ _ ___ __| __/ _ \ __/ _` | | | | '_ \| | | \ \/ /| | | __/ || (_| | |___| | | | | |_| |> < \_| \___|\__\__,_\_____/_|_| |_|\__,_/_/\_\
fetch build integrate package
deploy
© Copyright 2018 Xilinx
˃ GitHub.com/Xilinx
˃ Nearly 100 repositories
˃ All of our embedded software stack
˃ All of our Yocto recipes
˃ Scripts for Vivado
˃ Tutorials and Examples
Open and Public Code
© Copyright 2018 Xilinx
ATF v1.6
v2019.01
v4.11
v2.6 (Thud)
v4.19
The same for every device family!
Staying Up-to-Date
© Copyright 2018 Xilinx
Rebase Kernel Tree
˃ Merge-Tree
Merges two separate branches into a single new branch going forward
Lose the history of what was different between the branches
˃ Rebase Tree
Creates a series of patches that can be applied cleanly to the HEAD node
Maintain history of development in the separate development paths
˃ Single upstream kernel version per year
˃ Rebase patchsets with Vivado releases
˃ Rolling merge tree
© Copyright 2018 Xilinx
Compilers and Toolchains
˃ AArch32 – ARMv7 – Zynq-7000
˃ AArch64 – ARMv8 – Zynq UltraScale+, Versal
˃ Cortex-R5 – ARMv7 – Zynq UltraScale+, Versal
Linaro GCC 7.3.1
˃ MicroBlaze – MMU / Linux Configuration
˃ MicroBlaze – Microcontroller Configuration
crosstool-NG GCC 7.3.1
GCC 8 Support in 2019
© Copyright 2018 Xilinx
Enabling Yocto
˃ meta-xilinx – BSP support for Xilinx device families
˃ meta-xilinx-tools – Yocto infrastructure to interface with Xilinx tools
˃ meta-petalinux – Infrastructure to replicate the default PetaLinux root filesystem
© Copyright 2018 Xilinx
GitHub Sources
meta-xilinx
meta-xilinx-tools
meta-petalinux
Integrating with Yocto
© Copyright 2018 Xilinx
Abstracting Yocto
______ _ _ _ | ___ \ | | | | (_) | |_/ /__| |_ __ _| | _ _ __ _ ___ __| __/ _ \ __/ _` | | | | '_ \| | | \ \/ /| | | __/ || (_| | |___| | | | | |_| |> < \_| \___|\__\__,_\_____/_|_| |_|\__,_/_/\_\
D
T
S
export deploy
ab
stra
cte
d
© Copyright 2018 Xilinx
˃Working toward certifiability˃Reducing code Size
˃Dom0-less boot ˃Automatic static partitioning
Multiprocessing with Xen
© Copyright 2018 Xilinx
Jailhouse on Zynq UltraScale+ MPSoC
˃ Done by Xilinx partner ENEA
˃ Runs on standard SMP Linux
without PREEMPT_RT
˃ Small and fast (<10k LoC)
˃ Simplifies running bare-metal
code on Linux systems
© Copyright 2018 Xilinx
OpenAMP and Interprocessor Comms
˃ Built on standard remoteproc and rpmsg infrastructure
˃ Open and public on GitHub.com/OpenAMP
Master
Core
Linux
RTOS / Bare-
Metal
Remote
Core
rpmsg
OpenAMPremoteproc /
rpmsg
remoteproc
Remote
Core
Linux
RTOS / Bare-
Metal
Master
Core
rpmsg
OpenAMPremoteproc /
rpmsg
Master
Core
RTOS / Bare-
Metal
RTOS / Bare-
Metal
Remote
Core
rpmsg
OpenAMPOpenAMP
© Copyright 2018 Xilinx
FPGA Manager
Programmable
Logic
Internal
Programming
Interface
(PCAP)
ATFPMUFW
XilFPGALinux
$ /sys/class/fpga_manager/fpga0/
© Copyright 2018 Xilinx
Xilinx Wiki
Open Support
Mailing Lists
Xilinx Forums
Xilinx KB
Community
Portal
© Copyright 2018 Xilinx
New Community Portal
˃ Xilinx.com/community
˃ Centralized Clearinghouse
References other resources, doesn’t replace them
˃ Increasing number of developers use Open
Source Content
Converge content and make navigation to desired location easier
˃ Xilinx has lots of Open Source content to
filter
GitHub, AWS, Wiki, Ultra96
© Copyright 2018 Xilinx
One more thing…
© Copyright 2018 Xilinx
Project A
2019.1
SW
Components A
Project A
2019.2
SW
Components A
Interchange
Vivado Open
FormatPetaLinux
D
S
A XSCT
2019.X+
Vivado
D
S
APetaLinux
T
C
L
Decoupled from Vivado
Tightly coupled with Vivado
2018.3
rootfs
2019.x
kernelUpdate
U-boot
FSBL
bitstream
rootfs
2019.x+
kernel
U-boot
FSBL
bitstream
Package Update
Package Repo
Decoupling PetaLinux Projects
Decoupling Runtime Components
Decoupling Linux from Vivado
Decoupling Packages from Each Other
© Copyright 2018 Xilinx