Jaeyong Chung
System-on-Chips (SoC) Laboratory
Incheon National University
Embedded System Design
Lecture 6
A communication system that transfers data between
components inside a computer, or between computers
A single set of wires (aka lines) used to connect two or
more components (bus hardware)
Unlike a typical wire in a processor, a bus can communicate in
different directions at different times.
A communication protocol (bus software)
What is a bus?
Control
Datapath
Memory
Processor
Input
Output
[David Culler]
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Examples AHB (Advanced High-Performance Bus)
APB (Advanced Peripheral Bus)
IEEE1394
USB (Universal Serial Bus)
PCI (Peripheral Component Interconnect)
PCI Expresses
SATA (Serial ATA)
SCSI (Small Computer System Interface)
ISA (Industry Standard Architecture)
Ethernet (LAN)
….
.....
There are various buses of different scales components
(CPU, Memory, IO devices, computers) in computing
systems are attached a bus
Bridge
Core
SRAM
USB Keyboard
USB Mouse
BridgeLANAdaptor
HDD1
HDD2
Computer 2
Eth
ern
et
AHB
SATA
USB
What is a bus?
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System Bus Configurations
Multiple busses allow
parallelism:
Slow devices on one bus
Fast devices on separate
bus
A bridge connects two
busses
CPU slow device
memory
high-speed
device
bri
dge
slow device
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Advantages of Buses
Versatility New devices can be added easily
Peripheral devices can be moved between computer
systems that use the same bus standard
Low Cost A single set of wires is shared in multiple ways
Provides a way to manage the complexity of design Device only has to implement the bus standard.
MemoryProcessor
I/O
Device
I/O
Device
I/O
Device
[David Culler]
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Disadvantage of Buses
It creates a communication bottleneck
Bus bandwidth can limit the maximum I/O throughput
The maximum bus speed is largely limited by:
The length of the bus
The number of devices on the bus
The need to support a range of devices with:
Widely varying latencies
Widely varying data transfer rates
MemoryProcessor
I/O
Device
I/O
Device
I/O
Device
[David Culler]
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The General Organization of a Bus
Control lines:
Signal requests and acknowledgments
Indicate what type of information is on the data lines, if there are
errors, etc.
Data lines carry information between the source and the
destination:
Data
Addresses
Complex commands
Data Lines
Control Lines
[David Culler]
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Typical Bus Transaction
1. Various components request access to bus
2. One is selected (it becomes the bus master for this
transaction)
3. The master puts an address and request type (e.g.
read or write) on the bus
4. The master and the addressed component (slave)
send data one way or the other (depending on request
type)
5. The bus master signals that it’s done.
Return to step 1
Bus
Master
Bus
Slave
Master issues command
Data can go either way
[David Culler]
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Synchronous vs Asynchronous Bus
Synchronous Bus:
Control and data signals move with respect to a common clock
(usually one of the bus control lines)
Advantage: low latency & high bandwidth.
Disadvantages:
Every device on the bus must run at the same clock rate
To avoid clock skew, bus cannot be long if it is fast
Asynchronous Bus:
It is not clocked
It can accommodate a wide range of devices
It can be lengthened without worrying about clock skew
Communication protocol is more complicated
[David Culler]
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Buses so far ...
°°°Master Slave
Control Lines
Address Lines
Data Lines
Bus Master: has ability to control the bus, initiates transaction
Bus Slave: module activated by the transaction
Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information.
Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing.
Synchronous Bus Transfers: sequence relative to common clock.
[David Culler]
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How do you decide which component will be the bus master - the one that initiates a bus transaction?
The simplest solution: The processor is the only bus master
Major drawback: the processor is involved in every transaction.
Multiple masters:
A bus master wanting to use the bus makes a request
It cannot use the bus until its request is granted
It must release the bus when it’s finished
PCI bus (and others) use “request” and “grant” signals
Bus Arbitration: Choosing a Master
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Bus Arbitration: Choosing a Master
Bus arbitration schemes must to balance 2 factors:
Bus priority: highest priority device should be serviced first
Fairness: even the lowest priority device should never be
completely locked out from the bus
Bus arbitration schemes can be divided into four broad
classes:
Distributed arbitration by self-selection:
each device wanting the bus places an id code on the bus.
they all follow the same protocol to choose master
Distributed arbitration by collision detection (e.g. Ethernet)
Daisy chain arbitration
Centralized arbitration
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Daisy Chain Bus Arbitration
Advantage: simple
Disadvantages
Doesn’t assure fairness
A low-priority device may be locked out indefinitely
The daisy chain grant signal also limits the bus speed
Bus
Arbiter
Device 1
Highest
Priority
Device N
Lowest
Priority
Device 2
Grant Grant Grant
Release
Request
wired-OR
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Centralized Arbitration
Used in essentially all processor-memory busses and
in high-speed I/O busses
Bus
Arbiter
Device 1 Device NDevice 2
Grant Req
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Increasing the Bus Bandwidth
Use separate address lines and data lines
Address and data can be transmitted in one bus cycle
Cost: more bus lines
Increase bus width
By increasing the width of the data bus, transfers of multiple words
require fewer bus cycles
Example: SPARCstation 20’s memory bus is 128 bit wide
Cost: more bus lines
Block transfers (Burst mode)
Allow the bus to transfer multiple words in back-to-back bus cycles
Only one address needs to be sent at the beginning
Bus isn’t released until the last word is transferred
Cost: (a) increased complexity
(b) decreased response time for request
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Summary of Bus Options
Option High performance Low cost
Bus width Separate address Multiplex address
& data lines & data lines
Data width Wider is faster Narrower is cheaper
(e.g., 32 bits) (e.g., 8 bits)
Transfer size Multiple words has Single-word transfer
less bus overhead is simpler
Bus masters Multiple Single master
(requires arbitration) (no arbitration)
Protocol Pipelined Serial
Clocking Synchronous
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Example: AHB
pipelining
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Activity
Draw a timing diagram for the below case
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Example: AHB
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Example: AHB
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Activity
Design a AHB bus using muxes
Master#1
Arbiter
Slave #1
Decoder
HADDR
HWDATA
HRDATA
HADDR
HWDATA
HRDATA
Master#2
HADDR
HWDATA
HRDATA
Master#3
HADDR
HWDATA
HRDATA
Slave #2
HADDR
HWDATA
HRDATA
Slave #3
HADDR
HWDATA
HRDATA
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ARM AMBA bus
Two varieties
AHB is high-
performance.
APB is lower-speed,
lower cost.
AHB supports
pipelining, burst
transfers, split
transactions, multiple
bus masters
All devices are slaves
on APB
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DMA
Direct memory access (DMA) performs data transfers
without executing instructions
CPU sets up transfer
DMA engine fetches, writes
DMA controller is a separate unit
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Bus Mastership
By default, CPU is bus master and initiates transfers.
DMA must become bus master to perform its work.
CPU can’t use bus while DMA operates.
Bus mastership protocol:
Bus request.
Bus grant.
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DMA Controllers in PXA320
[PXA320 Developer Manual] Peripherals on system bus,
such as the LCD controller, camera interface, graphics
controller, mostly use their own internal DMA controller
to access the system
The exception is the data flash controller, which uses
the system DMA controller to transfer data
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DMA Operation
CPU sets DMA registers for start address, length.
DMA status register controls the unit.
Once DMA is bus master, it transfers automatically.
May run continuously until complete.
May use every nth bus cycle.
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ARM AMBA bus
Two varieties:
AHB is high-performance.
APB is lower-speed, lower cost.
AHB supports pipelining, burst transfers, split transactions,
multiple bus masters.
All devices are slaves on APB.
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ARM AMBA bus
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