EMBEDDED SYSTEMS-I_O PROGRAMMING.ppt

7/18/2019 EMBEDDED SYSTEMS-I_O PROGRAMMING.ppt

http://slidepdf.com/reader/full/embedded-systems-io-programmingppt 1/33

8051 MICROCONTROLLER

I/O PROGRAMMING

EMBEDDED SYSTEMS



1234

5678910111213141516171819

20

40393837

363534333231302928272625242322

21

P1.0P1.1P1.2P1.3

P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2

(INT1)P3.3

(RD)P3.7

(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)

P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)

EA/VPP ALE/PROG

PSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)

P2.0(A8)

8051(8031)



Pins of I/O Port

The 8051 has four I/O ports

Port 0 （ pins 32-39）： P0（ P0.0～ P0.7） Port 1（ pins 1-8）： P1（ P1.0～ P1.7） Port 2（ pins 21-28）： P2（ P2.0～ P2.7） Port 3（ pins 10-17）： P3（ P3.0～ P3.7） Each port has 8 pins.

Nae! P0." （"#0$1$...$7） $ P1."$ P2."$ P3."

E%： P0.0 is the &it 0（ '()） of P0 E%： P0.7 is the &it 7（*()） of P0

These 8 &its for a &+te.

Each port can &e use! as input or output ,&i-!irection.



I/O Port Programming

Port 1（ pins 1-8）

Port 1 is !enote! &+ P1. P1.0 P1.7

e use P1 as e%apes to sho the operations on ports.

P1 as an output port ,i.e.$ rite P !ata to the e%terna

pin

P1 as an input port ,i.e.$ rea! pin !ata into P &us



Other Pins P1$ P2$ an! P3 ha4e interna pu-up resisters.

P1$ P2$ an! P3 are not open !rain.

P0 has no interna pu-up resistors an! !oes not connectsto cc insi!e the 8051.

P0 is open !rain.

opare the fi6ures of P1." an! P0.".

oe4er$ for a pro6raer$ it is the sae to pro6ra P0$P1$ P2 an! P3.

the ports upon E(ET are confi6ure! as output.



Pin of Port 0

8051 I

: ;

< ;

ea! atch

ea! pin

rite to atch

Interna P

&us

*1

P0."

pinP1."

T)1

T)2

P1.%

http://var/www/apps/conversion/tmp/scratch_7/%23Slide%2039

http://var/www/apps/conversion/tmp/scratch_7/%23Slide%2039



Tri-state )uffer Output Input

Tri-state contro,acti4e hi6h

' 'o

i6hipe!ance

,open-circuit

'



Port 0（

pins 32-39）

P0 is an open !rain.

Open !rain is a ter use! for *O( chips in the sae

a+ that open coector is use! for TT' chips.

hen P0 is use! for sipe !ata I/O e ust connect it to

e%terna pu-up resistors.

Each pin of P0 ust &e connecte! e%terna+ to a 10=

oh pu-up resistor. ith e%terna pu-up resistors connecte! upon reset$

port 0 is confi6ure! as an output port.



Port 0 ith Pu-p esistors

P0.0P0.1P0.2P0.3P0.>P0.5

P0.?P0.7

DS5000

8751

8951

Vcc10 K

P or t 0



:ua oe of Port 0 hen connectin6 an 8051/8031 to an e%terna eor+$ the

8051 uses ports to sen! a!!resses an! rea! instructions.

8031 is capa&e of accessin6 ?>= &+tes of e%terna eor+.

1?-&it a!!ress： P0 pro4i!es &oth a!!ress 0-7$ P2

pro4i!es a!!ress 8-15.

so$ P0 pro4i!es !ata ines :0-:7.

hen P0 is use! for a!!ress/!ata utipe%in6$ it is connecte!

to the 7>'(373 to atch the a!!ress. There is no nee! for e%terna pu-up resistors as shon in

hapter 1>.



7>'(373

D

74LS373ALE

P00

P07

PSE!

A0

A7

D0

D7

P"0

P"7

A8

A15

OE

O#

EA

$

8051 O*



ea!in6 O* ,1/2

D

74LS373ALE

P00

P07

PSE!

A0

A7

D0

D7

P"0

P"7

A8

A1"

OE

O#

EA

$

8051 O*

1. (en! a!!ress to

O*

2. 7>373 atches the

a!!ress an! sen! toO*

!!ress



ea!in6 O* ,2/2

D

74LS373ALE

P00

P07

PSE!

A0

A7

D0

D7

P"0

P"7

A8

A1"

OE

O#

EA

$

8051 O*

2. 7>373 atches the

a!!ress an! sen! toO*

!!ress

3. O* sen! the

instruction &ac<



'E Pin The 'E pin is use! for !e-utipe%in6 the

a!!ress an! !ata &+ connectin6 to the @ pin

of the 7>'(373 atch. hen 'E#0$ P0 pro4i!es !ata :0-:7.

hen 'E#1$ P0 pro4i!es a!!ress 0-7.

The reason is to ao P0 to utipe% a!!ressan! !ata.



Port 2（

pins 21-28）

Port 2 !oes not nee! an+ pu-up resistors

since it area!+ has pu-up resistors

interna+. In an 8031-&ase! s+ste$ P2 are use! to

pro4i!e a!!ress 8-15.



Port 3（

pins 10-17）

Port 3 !oes not nee! an+ pu-up resistors since it area!+ has pu-up resistors interna+.

thou6h port 3 is confi6ure! as an output port upon reset$ this

is not the a+ it is ost coon+ use!.

Port 3 has the a!!itiona function of pro4i!in6 si6nas. (eria counications si6na： %:$ T%:（ hapter 10） E%terna interrupt： /INT0$ /INT1（ hapter 11） Tier/counter ： T0$ T1（ hapter 9） E%terna eor+ accesses in 8031-&ase! s+ste： /$

/:（ hapter 1>）



Port 3 ternate Aunctions

17:P3.7

1? P3.?15T1P3.5

1>T0P3.>

13INT1P3.3

12INT0P3.2

11T%:P3.1

10%:P3.0

Pin%&nctionP3 'it



Pin of Port 1

8051 I

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P

&us

*1

P1."

pinP1."

T)1

T)2

P0.%



ar!are (tructure of I/O Pin

Each pin of I/O ports

Interna P &us： counicate ith P

: atch store the 4aue of this pin

: atch is controe! &+ Brite to atchC rite to atch＝ 1：rite !ata into the : atch

2 Tri-state &uffer ： T)1D controe! &+ Bea! pinC

ea! pin＝ 1： rea+ rea! the !ata present at the pin

T)2D controe! &+ Bea! atchC

ea! atch＝ 1： rea! 4aue fro interna atch

transistor *1 6ate

@ate#0D open

@ate#1D cose



ritin6 B1C to Output Pin P1."

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P

&us

*1

P1."

pinP1."

8051 I

2. output pin is

cc1. rite a 1 to the pin

1

0 output 1

T)1

T)2



ritin6 B0C to Output Pin P1."

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P

&us

*1

P1."

pinP1."

8051 I

2. output pin is

6roun!1. rite a 0 to the pin

0

1 output 0

T)1

T)2



Port 1 as Output（rite to a

Port）

(en! !ata to Port 1：

(OV A)*55+

'A#K, (OV P1)A

A#ALL DELA-

#PL A

S.(P 'A#K

'et P1 to66e. ou can rite to P1 !irect+.



ea!in6 Input 4.s. Port 'atch

hen rea!in6 ports$ there are to possi&iities： ea! the status of the input pin. （ fro external pin value）

*O $ P"

FN) P2.1$ T@ET G Hup if P2.1 is not set

F) P2.1$ T@ET G Hup if P2.1 is set

Ai6ures -11$ -12

ea! the internal latch of the output port.

N' P1$ G P1 P1 N:

O' P1$ G P1 P1 O

IN P1 G increase P1

Ai6ure -17

Ta&e -? ea!-*o!if+-rite Instruction ,or Ta&e 8-5

(ee (ection 8.3



ea!in6 Bi6hC at Input Pin

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P &us

*1

P1." pin

P1."

8051 I

2. *O $P1

e%terna pin#i6h1. rite a 1 to the pin *O

P1$J0AA

1

0

3. ea! pin#1 ea! atch#0

rite to atch#1

1

T)1

T)2



ea!in6 B'oC at Input Pin

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P &us

*1

P1." pin

P1."

8051 I

2. *O $P1

e%terna pin#'o1. rite a 1 to the pin

*O P1$J0AA

1

0

3. ea! pin#1 ea! atch#0

rite to atch#1

0

T)1

T)2



Port 1 as Input（ ea! fro Port）

In or!er to a<e P1 an input$ the port ust &e pro6rae! &+ ritin6

1 to a the &it.

(OV A)*0%%+ A11111111'

(OV P1)A ma2 P1 an in&t ort

'A#K, (OV A)P1 g2t ata from P0

(OV P")A s2n ata to P"

S.(P 'A#K

To &e an input port$ P0$ P1$ P2 an! P3 ha4e siiar etho!s.



Instructions Aor ea!in6 an Input

Port

(n2monics Eam62s D2scrition

(OV A)P (OV A)P")rin6 into the !ata at P2

pins

.!' P-) .!' P"1)A$E Fup if pin P2.1 is o

.' P-) .' P13)A$E Fup if pin P1.3 is hi6h

(OV #)P- (OV #)P"4 op+ status of pin P2.> to

Aooin6 are instructions for rea!in6 e%terna pins of portsD



ea!in6 'atch

E%cusi4e-or the Port 1：

(OV P1)*55+ P101010101

OL P1)*0%0+ P111110101

1. The rea! atch acti4ates T)2 an! &rin6 the !ata fro the ; atch intoP.

ea! P1.0#0

2. P perfors an operation.

This !ata is Oe! ith &it 1 of re6ister . @et 1.

3. The atch is o!ifie!. : atch of P1.0 has 4aue 1.

>. The resut is ritten to the e%terna pin.

E%terna pin ,pin 1D P1.0 has 4aue 1.



ea!in6 the 'atch

: ;

< ;

cc

'oa!,'1

ea! atch

ea! pin

rite to atch

Interna P &us

*1

P1." pin

P1."

8051 I

>. P1."#12. P copute P1." O 1

0

0

1. ea! pin#0 ea! atch#1 rite to

atch#0 ,ssue P1."#0 initia+

1

T)1

T)2

3. rite resut to atch ea!

pin#0 ea! atch#0

rite to atch#1

1

0



ea!-o!if+-rite Aeature

ea!-o!if+-rite Instructions

Ta&e -?

This features co&ines 3 actions in a sin6einstruction：

1. P rea!s the atch of the port

2. P perfor the operation

3. *o!if+in6 the atch

>. ritin6 to the pin

Note that 8 pins of P1 or< in!epen!ent+.



Port 1 as Input（ ea! fro atch）

E%cusi4e-or the Port 1：

(OV P1)*55+ P101010101

A$AI!, O P1)*0%%+ com62m2nt

A#ALL DELA-

S.(P A$AI!

Note that the "O of 55 an! AA 6i4es .

"O of an! AA 6i4es 55.

The instruction rea! the !ata in the atch ,not fro the pin.

The instruction resut i put into the atch an! the pin.



Read-Modify-Wi!e I"#!$%!io"#

ExampleMnemonics

SETB P1&'SETB P(&Y

CLR P1&)CLR P(&Y

MO* P1&+,CMO* P(&Y,C

DN. P1,TARGETDN. P(, TARGET

INC P1INC

CPL P1&+CPL BC P1&1, TARGET BC P(&Y, TARGET

(RL P1,A(RL

ORL P1,AORL

ANL P1,AANL

DEC P1DEC



ou are a&e to anser this ;uestionsD

o to rite the !ata to a pin？ o to rea! the !ata fro the pin？

ea! the 4aue present at the e%terna pin. h+ e nee! to set the pin first？

ea! the 4aue coe fro the atch（ not fro the e%terna

pin） .

h+ the instruction is cae! rea!-o!if+ riteK

Date post:	14-Jan-2016
Category:	Documents
Upload:	tansnvarma
View:	227 times
Download:	0 times

EMBEDDED SYSTEMS-I_O PROGRAMMING.ppt

Documents