eMCP MX100 Series
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1. Features
eMMC
MLC NAND
General Features
o Embedded with e-MMC Flash Controller
and NAND flash
o JEDEC○R eMMC 5.1 compliant
o Field Firmware Update
o Device Health Report
o Secure Removal
o Command Queuing
o 1bit, 4bit, 8bit data bus widths
Supported Speed Mode
o SDR52MHz/DDR52MHz/HS200/HS400
Form Factor
o JEDEC○R MO-276D Embedded Flash
Memory
o BGA 221 Ball BA type (11.5 x 13 mm)
Available Capacities
o 8 GB
Voltages
o Memory Power (VCC): 3.3V
o Interface Power (VCCQ): 1.8V
ECC
o Internal Error Correction
High Performance
o HS400 (400 MB/s bus transfer rate)
Temperature Ranges
o -25⁰ C ~+85⁰ C
LPDDR3 SDRAM
JEDEC LPDDR3 Compliant
o Low Power Consumption
Signal Integrity
o Configurable DS for System
Compatibility
o Configurable On-Die Termination
o ZQ Calibration for DS/ODT
Impedance Accuracy via External ZQ
Pad(240Ω±1%)
Training for Signals Synchronization
o DC Calibration Offering Specific DQ
Output Patterns
o CA Training
o Write Leveling via MR Settings
Data Integrity
o DRAM built-in Temperature Sensor
for Temp. Compensated Self
Refresh(TCSR)
o Auto Refresh and Self Refresh Modes
Power-Saving Modes
o Deep Power Down Mode (DPD)
o Partial Array Self Refresh (PASR)
o Clock Stop Capability during Idle
Period
HSUL12 Interface and Power Supply
o VDD1=1.70V to 1.95V
o VDD2/VDDQ/VDDCA=1.14V to 1.3V
Programmable Functions
o RON(34.3/40/48/60/80)
o RON(PD34.3_PU40/PD40_PU48/PD
34.3_PU48)
o RTT(120/240)
o RL/WL Select(Set A/Set B)
o nWRE(nWR≦9/nWR>9)
o PASR(bank/segment)
Speed Grade(DataRate/Read Latency)
1600Mbps/RL=12
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2. Ordering Information
Part Number NAND
(GB*)
LPDDR3
(Gb)
Dimension
(mm)
Form Factor
T0804P1VDA-FNB0 8 4 11.5 x 13 x 1.0 BGA 221 ball
T0808P1VDA-FNB0 8 8 11.5 x 13 x 1.0 BGA 221 ball
* 1 GB=1,000,000,000 Bytes
For latest ordering information, please consult BIG-INNO’s sales.
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3. Contents
1. Features 1
2. Ordering Information 2
3. Contents 3
4. General Description 4
4.1 System Performance 5
4.2 Environmental Specifications 5
4.3 Power Consumption 5
5. Functional Block Diagram 6
6. Physical Dimension 7
7. Electrical Interface 8
e-MMC 11
1. Product Features 12
1.1 Communication interface 12
1.2 Bus Operating Condition 12
2. Supported Features 14
2.1 Bootable 14
2.2 Partition 17
2.3 Sleep Mode 17
2.4 Sleep (CMD5) 17
2.5 Enhanced Write 18
2.6 Secure Erase 18
2.7 Secure Trim 18
2.8 Trim 18
2.9 Write Protection 18
2.10 Hardware Reset 18
2.11 Background Operations 18
2.12 High Priority Interrupt (HPI) 19
2.13 HS400 19
2.14 Discard Command 21
2.15 Sanitize 21
2.16 Extended partition types 21
2.17 Context ID Management 21
2.18 Data Tag 22
2.19 Packed Commands 22
2.20 Real Time Clock 22
2.21 Dynamic Device Capacity 22
2.22 Power Off Notification 22
2.23 Large Sector Size 22
2.24 Cache 23
3. Signals Connection and Layout Guideline 24
4. Register 26
4.1 OCR Register 26
4.2 CID Register 26
4.3 CSD Register 27
4.4 Extended CSD Register 28
Mobile LPDDR3 SDRAM 37
1. General Description 38
2. Density, Signals and Addressing 38
3. Functional Block Diagram 39
4. LPDDR Ball Descriptions 40
5. Absolute Maximum Ratings 41
6. AC/DC Operating Conditions 43
7. AC/DC Input Level 45
8. VREF Tolerance 47
9. Input Signal- LPDDR3-1600 Input Signal 48
10. AC and DC Logic Input Levels for Differential Signals 49
11. Single-Ended Requirement for Differential Signals 52
12. Differential Input Cross-Point Voltage 53
13. Slew Rate Definitions for Differential Input Signals 54
14. AC/DC Output Measurement Level 55
15. AC Overshoot/Undershoot Specification 59
16. AC Timing 60
17. HSUL_12 Driver Output Timing Reference Load 67
18. Input/Output Capacitance 69
19. IDD Specification 70
20. Electrical Characteristic and AC Timing 75
21. CA and CS Setup, Hold and Derating 76
22. Data Setup, Hold and Slew Rate Derating 84
23. Basic Functionality 91
24. Contact Information 109
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4. General Description
BIG-INNO MX100 is a multichip package memory which combines eMMC and Mobile DDR3
synchronous Dynamic RAM together.
The eMMC is an embedded flash memory storage solution with Multimedia Card interface which
develops for low-cost storage solution for mobile or handheld devices, digital recorders, cameras or
MP3 players. BIG-INNO MX100 eMCP provides several features such as Boot, RPMB partitions,
HPI and background operations. BIG-INNO MX100 integrates advanced NAND Flash with
advanced firmware and controller for the NAND Flash management such as Error Correction Code
(ECC) and power management.
BIG-INNO MX100 integrates a DDR architecture on the command/Address (CA) bus to reduce the
input pin numbers. The 10-bit CA bus contains command, address and Bank information. There is
one clock cycle used by each command when the command information is transferred on both
positive and negative edge of the clock. For achieving high speed operation, BIG-INNO MX100
adopts DDR architecture which is essentially a 4n prefetch architecture with an interface designed
to transfer two data bits per DQ every clock cycle at the I/O pins. The Low Power DDR Read and
Write accesses begin at a specific location. After it starts, the read and write accesses will be
continued in a programmed sequence for a pre-set number of locations. BIG-INNO MX100 Read or
Write accesses starts by registering the Activate command, and then the Activate command will be
followed by a Read or Write command. The registered BA bits and the address which are the same
with the Activate command will be used to select the row and the Banks to be accessed. The Bank
and the starting column location for the burst access will be selected by the registered address bits
which is the same with the Read or Write command. The Low Power DDR3 must be initialized prior
to normal operation.
For the consideration of power consumption efficiency and the limited mount area, BIG-INNO
MX100 is the best solution which is available in 221 ball FBGA package.
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4.1 System Performance
Table 1: System Performance Table
System Performance Value Unit
Sustained Sequential Read Rate
8 GB
190 MB/s
Sustained Sequential Write Rate 35 MB/s
4KB Random Read IOPS 8635 IOPS
4KB Random Write IOPS 810 IOPS
Note: Performance is based on 8-bit HS200 mode
4.2 Environmental Specifications
4.2.1 Recommended Operating Conditions
Table 2: Recommended Operating Conditions
Parameter Value
Operating Temperature -25℃ to +85℃
Temperature Gradient (℃ per hour max, non-condensing) 20℃ (operating)
Temperature Gradient (℃ per hour max, non-condensing) 30℃ (non-operating)
Power Supply Voltage (VCC) 3.3V
Power Supply Voltage (VCCQ) 1.8V/3.3V
4.3 Power Consumption Table 3: Power Consumption
VCC VCCQ
Active 46.10mA 76.39mA
Power saving 38.51μA 116.72μA
All values are tested under room temperature 25℃
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5. Functional Block Diagram
Controller
Low Power DDR3
Memory
NAND Flash
Memory
Data In/Out
Control
eMMC Bus
Interface
LPDDR3 Bus
Interface
Figure 1: Functional Block Diagram
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6. Physical Dimension
TOP BOTTOM
Figure 2 Side/Top View
Dimensions Unit
Length 11.5 mm
Width 13 mm
Thickness 1.0 mm
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7. Electrical Interface
221 FBGA TOP view
Figure 3: TOP View (ball down)
◤ 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A DNU NC VSSm VCCQm DAT6m CMDm RCLKm VSSm DAT0m DAT5m VDDIm VSSm NC DNU
B TXm VSSm VCCm DAT7m DAT3m VCCQm VSSm CLKm VCCQm DAT1m VSSm VCCm VCCm RXm
C RSTm VSSm VCCm VSSm DAT2m VCCQm VSSm DAT4m VSSm VCCQm VSSm VSSm
D NC NC NC NC NC VSSm VCCm
E
F VSS VDD1 VDD1 VDD2 VDD2 VDD1 DQ29 DQ30 DQ31 VSSQ
G ZQ0 NC VSS VDD1 VSS VDDQ DQ26 VSSQ DQ27 DQ28
H CA9 VSS VSSCA VSS VDDQ DQS3 VSSQ DQ24 VDDQ DQ25
J CA8 CA7 VSSCA VDD2 VSSQ /DQS3 DM3 VDDQ DQ15 VSSQ
K VDDCA CA6 VSSCA VDD2 VSSQ VSSQ VDDQ DQ13 VDDQ DQ14
L VDD2 CA5 VSS VDD2 VDDQ VDDQ VSSQ DQ12 VSSQ DQ11
M Vref(CA) VSS VSS VDD2 VSSQ DQS1 VDDQ DQ10 VDDQ DQ9
N VDDCA /CK VSS VDD2 VSS /DQS1 DM1 VDDQ DQ8 VSSQ
P VSSCA CK VSS VDD2 VDD2 VSSQ ODT VDD2 VSS Vref(DQ)
R CKE1 VSS VSS VDD2 VSS /DQS0 DM0 VDDQ DQ7 VSSQ
T CKE0 /CS1 VSS VDD2 VSSQ DQS0 VDDQ DQ5 VDDQ DQ6
U VDDCA /CS0 VSSCA VDD2 VDDQ VDDQ VSSQ DQ3 VSSQ DQ4
V VDDCA CA4 VSSCA VDD2 VSSQ VSSQ VDDQ DQ1 VDDQ DQ2
W CA2 CA3 VSSCA VDD2 VSSQ /DQS2 DM2 VDDQ DQ0 VSSQ
Y CA0 CA1 VSS VSS VDDQ DQS2 VSSQ DQ23 VDDQ DQ22
AA DNU VSS VDD1 VSS VDD1 VSS VDDQ DQ21 VSSQ DQ20 DQ19 DNU
AB DNU DNU VDD1 VDD1 VDD2 VDD2 VDD1 DQ18 DQ17 DQ16 DNU DNU
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Table 4 221 ball Pin and Signal Definition
eMCP
Pin Name Description
DAT0m~DAT7m Data Input/Output
CLKm Clock
RCLKm Data Strobe
CMDm Command
VCCm Power Supply for NAND Flash
VCCQm Power Supply for Controller
VDDIm External capacitance for internal power stability
VSSm Ground pin for Controller/Flash
VSSQm I/O Ground
RSTm This pin is used for Reset
RXm UART receive for eMMC debug pin*
TXm UART transmit for eMMC debug pin*
*It is suggested that the test pads or VIA for RXm and TXm should be taken into consideration for ideal PCB design.
LPDDR3
Pin Name Description
CK,/CK System differential Clock
CKE0,CKE1 Clock Enable
/CS0,/CS1 Chip Selection
CA0~CA9 Command/Address Input
DM0~DM3 Data Mask
DQS0~DQS3 Data Strobe Bi-directional
/DQS0~/DQS3 Data Strobe Complementary
DQ0~DQ31 Data Input/Output
VDD1 Core Power Supply 1
VDD2 Core Power Supply 2
VDDCA Power Supply for Input Receiver
VDDQ I/O Power Supply
VREF(CA) Reference Voltage for CA Input Receiver
VREF(DQ) Reference Voltage for DQ Input Receiver
VSS Ground
VSSCA Ground Pin for CA Input Receivers
VSSQ I/O Ground
ZQ0 Reference Pin for Output Drive Strength Calibration
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Pin Name Description
DNU Do Not Use
NC No Connection
ODT On-Die Termination. This input signal enables/disables termination on the
DRAM DQ according to the specified mode register settings.
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e-MMC
eMCP MX100 Series
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1. Product Features
The BIG-INNO MX100 contain with a high-speed eMMC controller, an advanced NAND Flash
package and a LPDDR3 in to a low profile BGA package.
1.1 Communication interface
BIG-INNO MX100 with eMMC interface supports the eMMC protocol. For more details regarding
these buses refer to JEDEC○R Standard No. 84-B51. The BIG-INNO MX100 has the following
command line as shown in Table 7.
Table 5 MX100 Command Line List
Command Description
CMD This signal is a bidirectional command channel used for device initialization and
command transfers. The CMD signal has two operating modes: open-drain for
initialization, and push-pull for command transfer. Commands are sent from the
MMC bus master to the device, and responses are sent from the device to the host.
DAT [7:0] These are bidirectional data signals. The DAT signals operate in push-pull mode. By
default, after power-up or RESET, only DAT0 is used for data transfer. The memory
controller can configure a wider data bus for data transfer using either DAT[3:0]
(4-bit mode) or DAT[7:0] (8-bit mode).
CLK Each cycle of the clock directs a transfer on the command line and on the data
line(s).The frequency can vary between the minimum and the maximum clock
frequency.
RST_n Reset signal is used for host resetting device, moving the device to pre-idle state. By
default, the RST_n signal is temporary disabled in device. Host need to set bit[0:1]
in the extended CSD register [162] to 0x1 to enable this functionality before the host
uses.
VCCQ VCCQ is the supply voltage for host interface
VCC Flash memory I/F and Flash memory power supply.
VDDi Connect 0.2μF and 4.7μF capacitors to stabilize regulator output to controller core
logics
VSS/VSSQ ground lines
Data Strobe Data Strobe signal is generated by the device for using in HS400 mode. For data
output, each signal cycle directs two bits (2X) on the data. One bit is for positive
edge and the other bit is for negative edge. The CRC and CMD response output
(enabled for HS400 enhanced strobe mode only) are latched on the positive edge
only and don‟t care on the negative edge.
1.2 Bus Operating Condition Table 6 MX100 Bus Operating Condition
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Parameter Symbol Min Max. Unit
Peak voltage on all lines -0.5 VCCQ + 0.5 V
All Inputs
Input Leakage Current (before
initialization sequence and/or the
internal pull up resistors connected)
-100 100 µA
Input Leakage Current (after
initialization sequence and the internal
pull up resistors disconnected )
-2 2 µA
All Outputs
Output Leakage Current (before
initialization sequence)
-100 100 µA
Output Leakage Current (after
initialization sequence)
-2 2 µA
Table 7 Dual Voltage Power Supply
Parameter Symbol Min Max. Unit
Supply voltage (low voltage range) VCCQ 2.7 3.6 V
1.70 1.95 V
VCC 2.7 3.6 V
Supply voltage differentials (VSS1,
VSS2)
-0.5 0.5 V
Supply power-up (1.8V) tPRUL - 25 ms
Supply power-up (3.3V) tPRUH - 35 ms
The MX100 supports one or more combinations of VCC and VCCQ as shown above. VCCQ must be defined
equal to or less than VCC.
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2. Supported Features
2.1 Bootable
BIG-INNO MX100 supports boot operation modes accordingly to eMMC interface definition as
specified by JEDEC○R .
2.1.1 Timing for Boot Operation
The following diagram show Multimedia Card state and timing diagram for normal boot mode. The
operation detail for the boot operation is described as following.
If the CMD line is held LOW for 74 clock cycles and more after power-up or reset (no matter
through CMD0 with the argument of 0xF0F0F0F0 or assertion of hardware reset for eMMC, If it is
enabled in Extended CSD register byte [162], bits [1:0]) before the first command is issued, the
boot data will be prepared internally by the slave once it recognizes that the boot mode is being
initiated. The partition from which the master will read the boot data can be selected in advance by
using EXT_CSD byte [179], bits [5:3]. The data size 128KB xBOOT_SIZE_MULT (EXT_CSD byte
[226]). After the CMD line goes low and within 1 second, the slave starts to send the first boot data
to the master on the DAT line (s). The CMD line must be kept LOW by the master to read all of the
boot data. The push-pull mode must be used by the master until boot operation is terminated. The
master can choose to use single data rate mode with backward-compatible interface timing, single
data rate with high-speed interface timing or dual data rate timing (if it supported). The master can
choose to receive boot acknowledge from the slave by setting “1” in EXIT_CSD register, byte [179],
bit6. And then the master recognizes that the slave is operating in boot mode. The slave has to
send acknowledge pattern “010” to the master within 50ms after the CMD goes low if boot
acknowledge is enabled. The acknowledge pattern “0-1-0” will not be sent out by the slave if boot
acknowledge is disabled. The boot mode can be terminated by the master with the CMD line is
High. If the CMD line is pulled High by the master in the middle of data transfer, the slave has to
terminate the data transfer or acknowledge pattern within NST clock cycles (one data cycle and
end bit cycle). If the boot mode is terminated by the master between consecutive blocks, the slave
must release the data line(s) within NST clock cycles.
When all contents of the enabled boot data are sent to the master, boot operation will be terminated.
After boot operation is executed, the slave shall be ready for CMD1 operation and the master
needs to start a normal MMC initialization sequence by sending CMD1. From CMD signal high to
next MMC command, it needs minimum 8 clocks + 48 clocks = 56 clocks. Before CMD1 is issued, if
the CMD line is held LOW for less than 74 clock cycles after power-up or the master sends any
normal MMC command other than CMD0 with argument 0xFFFFFFFA before initiating boot mode,
the slave shall not respond and shall be locked out of boot mode until the next power cycle or
hardware reset, and shall enter Idle State. Slave must enter Card Identification Mode and respond
to the command when BOOT_PARTITION_ENABLE bits are set and master send CMD1
(SEND_OP_COND). If the boot operation mode is not supported by the slave that is compliant with
v4.2 or before or BOOT_PARTITION_ENABLE bit is cleared, slave automatically enter Idle State
after power-on.
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Figure 4 Multimedia Card State & Timing Diagram (Boot Mode)
2.1.2 Alternative Boot Operation
This boot function is compulsory for v4.4 or newer standard. Device that is compliant with v4.4
standard will show “1” bit 0 in the Extended CSD byte [228]. The slave will recognize that boot
mode is being initiated and starts preparing boot data internally, if the host issues CMD0 with the
argument of 0xFFFFFFFA after 74 clock cycles before CMD1 is issued or the CMD line goes low
when the device is powered-up or reset (either assertion of CMD0 with the argument of
0xF0F0F0F0 or H/W reset if it is enabled). The partition from which the master will read the boot
data can be selected in advance using EXT_CSD byte [179], bits [5:3]. 128KB
xBOOT_SIZE_MULT (EXT_CSD byte [226] is the data size that the master can read during boot
operation. The slave starts to send the first boot data to the master on the DAT line(s) within 1
second after CMD with the argument of 0xFFFFFFFA is issued within 1 second. The master must
use push-pull mode until boot operation is terminated. The master can choose to use single data
rate with high-speed interface timing or dual rate timing (if it is supported), single data rate mode
with backward-compatible interface timing. The master can choose to receive boot acknowledge
from the slave by setting “1” in EXT_CSD register, byte [179], bit 6 that the master can recognize
that the slave is operating in boot mode.
The acknowledge pattern “010” must be sent to the master within 50ms by the slave after the
CMD0 with the argument of 0xFFFFFFFA is received for the condition if boot acknowledge is
enabled. If boot acknowledge is disabled, the acknowledge pattern “010” will not be sent out by the
slave. When all contents of the enabled boot data are sent to the master, boot operation will be
terminated.
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Figure 5 Multimedia Card State & Timing Diagram (Alternative Boot Mode)
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2.2 Partition
BIG-INNO MX100 let the host split local memory into partitions with independent addressable
space from logical address 0x00000000 for different use. Memory blocks are segmented as
hereafter:
Default factory setting defines two 4 MB boot partitions, as enhanced storage media.
Host can set one segment in User Data Area as enhanced storage media (starting location and
Write Protect Group size). This is one-time programmable and can NOT be changed once set.
Up to 4 General Purpose Area can be set as user data or sensitive data or other usage. Partition
size must be a multiple of the write protect group. This is one-time programmable and can NOT be
changed once set.
There are four default area existed in the memory device including a User Data Area, two possible
boot area partitions for booting and the Replay Protected Area Partition to verify and replay-protect
data. Before any partitioning operation, the memory initially consists of the User Data Area and
Boot Area Partitions. The embedded device offers the possibility of configuring by using host
additional split local memory partition with independent addressable space. The addressable space
starts from logical address 0x00000000 for different usage models. For two Boot Area Partitions,
the size is multiple of 128KB and let the booting from eMMC can be performed. Four General
Purpose Area Partitions is used for sensitive data storage and the size is multiple of a Write Protect
Group. Memory manufacturer defines Boot Partitions‟ size and attributes (read-only). For General
Purpose Area Partitions‟ sizes and attributes, they can be programmed by the host only once in the
device life cycle (one-time programmable). Moreover, one segment of the User Data Area can be
configured to be implemented as enhanced storage media and to specify its starting location and
size in terms of Write Protect Groups. The attributes of the Enhanced User Data Area can be
programmed only once during device life cycle.
2.3 Sleep Mode
BIG-INNO MX100 automatically switches to sleep mode to save power if no further commands are
received. Typical sleep transition last 200ns (highest duration before sleep is 850ms, for
housekeeping operation). It does not involve any action from host, however, for maximum power
saving (lowest current), host clock to the memory device needs to be shut down. For most
embedded systems, beside while host is accessing data, devices are always in sleep mode, for
greater power saving efficiency. Whenever host is going to access storage device in sleep mode,
any issued command will cause device to exit sleep and operation execution.
2.4 Sleep (CMD5)
BIG-INNO MX100 can switch between Sleep and Standby on SLEEP/AWAKE (CMD5) command.
In Sleep state, device‟s power consumption is minimized and reacts only to RESET (CMD0) and
SLEEP/AWAKE (CMD5) commands. Any other command will be completely ignored.
The Vcc power supply may even be switched off in Sleep mode to allow further power saving.
For additional information please refer JESD84-B51 6.6.21.
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2.5 Enhanced Write
In BIG-INNO MX100 reliable write mode, original data pointed by a logical address will stay the
same until the new data has been successfully overwritten. This ensures that the each write
transaction will always be reliable and never leaves undefined data in given address. When using
enhanced write, data will remain valid even in the case of power drop during programming.
2.6 Secure Erase
BIG-INNO MX100 supports Security Mode Erase command. Once triggered, no command is
allowed until Secure Erase is completed.
BIG-INNO MX100 will sanitize the erase area with predefined pattern. The purge will overwrite
addressable content with a given character and then erase the NAND flash.
This command meets specific defense or governmental requirements and guarantees Flash
memory content can no longer be restored.
2.7 Secure Trim
BIG-INNO MX100 Secure Trim is similar to the Secure Erase but performs a purge on write blocks
(512 bytes) .
2.8 Trim
Trim function acts like an Erase but operate at block (512 B) level. For additional information, refer
to JEDEC○R JESD84-B51 6.6.10
2.9 Write Protection
To prevent accidental data loss or overwrite, BIG-INNO MX100 provides two levels of write
protection:
• Write-protect the whole device (including the Boot Area Partitions, General Purpose Area
Partition, and User/Enhanced User Data Area Partition) by setting the permanent or temporary
write protect bits in the CSD.
• Write-protect specific segments permanently or temporarily write protected. Segment size can
be defined in the EXT_CSD register.
For additional information, refer to JEDEC○R JESD84-B51 6.6.15.
2.10 Hardware Reset
Host may reset the device to pre-idle state and disable temporary write protection on related blocks.
For additional information, refer to JEDEC○R JESD84-B51 6.15.10.
2.11 Background Operations
In order to reduce latency for time critical operations, housekeeping operations (garbage collection,
erase and compaction) are executed in the background.
Operations are classified into two types:
Foreground – such as read or write commands and
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Background –executed when the device is not busy with host commands.
For additional information on Background Operations, refer to JESD84-B51 standard 6.6.25.
2.12 High Priority Interrupt (HPI)
If OS use on demand-paging to run user process, the host needs to fetch pages in the midst of
other operation, so the query might be delayed until the completion of the command.
High priority interrupt (HPI) allows low read latency operation, by holding lower priority process
before completion. This mechanism reduces latency, typically to less than 10 ms.
For additional information on the HPI function, refer to JESD84-B51 standard 6.6.26.
2.13 HS400
BIG-INNO MX100 eMCP supports the HS 400 mode operation which can enhance the transfer
speed up to 400 MB/s with up to 200 MHz frequency by 1.8V supply voltages.
After the MX100 is triggered by the host, the host will read the DEVICE_TYPE field in the Extended
CSD register to see whether MX100 is HS400 mode supported or not. For more information on the
HS400 mode, refer to JESD84-B51 standard 5.3.6. Please see following diagram for HS400 mode
operation flow.
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Entering the HS200 Mode
Set HS200 bit and Driver
Strength value in
HS_TIMING (CMD6)
Host may invoke Tuning
Command (CMD21)
Tuning Process
Completed?
Yes
HS200 mode selection
completed
Set HS_TIMING to 0x01
(High Speed) for DDR 8bit
bus width setting (CMD6)
Host may change
frequency to ≤ 52 MHz
Set the bus width to DDR
8bit (CMD6)
Host may read Driver
Strength (CMD8)
Set HS400 in HS_TIMING
(CMD6)
Device Busy?
Busy
Device reports No
Error?
Cannot switch to HS400
No
Host may change
frequency to ≤ 200 MHz
HS400 mode selection
completed
Yes
No
Not Busy
HS400 Mode Selection Sequence
Figure 6 HS400 operation flow
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2.14 Discard Command
The Discard function allows the host to identify the data that is no longer needed and then the data
can be erased if necessary during background erase events. The Discard operation is similar to
TRIM. After discard operation, the data will be partially or fully remained according to different
device. The contents of discarded write block will be decided by the device.
For Discard, if the data is marked for erase, it is no need for the device to guarantee that the host
would not retrieve the original data from those “marked” logical block address when a Read
operation is directed. However, for TRIM operation, it must response with „0‟ or „1‟ depends on
different memory technology.
For additional information on the Discard, please refer to JESD84-B51 standard 6.6.12
2.15 Sanitize
The Sanitize operation is a feature that is used to remove data from the device in addition to TRIM
and Erase. The Sanitize operation is to physically remove the data from the unmapped user
address space in the device. For initializing a Sanitize operation, it is needed to write a value to the
extended CSD [165] SANITIZE_START. While the device is performing the sanitize operation, the
busy line is asserted, the busy line is asserted. The Sanitize operation will be continued with busy
asserted until one of the following events occurs:
Sanitize operation is complete.
An HPI is used to abort the operation
A power failure.
A hardware reset. For additional information on the Sanitize, refer to JESD84-B51 standard
6.6.11.
2.16 Extended partition types
Each General Purpose partition has a different extended partition attribute. The list of attribute
types includes as following:
Default: no extended attribute is set
System code: a partition that is rarely updated and contains important system files (e.g.
containing the executable files of the host operating system)
Non-Persistent – a partition that is used for temporary information (e.g. swap file to extend the
host virtual memory space)
The device can be optimized for the mixture of storage media characteristics for users per partition.
The enhanced and extended attribute set can not be existed in a single partition. For additional
information on the extended partition, refer to JESD84-B51 6.2.3 standard
2.17 Context ID Management
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Contents can be associated with groups of read and write commands for improving multitasking
support and distinguishing large sequential and small random operations. By combining a group of
commands with a single context can optimize the performance of data handling for the device.
The context-ID defines one or more concurrent contexts that can be supported by the device.
Context ID #0 always exists for backward compatibility and for context-less data. For each context
ID (besides #0), there is a configuration field in EXT_CSD to control its behavior. For additional
information on the Context ID Management, refer to JESD84-B51 standard 6.6.27.
2.18 Data Tag
The device can receive the specific data types (for instance file system metadata, time-stamps,
configuration parameters, etc.) from the host by the Data Tag mechanism. The address will be well
defined and the information will be transferred before a write multiple blocks writing operation.
During the read and update operations, the device improves the access rate by receiving the Data
Tag information. Besides, the Data Tag also helps for more reliable and robust storage solution. For
additional information on the Data Tag function, refer to JESD84-B51 standard 6.6.28
2.19 Packed Commands
For reducing overheads, packed commands can be applied to pack read and write commands in
one group and transfer it at one time on the bus. For additional information on the Packed
Commands, refer to JESD84-B51 standard 6.6.29.
2.20 Real Time Clock
For the host, it provides UTC based absolute time or relative time if available for the host to update
real time clock and relative time updates (see CMD49). The main function of the real time clock is
to provide real time clock information to the device for internal maintenance use. For additional
information on the Real Time Clock, refer to JESD84-B51 standard 6.6.35.
2.21 Dynamic Device Capacity
Dynamic Device Capacity is a function to reduce the bad blocks capacity due to extensive memory
usage or aging of Flash to extend the lifespan of the device.
The dynamic device capacity commands and statuses are based on high capacity write protection
group size and support only for high capacity devices.
For additional information on the Dynamic Device Capacity, refer to JESD84-B51 6.6.33 standard.
2.22 Power Off Notification
The Power Off Notification is transferred from the host to the device to notify the device to be well
prepared before power off occurs.
For additional information on the Power Off Notification, refer to JESD84-B51 standard 6.6.36
2.23 Large Sector Size
The Large sector size can be the smallest unit for the device for internal management. There are
eMCP MX100 Series
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two options for the large sector size of high capacity devices as follows.
Small 512B sectors (supported by devices up to and including 256GB)
Large 4KB sectors (supported by all devices)
The device reports its native sector size in NATIVE_SECTOR_SIZE field of EXT_CSD [63].
For additional information on the Large Sector Size, refer to JESD84-B51 standard 6.6.34
2.24 Cache
For an eMCP device, cache is the temporary storage space used for reducing read/write access
time (compared to an access to the main non-volatile storage). The cache can be used also for
some special operations such as to be the execution memory for memory controller or to be the
address mapping table storage space. For additional information on the Cache, refer to
JESD84-B51 standard 6.6.31.
eMCP MX100 Series
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3. Signals Connection and Layout Guideline
The paragraph provides you the connection and layout guideline for BIG-INNO eMCP embedded
storage solutions. Please follow following layout guidelines to achieve highest reliability and
performance for your eMCP storage solutions
1. For signal integrity, it is recommended that all of eMCP signals route on PCB component layer
and reference to GND layer.
2. The following table capture from eMMC spec shows the pull high resistor value for eMMC
interface. It is recommended to put 47KΩ for DAT signals, 10 KΩ for CMD signal and a 22 Ω serial
resistor for CLK between host and eMCP device.
Table 8 Recommended component value for layout
Parameter Symbol Min Typ Max Unit Remark
Pull-up resistance for CMD RCMD 4.7 100 KΩ To prevent bus floating
Pull-up resistance for DAT0-7 RDAT 10 100 KΩ To prevent bus floating
Pull-down resistance for Data
Strobe
RDS 10 100 KΩ
3. The eMCP support one or more combinations of Vcc and Vccq as shown below. The Vccq
must be defined at equal to or less than Vcc.
For eMCP, it needs Vccq 1.8V for 200MHz high speed, so it is recommended to supply 3.3V and
1.8V for Vcc and Vccq respectively.
VCCQ
1.7V~1.95V/2.7V~3.6V
VCC 2.7V~3.6V Valid
4. For VCC, It‟s recommended to put one 0.2uF and one 4.7uF capacitors. For VCCQ, it is
recommended to put one 0.2uF and one 2.0uF capacitors. For VDDI, it‟s recommended to put one
0.2uF and one 4.7 uF capacitors.
It needs to keep the PWR/GND trace as wide as short as possible. It‟s recommended to put the
capacitors on bottom layer under the power ball.
eMCP MX100 Series
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Host Device
CLK
CMD
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
VCCQ
VCC
VSS
RSTN
VDDI
CLK
VCC
VCCQ
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
H/W RESET
CMD
R R R R R R R R R R
C
C C
C C
VCCQVCCQ
Host connection guide for x8 Support
47KΩ 47KΩ 47KΩ 47KΩ 47KΩ 47KΩ 47KΩ 47KΩ 47KΩ
22Ω
4.7μ F
0.2μ F 2.0μ F
0.2μ F 4.7μ F
10KΩ
RCLKm
RDS
30KΩ C
0.2μF
Figure 7 Supported x8 connection guide
Host
controller Device
CLK
CMD
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
VDD
VDDF
VSS
RSTN
VDDI
CLK
VDDF
VDD
DAT0
DAT1
DAT2
DAT3
H/W RESET
CMD
R R R R R R
C
CC
C C
VDDVDD
Host connection guide for x4 Support
47KΩ 47KΩ 47KΩ 47KΩ 50KΩ10KΩ
22Ω
2.0μ F0.2μ F
0.2μ F4.7μF
4.7μ F
RCLKm
C
0.2μF
Figure 8 Supported x4 connection guide
eMCP MX100 Series
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4. Register
4.1 OCR Register Offset Field Value
[6:0] Reserved 00 0000b
[7:7] 1.70 V to 1.95V 1b
[14:8] 2.0 V to 2.6V 000 0000b
[23:15] 2.7 V to 3.6V 1 1111 1111b
[28:24] Reserved 0 0000b
[30:29] Access mode 10b (sector mode)
[31:31] Card power up status bit 1b (Ready)
4.2 CID Register Offset Field Value
[127:120] MID 0x34
[119:114] Reserved 0x0
[113:112] CBX 0x1
[111:104] OID 0x0
[103:56] PNM PFP11A, PFP12A
[55:48] PRV 0x00 (0.0)
[47:16] PSN Inconstant value
[15:8] MDT 0xB2 (Month:11, Year:1999)*
[7:1] CRC Inconstant value
[0:0] Always1 0x1
*If EXT_CSD_REV〔192〕>4, Year: 2015
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4.3 CSD Register Offset Field Value
[127:126] CSD_STRUCTURE 0x3 (Version is in EXT_CSD CSD_STRUCTURE byte)
[125:122] SPEC_VERS 0x4 (Version 4.1, 4.2, 4.3)
[121:120] Reserved 0x0
[119:112] TAAC 0x27 (15ms)
[111:104] NSAC 0x1
[103:96] TRAN_SPEED 0x32 (26MHz)
[95:84] CCC 0x1F5 (Card supports class 0 2 4 5 6 7 8 )
[83:80] READ_BL_LEN 0x9 (512 Bytes)
[79:79] READ_BL_PARTIAL 0x0
[78:78] WRITE_BLK_MISALIGN 0x0
[77:77] READ_BLK_MISALIGN 0x0
[76:76] DSR_IMP 0x0
[75:74] Reserved 0x0
[73:62] C_SIZE 0xFFF (device density is greater than 2GB)
[61:59] VDD_R_CURR_MIN 0x6 (60mA)
[58:56] VDD_R_CURR_MAX 0x6 (80mA)
[55:53] VDD_W_CURR_MIN 0x6 (60mA)
[52:50] VDD_W_CURR_MAX 0x6 (80mA)
[49:47] C_SIZE_MULT 0x7 (512)
[46:42] ERASE_GRP_SIZE 0x1F (31)
[41:37] ERASE_GRP_MULT 0x1F (31)
[36:32] WP_GRP_SIZE 0x1F
[31:31] WP_GRP_ENABLE 0x1
[30:29] DEFAULT_ECC 0x0
[28:26] R2W_FACTOR 0x7 (128)
[25:22] WRITE_BL_LEN 0x9 (512 Bytes)
[21:21] WRITE_BL_PARTIAL 0x0
[20:17] Reserved 0x0
[16:16] CONTENT_PROT_APP 0x0
[15:15] FILE_FORMAT_GRP 0x0(Hard disk-like file system with partition table)
[14:14] COPY 0x1
[13:13] PERM_WRITE_PROTECT 0x0
[12:12] TMP_WRITE_PROTECT 0x0
[11:10] FILE_FORMAT 0x0
[9:8] ECC code 0x0(none)
[7:1] CRC 0xE
[0:0] Always1 0x1
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4.4 Extended CSD Register Offset Field Value
Properties Segment
[511:506] Reserved 00 00 00 00 00 00
[505] EXT_SECURITY_ERR 0x0
[504] S_CMD_SET 0x1
[503] HPI_FEATURES 0x1
(HPI_SUPPORT, HPI mechanism implementation based on
CMD13)
[502] BKOPS_SUPPORT 0x1
[501] MAX_PACKED_READS 0x3F
[500] MAX_PACKED_WRITES 0x3F
[499] DATA_TAG_SUPPORT 0x1
[498] TAG_UNIT_SIZE 0x8
[497] TAG_RES_SIZE 0x0
[496] CONTEXT_CAPABILITIES 0x5
[495] LARGE_UNIT_SIZE_M1 0x0
[494] EXT_SUPPORT 0x3
[493]
SUPPORTED_MODES
0x1
bit[0]=0x1 (FFU(Field Firmware Update) is supported.),
bit[1]=0x0 (VSM(Vendor Specific Mode) is not supported.)
[492]
FFU_FEATURES
0x0
bit[0]=0x1 (Device support FFU_FEATURES.)
[491]
OPERATION_CODE_TIMEOUT
0x12
(26214400 us)
[490:487] FFU_ARG 00 00 00 00
[486] BARRIER_SUPPORT 0x0
[485:309] Reserved 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Offset Field Value
00 00 00 00 00 00 00 00 00 00 00
[308] CMDQ_SUPPORT 0x0
[307] CMDQ_DEPTH 0x0
[306] Reserved 0x0
[305:302] NUMBER_OF_FW_SECTORS_
CORRECTLY_PROGRAMMED
0x00000000
[301:270] VENDOR_PROPRIETARY_HE
ALTH_REPORT
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[269] DEVICE_LIFE_TIME_EST_TYP
_B
0x1
(0%-10% device life time used)
[268] DEVICE_LIFE_TIME_EST_TYP
_A
0x1
(0%-10% device life time used)
[267] PRE_EOL_INFO 0x1
(Normal)
[266] OPTIMAL_READ_SIZE 0x2
(Optimal Read Size = 8 KB)
[265] OPTIMAL_WRITE_SIZE 0x2
(Optimal Write Size = 8 KB)
[264] OPTIMAL_TRIM_UNIT_SIZE 0x1
(Optimal trim unit size = 4 KB)
[263:262] DEVICE_VERSION 0x0000
[261:254] FIRMWARE_VERSION 00 00 00 00 00 00 02 94
[253] PWR_CL_DDR_200_360 0x0
[252:249] CACHE_SIZE 0x00000080 (Size of the Cache = 128 Kbytes)
[248] GENERIC_CMD6_TIME 0xA (100 ms)
[247] POWER_OFF_LONG_TIME 0x3C (600 ms)
[246] BKOPS_STATUS 0x0
[245:242] CORRECTLY_PRG_SECTORS
_NUM
0x00000000
[241] INI_TIMEOUT_AP 0x64 (10000 ms)
[240] Reserved 0x0
[239] PWR_CL_DDR_52_360 0x0
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Offset Field Value
[238] PWR_CL_DDR_52_195 0x0
[237] PWR_CL_200_195 0x0
[236] PWR_CL_200_130 0x0
[235] MIN_PERF_DDR_W_8_52 0x0
[234] MIN_PERF_DDR_R_8_52 0x0
[233] Reserved 0x0
[232] TRIM_MULT 0x2 (TRIM Timeout = 600 ms)
[231] SEC_FEATURE_SUPPORT 0x55
bit[0]=0x1(SECURE_ER_EN),
bit[2]=0x1(SEC_BD_BLK_EN),
bit[4]=0x1(SEC_GB_CL_EN),
bit[6]=0x1(SEC_SANITIZE)
[230] SEC_ERASE_MULT 0xFF (Secure Erase Timeout = 153000 ms)
[229] SEC_TRIM_MULT 0xFF (Secure TRIM Timeout = 153000 ms)
[228] BOOT_INFO 0x7
bit[0]=0x1(Support ALT_BOOT_MODE),
bit[1]=0x1(Support DDR_BOOT_MODE),
bit[2]=0x1(Support HS_BOOT_MODE)
[227] Reserved 0x0
[226] BOOT_SIZE_MULT 0x20 (Boot Partition size = 4096 Kbytes)
[225] ACC_SIZE 0x4 (Super-page size = 4096 Kbytes)
[224] HC_ERASE_GRP_SIZE 0x1 (Erase Unit Size = 512 Kbytes)
[223] ERASE_TIMEOUT_MULT 0x2 (600 ms)
[222] REL_WR_SEC_C 0x1
[221] HC_WP_GRP_SIZE 0x10 (8192 Kbytes)
[220] S_C_VCC 0x8(256μA)
[219] S_C_VCCQ 0x8(256μA)
[218] PRODUCTION_STATE_AWARE
NESS_TIMEOUT
0x17
[217] S_A_TIMEOUT 0x17 (838860800 ns)
[216] SLEEP_NOTIFICATION_TIME 0x5
[215:212] SEC_COUNT 8 GB: 0x00E90000 (Device density = 7.281 GB)
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Offset Field Value
[211] SECURE_WP_INFO 0x0
bit[0]=0x0(SECURE_WP_SUPPORT)),
bit[1]=0x0(SECURE_WP_EN_STATUS)),
[210] MIN_PERF_W_8_52 0x0
[209] MIN_PERF_R_8_52 0x0
[208] MIN_PERF_W_8_26_4_52 0x0
[207] MIN_PERF_R_8_26_4_52 0x0
[206] MIN_PERF_W_4_26 0x0
[205] MIN_PERF_R_4_26 0x0
[204] Reserved 0x0
[203] PWR_CL_26_360 0x0
[202] PWR_CL_52_360 0x0
[201] PWR_CL_26_195 0x0
[200] PWR_CL_52_195 0x0
[199] PARTITION_SWITCH_TIME 0x4 (40 ms)
[198] OUT_OF_INTERRUPT_TIME 0x5 (50 ms)
[197] DRIVER_STRENGTH 0x1F
[196] DEVICE_TYPE 0x57
bit[0]=0x1(HS @ 26MHz - at rated device voltage(s)),
bit[1]=0x1(HS @ 52MHz - at rated device voltage(s)),
bit[2]=0x1(HS_DDR @ 52MHz - 1.8V or 3V I/O),
bit[3]=0x0(HS_DDR @ 52MHz - 1.2V I/O),
bit[4]=0x1(HS200_SDR @ 200 MHz - 1.8V I/O),
bit[5]=0x0(HS200_SDR @ 200 MHz - 1.2V I/O),
bit[6]=0x1(HS400_DDR @ 200MHz V 1.8V I/O),
bit[7]=0x0(HS400_DDR @ 200MHz V 1.2V I/O)
[195] Reserved 0x0
[194] CSD_STRUCTURE 0x2 (CSD version No. 1.2)
[193] Reserved 0x0
[192] EXT_CSD_REV 0x7 (Revision 1.7, for MMC v5.0)
[191] CMD_SET 0x0
[190] Reserved 0x0
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Offset Field Value
[189] CMD_SET_REV 0x0 (v4.0)
[188] Reserved 0x0
[187] POWER_CLASS 0x0
[186] Reserved 0x0
[185] HS_TIMING 0x0 (Selecting backwards compatibility interface timing)
[184] Reserved 0x0
[183] BUS_WIDTH 0x0
[182] Reserved 0x0
[181] ERASED_MEM_CONT 0x0
[180] Reserved 0x0
[179] PARTITION_CONFIG 0x0
bit[2:0]=0x0(PARTITION_ACCESS: No access to
boot partition (default))
bit[5:3]=0x0(BOOT_PARTITION_ENABLE: Device
not boot enabled (default))
bit[6]=0x0(BOOT_ACK: No boot ACK sent (default))
[178] BOOT_CONFIG_PROT 0x0
bit[0]=0x0(PWR_BOOT_CONFIG_PROT: is not enabled
(default))
bit[4]=0x0(PERM_BOOT_CONFIG_PROT: is not enabled
(default))
[177] BOOT_BUS_CONDITIONS 0x0
bit[1:0]=0x0(BOOT_BUS_WIDTH: x1(sdr) or x4(ddr) bus
width in boot operation mode (default))
bit[2]=0x0(RESET_BOOT_BUS_CONDITIONS: Reset
(default))
bit[4:3]=0x0(BOOT_MODE: SDR, backward compatible
timings (default))
[176] Reserved 0x0
[175] ERASE_GROUP_DEF 0x0
[174] BOOT_WP_STATUS 0x0
bit[1:0]=0x0(B_AREA_1_WP: Boot Area 1 is not
protected)
bit[3:2]=0x0(B_AREA_2_WP: Boot Area 2 is not
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Offset Field Value
protected)
[173] BOOT_WP 0x0
bit[0]=0x0(B_PWR_WP_EN)
bit[1]=0x0(B_PWR_WP_SEC_SEL)
bit[2]=0x0(B_PERM_WP_EN)
bit[3]=0x0(B_PERM_WP_SEC_SEL)
bit[4]=0x0(B_PERM_WP_DIS)
bit[6]=0x0(B_PWR_WP_DIS)
bit[7]=0x0(B_SEC_WP_SEL)
[172] Reserved 0x0
[171] USER_WP 0x0
bit[0]=0x0(US_PWR_WP_EN)
bit[2]=0x0(US_PERM_WP_EN)
bit[3]=0x0(US_PWR_WP_DIS)
bit[4]=0x0(US_PERM_WP_DIS)
bit[6]=0x0(CD_PERM_WP_DIS)
bit[7]=0x0(PERM_PSWD_DIS)
[170] Reserved 0x0
[169] FW_CONFIG 0x0
[168] RPMB_SIZE_MULT 0x20 (RPMB partition size = 4,096 Kbytes)
[167] WR_REL_SET 0x1F
bit[0]=0x1(WR_DATA_REL_USR)
bit[1]=0x1(WR_DATA_REL_1)
bit[2]=0x1(WR_DATA_REL_2)
bit[3]=0x1(WR_DATA_REL_3)
bit[4]=0x1(WR_DATA_REL_4)
[166] WR_REL_PARAM 0x5
bit[0]=0x1(HS_CTRL_REL)
bit[2]=0x1(EN_REL_WR)
bit[4]=0x0(EN_RPMB_REL_WR)
[165] SANITIZE_START 0x0
[164] BKOPS_START 0x0
[163] BKOPS_EN 0x0
[162] RST_n_FUNCTION 0x0
bit[1:0]=0x0(RST_n_ENABLE: RST_n signal is temporarily
disabled (default))
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Offset Field Value
[161] HPI_MGMT 0x0
[160] PARTITIONING_SUPPORT 0x7
bit[0]=0x1(PARTITIONING_EN)
bit[1]=0x1(ENH_ATTRIBUTE_EN)
bit[2]=0x1(EXT_ATTRIBUTE_EN)
[159:157] MAX_ENH_SIZE_MULT 8 GB: MAX_ENH_SIZE_MULT: 0x0001D2 (Max Enhanced
Area = 3817472 Kbytes)
[156] PARTITIONS_ATTRIBUTE 0x0
bit[0]=0x0(ENH_USR)
bit[1]=0x0(ENH_GPP_1)
bit[2]=0x0(ENH_GPP_2)
bit[3]=0x0(ENH_GPP_3)
bit[4]=0x0(ENH_GPP_4)
[155] PARTITION_SETTING_COMPL
ETED
0x0
[154:143] GP_SIZE_MULT 0x000000(GPP1), (GPP1 Size = 0 Kbytes)
0x000000(GPP2), (GPP2 Size = 0 Kbytes)
0x000000(GPP3), (GPP3 Size = 0 Kbytes)
0x000000(GPP4), (GPP4 Size = 0 Kbytes)
[142:140] ENH_SIZE_MULT 0x000000 (Enhanced User Area Size = 0 Kbytes)
[139:136] ENH_START_ADDR 0x00000000
[135] Reserved 0x0
[134] SEC_BAD_BLK_MGMNT 0x0 (SEC_BAD_BLK)
[133] PRODUCTION_STATE_AWARE
NESS
0x0
[132] TCASE_SUPPORT 0x0
[131] PERIODIC_WAKEUP 0x0 (WAKEUP_PERIOD: 0 infinity (no wakeups))
[130] PROGRAM_CID_CSD_DDR_S
UPPORT
0x1
[129:128] Reserved 0x0000
[127:64] VENDOR_SPECIFIC_FIELD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[63] NATIVE_SECTOR_SIZE 0x0
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Offset Field Value
[62] USE_NATIVE_SECTOR 0x0
[61] DATA_SECTOR_SIZE 0x0
[60] INI_TIMEOUT_EMU 0x0 (0 ms)
[59] CLASS_6_CTRL 0x0 (Write Protect (Default))
[58] DYNCAP_NEEDED 0x0
[57:56] EXCEPTION_EVENTS_CTRL 0x0000
bit[1]=0x0(DYNCAP_EVENT_EN)
bit[2]=0x0(SYSPOOL_EVENT_EN)
bit[3]=0x0(PACKED_EVENT_EN)
bit[4]=0x0(EXTENDED_SECURITY_EN)
[55:54] EXCEPTION_EVENTS_STATUS 0x0000
bit[0]=0x0(URGENT_BKOPS)
bit[1]=0x0(DYNCAP_NEEDED)
bit[2]=0x0(SYSPOOL_EXHAUSTED)
bit[3]=0x0(PACKED_FAILURE)
bit[4]=0x0(EXTENDED_SECURITY_FAILURE)
[53:52] EXT_PARTITIONS_ATTRIBUTE 0x0000
0x00(EXT_1)
0x00(EXT_2)
0x00(EXT_3)
0x00(EXT_4)
[51:37] CONTEXT_CONF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[36] PACKED_COMMAND_STATUS 0x0
bit[0]=0x0(Error)
bit[1]=0x0(Indexed Error)
[35] PACKED_FAILURE_INDEX 0x0
[34] POWER_OFF_NOTIFICATION 0x0
(NO_POWER_NOTIFICATION)
[33] CACHE_CTRL 0x0
(Cache is OFF)
[32] FLUSH_CACHE 0x0
(Reset value)
[31] BARRIER_CTRL 0x0
[30] MODE_CONFIG 0x0
(Normal Mode: To keep the compatibility)
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Offset Field Value
[29] MODE_OPERATION_CODES 0x0
(Reserved)
[28:27] Reserved 00 00
[26] FFU_STATUS 0x0
(Success)
[25:22] PRE_LOADING_DATA_SIZE 00 00 00 00
[21:18] MAX_PRE_LOADING_DATA_SI
ZE
00 40 00 00
[17] PRODUCT_STATE_AWARENES
S_ENABLEMENT
0x3
bit[0]=0x1(Manual mode is supported)
bit[1]=0x1(Auto mode is supported)
bit[4]=0x0(Production State Awareness is enabled)
bit[5]=0x0(Auto mode is enabled)
[16] SECURE_REMOVAL_TYPE 0x1
[Supported Secure Removal Type]
bit[0]=0x1(info. removed by an erase of the physical
memory)
bit[1]=0x0
bit[2]=0x0
bit[3]=0x0
[Configure Secure Removal Type]
bit[5:4]=0x0(info. removed by an erase of the physical
memory)
[15] CMDQ_MODE_EN 0x0
[14:0] Reserved 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Mobile LPDDR3 SDRAM
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1. General Description
BIG-INNO LPDDR3 devices are high-speed synchronous DRAM devices. BIG-INNO LPDDR3 also adopts
double date rate on the DQ pins to achieve high speed operation.
After the registration an Active command, the Access begins. After that, there will be a Read or Write
command. The 10-bit CA bus contains command, address and bank information.
For normal operation, the device must be initialized. For the detail information including device
initialization, register definition, command description and device operation, please see sections in the
following paragraphs. Packages/Density information
2. Density, Signals and Addressing
Table 9 Density, Signals and Addressing Items 4Gb (SDP) 8Gb (DDP)
X32 X32
CS CS CS 0:1
CK/CK /CKE CK/CK /CKE CK/CK /CKE 0:1
DQ [31:0]
DQS/DM [3:0]/ [3:0]
CA CA[9:0]
Bank Addr. BA[2:0]
Row Addr. R[13:0]
Column Addr C[9:0]
tREFI 3.9μs(TC≦85℃)
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3. Functional Block Diagram
Single Die, Single Channel Package
Figure 9 Functional Block Diagram for Single Die, Single Channel Package
VREFDQ
DQ[31:0]
DQS[3:0]
LPDDR3
Die 0
CKE
CK
CA[9:0]
VREFCA
VSS VDD1 VDD2 VDDQ VDDCA
ZQ
RZQ
ODT
Dual Die, Single Channel Package
Figure 10 Functional Block Diagram for Dual Die, Single Channel Package
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4. LPDDR Ball Descriptions
Symbol Type Function
CK ,CK Input Clock: CK and CK are differential clock inputs. All Double Data Rate
(DDR) CA inputs are sampled on both positive and negative edge of
CK. Single Data Rate (SDR) inputs, CS and CKE, are sampled at the
positive Clock edge. Clock is defined as the differential pair, CK and
CK . The positive Clock edge is defined by the crosspoint of a rising
CK and a falling CK . The negative Clock edge is defined by the
crosspoint of a falling CK and a rising CK .
CKE Input Clock Enable: CKE high activates, and CKE low deactivates internal
clock signals, and device input buffers and output drivers. Power
saving modes are entered and exited through CKE transitions. CKE is
considered part of the command code. CKE is sampled at the positive
Clock edge.
CS Input Chip Select: CS is considered part of the command code. CS is
sampled at the positive Clock edge.
CA0 – CA9
Input
Command/Address Inputs: Uni-directional command/address bus
inputs. Provide the command and address inputs according to the
command truth table. CA is considered part of the command code.
DM0-DM3 Input Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH coincident with that input
data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading matched the DQ
and DQS (or DQS ).
For x32 device, DM0 corresponds to the data on DQ0-DQ7, DM1
corresponds to the data on DQ8-DQ15.
DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds
to the data on DQ24-DQ31.
DQ0-DQ31 Input/output Data Bus: Bi-directional Input / Output data bus.
DQS0-3,
30DQS
Input/output
Data Strobe (Bi-directional, Differential): The data strobe is
bi-directional (used for read and write data) and Differential (DQS
DQS ). It is output with read data and input with write data.
DQS is edge-aligned to read data, and centered with write data. For
x32, DQS0 & 0DQS corresponds to the data on DQ0-DQ7,DQS1&
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Symbol Type Function
1DQS corresponds to the data on DQ8-DQ15, DQS2 & 2DQS
corresponds to the data on DQ16-DQ23, DQS3 & 3DQS corresponds
to the data on DQ24-DQ31.
ODT Input
On-Die Termination. The purpose of this signal is to enable and
disable DRAM DQ bus termination based on the specified mode
register settings.
ZQ Reference External Reference ball for ZQ Calibration. This ball is tied to an
eternal 240Ω resister (RZQ)
VDD1 Supply Core Power Supply 1: Core power supply
VDD2 Supply Core Power Supply 2: Core power supply
VDDQ Supply IO Power Supply: Power supply for Data Input/output buffers
VDDCA Supply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS , CK,
and CK input buffers.
VREFDQ Supply Reference Voltage: VREFDQ is reference voltage for all data input
buffers.
VREFCA Supply Reference Voltage for CA Command and Control lnput Receiver.
Reference voltage for all CA0-9, CKE, CS ,CK and CK
VSS Supply Ground
NC -- No Connection. No internal electrical connection.
NOTE 1: The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# = CK = CKb=CK_n=CK_c,
/DQS = DQS# = DQS =DQSb=DQS_n=DQS_c, /CS = CS# = CS = CSb=CS_b=CS_n.
NOTE2: Data includes DQ and DM.
5. Absolute Maximum Ratings
The stress rating of the device is listed in following table; it is possible to cause permanent damage if the
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value is greater than the stress rating. Exposure to absolute maximum rating conditions for extended
period of time may affect reliability of the device.
Symbol Parameter Min Max Units
VDD1 Voltage on VDD1 pin relative to Vss*1 -0.4 2.3 V
VDD2 Voltage on VDD2 pin relative to Vss*1 -0.4 1.6 V
VDDCA Voltage on VDDCA pin relative to Vss*1,2 -0.4 1.6 V
VDDQ Voltage on VDDQ pin relative to Vss*1,3 -0.4 1.6 V
Vin, Vout Voltage on any pin relative to Vss -0.4 1.6 V
Tstg Storage Temperature*4 -55 +125 C
Notes:
1. See “Power-Ramp” section for relationships between power supplies
2. VREFCA ≦0.6xVDDCA, however, VREFCA may be ≧ VDDCA provided that VREFCA≦300mV
3. VREFDQ ≦0.7xVDDQ, however, VREFDQ may be ≧ VDDQ provided that VREFDQ≦300mV
4. Storage Temperature is the case surface temperature on the center/top side of the LPDDR3 device. For the measurement
conditions, please refer to JESD 51-2 standard.
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6. AC/DC Operating Conditions
DC Operating Conditions
Symbol Voltage
DRAM Unit Min. Typ. Max.
VDD1 1.70 1.80 1.95 Core Power1 V
VDD2 1.14 1.20 1.30 Core Power2 V
VDDCA 1.14 1.20 1.30 Input Buffer Power V
VDDQ 1.14 1.20 1.30 I/O Buffer Power V
Notes:
1. VDD1 uses significantly less current than VDD2.
2. The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of
all noise up to 1MHz at the DRAM package ball.
Input Leakage Current
Parameter/Condition Symbol Min Max Unit Notes
Input Leakage
Current
IL -2 2 μA 1,2
VREF supply Leakage
Current
IVREF -1 1 μA 3,4
Notes:
1. For CA,CKE,CS , CK,CK . Any input 0V≦VIN ≦VDDCA(all other pins not under test=0V)
2. Although DM is for input only, the DM leakage shall match the DQS/ DQS output leakage
specification
3. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and
VREFDQ pins should be minimal.
4. VREFDQ =VDDQ/2 or VREFCA=VDDCA/2(All other pins not under test=0V)
Operating Temperature
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Parameter/Condition Symbol Min Max Unit
Operating Temperature TOPER -25 85 ℃
Notes
1. Operating Temperature is the case surface temperature on the center-top side of the LPDDR3 device. For
the measurement conditions, please refer to JESD51-2 standard.
2. Some applications require operation of LPDDR3 in the maximum temperature conditions in the Elevated
Temperature Range between 85℃ and 105℃ case temperature. For LPDDR3 devices, derating may be
necessary to operate in this range. See MR4 .
3. Either the device case temperature rating or the temperature sensor may be used to set an appropriate
refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature. When
using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that
applies for the Standard or Elevated Temperature Ranges. For example, Tcase may be above 85℃ when the
temperature sensor indicates a temperature of less than 85℃.
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7. AC/DC Input Level
AC and DC Logic Input Levels for Single-Ended Signals
Single-Ended AC and DC Input Levels for CA and CS Input
Symbol
Parameter
Value
Unit
Notes Min Max
VIHCA(AC)
AC Input logic HIGH VREF+0.150 Note2
V
1,2
VILCA(AC)
AC Input logic Low Note2 VREF-0.150
V
1,2
VIHCA(DC)
DC Input logic High VREF+0.100 VDDCA
V
1
VILCA(DC)
DC Input logic LOW VSS VREF-0.100
V
1
VREFCA(DC) Reference voltage for CA and CS input
inputs
0.49*VDDCA 0.51*VDDCA
V
3,4
Notes:
1. For CA and CS input only pins. VREF=VREF=VREFCA(DC)
2. Overshoot and Undershoot Specification
3. The ac peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ±1% VDDCA (for
reference: approx.±12mV).
4. For reference: approx. VDDCA/2±12mV.
Single-Ended AC and DC Input Levels for CKE
Symbol Parameter Min Max Unit Notes
VIHCKE CKE Input High Level 0.65xVDDCA Note 1 V 1
VILCKE CKE Input Low Level Note 1 0.35*VDDCA V 1
Note 1 Overshoot and Undershoot Specifications.
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Single-Ended AC and DC Input Levels for DQ and DM
Symbol Parameter Value
Unit Notes Min Max
VIHDQ(AC) AC input
logic high
VREF+0.150 Note2 V 1,2,5
VILDQ(AC) AC input
logic low
Note 2 VREF-0.150 V 1,2,5
VIHDQ(DC) DC input
logic high
VREF+0.100 VDDQ V 1
VILDQ(DC) DC input
logic low
VSS VREF-0.100 V 1
VREFDQ(DC)
(DQ ODT
Disabled)
Reference
Voltage for
DQ,DM
inputs
0.49*VDDQ 0.51*VDDQ V 3,4
VREFDQ(DC)
(DQ ODT
enabled)
Reference
Voltage for
DQ,DM
inputs
VODTR/2-0.01*VDDQ VODTR/2+0.01*VDDQ V 3,5,6
Note1: For DQ input only pins. VREF=VREFDQ(DC)
Note2: Overshoot and Undershoot Specification
Note3: The ac peak noise on VREFDQ may not allow VREFDQ to deviate from VREFDQ(DC) by more than ±1%
VDDQ (for reference: approx. ±12mV).
Note4: For reference: approx. VDDQ/2±12mV.
Note5: For reference: approx. VODTR/2±12mV.
Note6: RON and RODT nominal mode register programmed values are used for the calculation of VODTR. For
testing purposes a controller RON value of 50Ω is used.
VODTR= xVDDQRTTRON
RTTRON
2
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8. VREF Tolerance
The DC tolerance limits and AC noise limits for the reference voltages VREFCA and VREFDQ are
illustrated bellow. This figure shows a valid reference voltage VREF(t) as a function of time. VDD is
used in place of VDDCA for VREFCA, and VDDQ for VREFDQ. VREF(DC) is the linear average of
VREF(t) over a very long period of time (e.g., 1 second) and is specified as a fraction of the linear
average of VDDQ or VDDCA, also over a very long period of time (e.g., 1 second). This average
must meet the MIN/MAX requirements. Additionally, VREF(t) can temporarily deviate from
VREF(DC) by no more than ±1% VDD. VREF(t) cannot track noise on VDDQ or VDDCA if doing so
would force VREF outside these specifications.
VREF DC Tolerance and VREF AC Noise Limits
The voltage levels for setup and hold time measurements VIH(AC),VIH(DC),VIL(AC) and VIL(DC) are dependent on
VREF. “ VREF “shall be understood as VREF(DC) above.
This clarifies that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the LPDDR3 setup/hold specification and derating values need to include time and
voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the
specified limit (+/-1% of VDD) are included in LPDDR3 timings and their associated deratings.
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9. Input Signal- LPDDR3-1600 Input Signal
LPDDR3-1600 Input Signal
Notes:
1. Numbers reflect typical values.
2. For CA[9:0], CK, CK CS , VDD stands for VDDCA. For DQ, DM, DQS, and DQS and ODT, VDD stands for VDDQ.
3. For CA[9:0], CK, CK , CS , VSS stands for VSS. For DQ, DM, DQS, DQS and ODT, VSS stands for VSS.
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10. AC and DC Logic Input Levels for Differential Signals
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Differential Swing Requirements for clock (CK-CK ) and Strobe (DQS- DQS )
For CK and CK , VREF=VREFCA(DC),For DQS and DQS , VREF=VREFDQ(DC)
Differential AC and DC Input Levels
Symbol Parameter Value
Unit Notes Min Max
VIHdiff(DC) Differential Input high 2x(VIH(dc)-VREF) Note3 V 1
VILdiff(DC) Differential Input low Note3 2x(VIL(dc)-VREF) V 1
VIHdiff(AC) Differential Input high
ac
2x(VIH(ac)-VREF) Note3 V 2
VILdiff(AC) Differential Input low
ac
Note3 2x(VIH(ac)-VREF) V 2
Note1: Used to define a differential signal slew-rate. For CK-CK use VIH/VIL(dc) of CA and VREFCA, for DQS- DQS ,use
VIH/VIL(dc) of DQs and VREFDQ, if a reduced dc-high or dc-low level is used for a signal group, then the reduced level
applies also here.
Note 2: For CK- CK use VIH/VIL(ac) of CA and VREFCA, for DQS- DQS , use VIH/VIL(ac) of DQS and VREFDQ. If a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
Note3: These values are not defined, however the single-ended signals CK, CK , DQS and DQS need to be within
the respective limits(VIH(dc)max,VIL(dc)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to Overshoot and Undershoot Specifications.
Note4: For CK and CK ,VREF=VREFCA(DC). For DQS and DQS , VREF=VREFDQ(DC)
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Allowed time before ringback tDVAC for Strobe (DQQS- DQS )
Slew Rate nsV / tDVAC ps @ )(/ acLdiffVIH = 300mV 1600Mbps
min max
>8.0 48 -
8.0 48 -
7.0 46 -
6.0 43 -
5.0 40 -
4.0 35 -
3.0 27 -
<3.0 27 -
Allowed time before ringback tDVAC for Clock (CK-CK )
Slew Rate nsV / tDVAC ps @ )(/ acLdiffVIH = 300mV 1600Mbps
min max
>8.0 48 -
8.0 48 -
7.0 46 -
6.0 43 -
5.0 40 -
4.0 35 -
3.0 27 -
<3.0 27 -
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11. Single-Ended Requirement for Differential Signals
Each individual component of a differential signal (CK,CK , DQS, and DQS ) must also comply with certain requirements for
single-ended signals. CK and CK must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS, must meet
VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid transition.The applicable AC levels for CA
and DQ differ by speed-bin.
Note that while CA and DQ signal requirements are referenced to VREF, the single-ended components of
differential signals also have a requirement with respect to VDDQ/2 for DQS, DQS and VDDCA/2 for CK,CK .
The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended
components of differential signals, the requirement to reach VSEL(AC)max or VSEH(AC)min has no bearing on timing.
However, the requirement for reaching VSEL(AC)max or VSEH(AC)min adds a restriction on the common mode
characteristics of these signals (See tables: Single-End AC and DC Input Levels for CA and CS Inputs,
Single-Ended AC and DC Input Levels for DQ and DM).
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12. Differential Input Cross-Point Voltage
To ensure tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross-point voltage of differential input signals (CK,CK ,DQS, and DQS ) must meet the
specifications bellow. The differential input cross-point voltage (VIX) is measured from the actual cross
point of true and complement signals to the midlevel between VDD and Vss.
Cross-Point Voltage for Differential Input Signals (CK, CK , DQS, DQS )
Symbol
Paramete
r
LPDDR3 800-1066
Unit Min Max
VIXCA(AC) Differential input cross-point voltage relative to VDDCA/2 for CK and CK -120 +120 mV
VIXDQ(AC) Differential input cross-point voltage relative to VDDQ/2 for DQS and DQS
-120 +120 mV
Notes:
1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations
in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
2. For CK and CK , VREF = VREFCA(DC). For DQS and DQS , VREF = VREFDQ(DC).
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13. Slew Rate Definitions for Differential Input Signals
Differential Input Slew Rate Definition
Description Measured
Defined By from to
Differential input slew rate for rising edge
(CK-CK and DQS- DQS ).
VILdiffmax VILdiffmin maxmin VILdiffVIHdiff /DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS- DQS ).
VIHdiffmin VILdiffmax maxmin VILdiffVIHdiff /DeltaTFdiff
Note1: The differential signal (i.e. CK-CK and DQS- DQS ) must be linear between these thresholds.
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14. AC/DC Output Measurement Level
Single-Ended AC and DC Output Levels
Symbol Parameter Value Unit Notes
VOH(DC) DC output high measurement level
(for IV curve linearity)
0.9xVDDQ V 1
VOL(DC) ODT disabled DC output low
measurement
level(for IV curve
linearity)
0.1xVDDQ V 2
VOL(DC) ODT enabled VDDQ x
RONRTTRONx /9.01.0
V 3
VOH(AC) AC ouput high measurement level(for
output slew rate)
VREFDQ+0.12 V
VOL(AC) AC ouput low measurement level(for
output slew rate)
VREFDQ-0.12 V
IOZ Output Leakage
current(DQ,DM,DQS,
DQS )(DQ,DQS, DQS are disabled,
0V≦VOUT≦VDDQ
-5 μA
5 μA
Note1: IOH=-0.1mA
Note2: IOL=0.1mA
Note3: The minimum value is derived when using RTT, min and RON, max(±30% uncalibrated, ±15% calibrated)
Differential AC and DC Output Levels
Symbol Parameter Value Unit Notes
VOHdiff(AC) AC differential output
high measurement
level (for output SR)
+0.20xVDDQ V 1
VOLdiff(AC) AC differential output
low measurement
level (for output SR)
-0.20xVDDQ V 2
Note1: IOH=-0.1mA
Note2: IOL=0.1mA
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Single End Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown below.
Single-Ended Output Slew Rate Definition
Description
Defined by Measured
From To
Single-ended output slew rate for rising edge [VOH(AC) – VOL(AC)] / ΔTRSE VOL(AC) VOH(AC)
Single-ended output slew rate for falling edge [VOH(AC) – VOL(AC)] / ΔTFSE VOH(AC) VOL(AC)
Notes:
Output slew rate is verified by design and characterization, and may not be subject to production testing.
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Single-Ended Output Slew Rate
Parameter Symbol Value
Units Min1 Max2
Single-ended Output Slew
Rate (RON=40Ω±30%)
SRQse 1.5 4.0 V/ns
Output Slew Rate matching
Ratio (Pull-up to Pull-down)
0.7 1.4
Description: SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query Output), se: Single-ended Signals.
Note1: Measured with output reference load
Note2: The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down
drivers due to process variation.
Note3: The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).
Note4: Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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Differential Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and
measured between VOldiff(AC) and VOhdiff(AC) for differential signals as shown below.
Differential Output Slew Rate Definition
Description
Defined by Measured
From To
Differential output slew rate for rising edge [VOHdiff(AC) – VOLdiff(AC)] / ΔTRdiff VOLdiff(AC) VOHdiff(AC)
Differential output slew rate for falling edge [VOHdiff(AC) – VOLdiff(AC)] / ΔTFdiff VOHdiff(AC) VOLdiff(AC)
Note: Output slew rate is verified by design and characterization, and may not be subject to production testing.
Differential Output Slew Rate
Parameter Symbol Value
Units Min Max
Differential Output Slew
Rate(RON=40Ω±30%)
SRQdiff 3.0 8.0 V/ns
Description: SR: Slew Rate, Q:Query Output(like in DQ, which stands for Data-in, Query Output), diff:Differential
Signals
Note1: Measured with output reference load.
Note2: The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
Note3: Slew rates are measured under normal SSO conditions, with 50% of DQ signals per data byte switching.
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15. AC Overshoot/Undershoot Specification
Parameter
Value Unit
Maximum peak amplitude provided for overshoot area Max 0.35
V
Maximum peak amplitude provided for undershoot area Max 0.35
V
Maximum area above VDD Max 0.10
0.20
V
Maximum area below VSS Max 0.10
0.20
V
Note1: VDD stands for VDDCA for CA 0:9 ,CK,CK ,CS , and CKE. VDD stands for VDDQ for DQ,DM,ODT, DQS and
DQS .
Note2: VSS stands for VSS for CA 0:9 ,CK,CK ,CS , and CKE. VSS stands for VSS for DQ,DM,ODT, DQS and DQS
Note3: Maximum peak amplitude values are referenced from actual VDD and VSS values.
Note4: Maximum area values are referenced from maximum operating VDD and VSS values.
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16. AC Timing
Notes 1-4 apply to all parameters. Notes begin below table.
Parameter Symbol Min./
Max.
Data Rate Unit
1600
Maximum clock frequency fCK - 800 MHz
Clock Timing
Average clock period tCK(avg) Min 1.25 ns
Max 100
Average HIGH pulse width tCH(avg) Min 0.45 tCK(avg)
Max 0.55
Average LOW pulse width tCL(avg) Min 0.45 tCK(avg)
Max 0.55
Absolute clock period tCK(abs) Min tCK(avg)MIN+tJIT(per)MIN ns
Absolute clock HIGH pulse width tCH(abs) Min 0.43 tCK(avg)
Max 0.57
Absolute clock LOW pulse width tCL(abs) Min 0.43 tCK(avg)
Max 0.57
Clock period jitter (with supported jitter) tJIT(per),allowed Min -70 ps
Max 70
Max. clock jitter between two consecutive
clock cycles (with allowed jitter)
tJIT(cc),allowed Max 140 ps
Duty cycle jitter(with supported jitter) tJIT(duty),allowed Min Min((tCH(abs),min-tCH(avg),min),(tCL(
abs),min-tCL(avg),min))xtCK(avg)
ps
Max Max((tCH(abs),max-tCH(avg),max),(tC
L(abs),max-tCL(avg),min))xtCK(avg)
Cumulative errors across 2 cycles tERR(2per),
allowed
Min -103 ps
Max 103
Cumulative errors across 3 cycles tERR(3per),
allowed
Min -122 ps
Max 122
Cumulative errors across 4 cycles tERR(4per),
allowed
Min -136 ps
Max 136
Cumulative errors across 5 cycles tERR(5per),
allowed
Min -147 ps
Max 147
Cumulative errors across 6 cycles tERR(6per),
allowed
Min -155 ps
Max 155
Cumulative errors across 7 cycles tERR(7per),
allowed
Min -163 ps
Max 163
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Cumulative errors across 8 cycles tERR(8per),
allowed
Min -169 ps
Max 169
Cumulative errors across 9 cycles tERR(9per),
allowed
Min -175 ps
Max 175
Cumulative errors across 10 cycles tERR(10per),
allowed
Min -180 ps
Max 180
Cumulative errors across 11 cycles tERR(11per),
allowed
Min -184 ps
Max 184
Cumulative errors across 12 cycles tERR(12per),
allowed
Min -188 ps
Max 188
Clock Timing
Cumulative errors across
n=13,14,15…,19,20 cycles
tERR(nper),
allowed
Min tERR(nper),allowed
MIN=(1+0.68ln(n))xtJIT(per),allowed
MIN
ps
Max tERR(nper),allowed
MAX=(1+0.68ln(n))xtJIT(per),allowed
MAX
ZQ Calibration Parameters
Initialization calibration time tZQINIT MIN 1 μS
Long calibration time tZQCL MIN 360 ns
Short calibration time tZQCS MIN 90 ns
Calibration RESET time tZQRESET MIN Max(50ns,3nCK) ns
READ Parameters5
DQS output access time from CK/ CK tDQSCK Min 2500 ps
Max 5500
DQSCK delta short tDQSCKDS Max 220 ps
DQSCK delta medium tDQSCKDM Max 511 ps
DQSCK delta long tDQSCKDL Max 614 ps
DQS-DQ skew tDQSQ Max 135 ps
DQS output HIGH pulse width tQSH MIN tCH(abs)-0.05 tCK(avg)
DQS output LOW pulse width tQSL MIN tCL(abs)-0.05 tCK(avg)
DQ/DQS output hold time from DQS tQH MIN Min(tQSH,tQSL) ps
READ preamble tRPRE MIN 0.9 tCK(avg)
READ postamble tRPST MIN 0.3 tCK(avg)
DQS LOW-Z from clock tLZ(DQS) MIN tDQSCK (MIN)-300 ps
DQ LOW-Z from clock tLZ(DQ) MIN tDQSCK, (MIN)-300 ps
DQS HIGH-Z from clock tHZ(DQS) Max tDQSCK ,(MAX)-100 ps
DQ HIGH-Z from clock tHZ(DQ) MAX tDQSCK ,(MAX)+(1.4xtDQSQ,(MAX)) ps
WRITE Parameters5
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DQ and DM input hold time(VREF based) tDH MIN 150 ps
DQ and DM input setup time(VREF based) tDS MIN 150 ps
DQ and DM input pulse width tDIPW MIN 0.35 tCK(avg)
Write command to 1st DQS latching
transition
tDQSS MIN 0.75 tCK(avg)
MAX 1.25
DQS input high-level width tDQSH MIN 0.4 tCK(avg)
DQS input low-level width tDQSL MIN 0.4 tCK(avg)
DQS falling edge to CK setup time tDSS MIN 0.2 tCK(avg)
DQS falling edge hold time from CK tDSH MIN 0.2 tCK(avg)
Write postamble tWPST MIN 0.4 tCK(avg)
Write preamble tWPRE MIN 0.8 tCK(avg)
CKE Input Parameters
CKE minimum pulse width(HIGH and
LOW pulse width)
tCKE MIN Max(7.5ns,3nCK) ns
CKE input setup time tISCKE MIN 0.25 tCK(avg)
CKE input hold time tIHCKE MIN 0.25 tCK(avg)
Command path disable delay tCPDED MIN 2 tCK(avg)
Command Address Input Parameters5
Address and control input setup time tISCA MIN 150 ps
Address and control input hold time tIHCA MIN 150 ps
CS input setup time tISCS MIN 270 ps
CS input hold time tIHCS MIN 270 ps
Address and control input pulse width tIPWCA MIN 0.35 tCK(avg)
CS input pulse width tIPWCS MIN 0.7 tCK(avg)
Boot Parameters(10MHz-55MHz)16,17,18
Clock cycle time tCKb MAX 100 ns
MIN 18
CKE input setup time tISCKEb MIN 2.5 ns
CKE input hold time tIHCKEb MIN 2.5 ns
Address and control input setup time tISb MIN 1150 ps
Address and control input hold time tIHb MIN 1150 ps
DQS output data access time from CK/
CK
tDQSCKb MIN 2 ns
MAX 10
Parameter Symbol Min./
Max. Data Rate Unit
Data Strobe edge to output data edge tDQSQb MAX 1.2 ns
Mode Register Parameters
MODE REGISTER WRITE command period tMRW MIN 10 tCK(avg)
MODE REGISTER READ command period tMRR MIN 4 tCK(avg)
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Additional time after tXP has expired until
the MRR command may be issued
tMRRI MIN tRCD(min) ns
Core Parameters19
READ latency RL MIN 12 tCK(avg)
WRITE latency(Set A) WL MIN 6 tCK(avg)
WRITE latency(Set B) WL MIN 9 tCK(avg)
ACTIVATE-to-ACTIVATE command
period
tRC MIN tRAS +tRPab(with all-bank
precharge) tRAS +tRpb(with
per-bank precharge)
ns
CKE minimum pulse width during SELF
FERESH(low pulse width during SELF
REFRESH)
tCKESR MIN Max(15ns,3nCK) ns
SELF REFRESH exit to next valid
command delay
tXSR MIN Max(tRFCab+10ns,2nCK) ns
Exit power-down to next valid command
delay
tXP MIN Max(7.5ns,3nCK) ns
CAS-to-CAS delay tCCD MIN 4 tCK(avg)
Internal READ to PRECHARGE
command delay
tRTP MIN Max(7.5ns,4nCK) ns
RAS-to-CAS delay tRCD(fast) MIN Max(15ns, 3nCK) ns
tRCD(typ) Max(18ns, 3nCK)
tRCD(slow) Max(24ns, 3nCK)
Row precharge time (single bank) tRPpb(fast) MIN Max(15ns, 3nCK) ns
tRPpb(typ) Max(18ns, 3nCK)
tRPpb(slow) Max(24ns, 3nCK)
Row precharge time (all bank) tRPpab(fast) MIN Max(18ns, 3nCK) ns
tRPpab(typ) Max(21ns, 3nCK)
tRPpab(slow) Max(27ns, 3nCK)
Row active time tRAS MIN Max(42ns, 3nCK) ns
MAX 70 μs
WRITE recovery time tWR MIN Max(15ns, 4nCK) ns
Internal WRITE-to-READ command delay tWTR MIN Max(7.5ns, 4nCK) ns
Active bank A to active bank B tRRD MIN Max(10ns, 2nCK) ns
Four-bank ACTIVATE window tFAW MIN Max(50ns, 8nCK) ns
Minimum deep power-down time tDPD MIN 500 μs
ODT Parameters
Asynchronous RTT turn-on delay from
ODT input
tODTon MIN 1.75 ns
MAX 3.5
Asynchronous RTT turn-off delay from
ODT input
tODToff MIN 1.75 ns
MAX 3.5
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Automatic RTT turn-on delay after READ
data
tAODTon MAX tDQSCK+1.4xtDQSQmax+tCK
(avg,min)
ps
Automatic RTT turn-off delay after READ
data
tAODToff MIN tDQSCK,min-300 ps
RTT disable delay from power down,
self-refresh and deep power down entry
tODTd MIN 12 ns
RTT enable delay from power down and
self refresh exit
tODTe MAX 12 ns
CA Training Parameters
First CA calibration command after CA
calibration model is programmed
tCAMRD MIN 20 tCK(avg)
First CA calibration command after CKE is
LOW
tCAENT MIN 10 tCK(avg)
CA calibration exit command after CKE is
HIGH
tCAEXT MIN 10 tCK(avg)
CKE LOW after CA calibration mode is
programmed
tCACKEL MIN 10 tCK(avg)
CKE HIGH after the last CA calibration
results are driven
tCACKEH MIN 10 tCK(avg)
Data out delay after CA training calibration
command is programmed
tADR MAX 20 ns
MRW CA exit command to DQ tri-state tMRZ MIN 3 ns
CA calibration command to CA calibration
command delay
tCACD MIN RU(tADR+2xtCK) tCK(avg)
Write Leveling Parameters
DQS/ DQS delay after write leveling
mode is programmed
tWLDQSEN MIN 25 ns
MAX -
First DQS/ DQS edge after write leveling
mode is programmed
tWLMRD MIN 40 ns
MAX -
Write leveling output delay tWLO MIN 0 ns
MAX 20
Write leveling hold time tWLH MIN 175 ps
Write leveling setup time tWLS MIN 175 ps
Mode register set command delay tMRD MIN MAX(14ns,10nCK) ns
MAX -
Temperatue Derating
DQS output access time from CK/ CK
(derated)
tDQSCK MAX 5620 ps
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RAS-to CAS delay(derated) tRCD MIN tRCD+1.875 ns
ACTIVATE-to ACTIVATE command
period(derated)
tRC MIN tRC+1.875 ns
Row active time(derated) tRAS MIN tRAS+1.875 ns
Row precharge time(derated) tRP MIN tRP+1.875 ns
Active bank A to active bank B(derated) tRRD MIN tRRD+1.875 ns
Note 1: Frequency values are for reference only. Clock cycle time(tCK) is used to determine device capabilities.
Note2: All AC timings assume an input slew rate of 2V/ns for single-ended signals.
Note3: Measured with 4V/ns differential CK/ CK slew rate and nominal VIX.
Note4: All timing and voltage are defined at the ball.
Note5: READ, WRITE, and input setup and hold values are referenced to VREF.
Note6: tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane)
within a contiguous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by
design. Temperate drift in the system is <10℃/s. Values do not include clock jitter.
Note7: tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte line)
within a 1.6μs rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is
<10℃/s. Values do not include clock jitter.
Note8: tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements(in a byte line)
within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is
<10℃/s. Values do not include clock jitter.
Note9: For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses
the transition threshold(VTT). tHz and tLZ transitions occur in the same access time(when respect to clock) as valid
data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output
is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving(for tRPRE,tLZ(DQS) and tLZ(DQ)). The
figure below shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ) or
begins driving tLZ(DQS) and tLZ(DQ) by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent.
Note10: Output Transition Timing
Figure 11 tLZ and tHZ Method for Translation and Endpoints Calculating
Note11: The parameters tLZ(DQS),tLZ(DQ),tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and
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tRPST are determined from the differential signal DQS/ DQS
Note12: Measured from the point when DQS/ DQS begins driving the signal to the point when DQS/ DQS begins driving the
first rising strobe edge.
Note 13: Measured from the last falling strobe edge of DQS/ DQS to the point when DQS/ DQS finishes driving the signal.
Note14: CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK/ CK crossing.
Note15: CKE input hold-time is measured from CK/ CK crossing to CKE reaching a HIGH/LOW voltage level.
Note16: Input setup/hold-time for signal (CA[9:0], CS ).
Note17: To ensure device operation before the device is configured, a number of AC boot timing parameters are defined in the
table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCK6).
Note18: Mobile LPDDR3 devices set some mode register default values upon receiving a RESET(MRW) command, as specified in
Mode Register Definition.
Note19: The output skew parameters are measured with default output impedance settings using the reference load.
Note20: The minimum tCK column applies only when tCK is greater than 6ns.
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17. HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not intended as a precise representation of any particular system
environment or a depiction of the actual load presented by a production tester. System designers
should use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers correlate to their production test conditions, generally with one or more
coaxial transmission lines terminated at the tester electronics.
HSUL_12 Driver Output Reference Load for Timing and Slew Rate
Notes:
All output timing parameter values (tDQSCK,tDQSQ,tHZ,tRPRE,etc.) are reported with respect to this reference load. This
reference load is also used to report slew rate.
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ODT Levels and I-V Characteristics
On-Die Termination effective resistance, RTT is defined by mode register MR11 0:1 .ODT is applied to the DQ,
DM, and DQS/ DQS pins. A functional representation of the on-die termination is shown in the figure below.
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18. Input/Output Capacitance
Parameter Symbol Min Max Units Notes
Input capacitance, CK and
CK
CCK 0.5 1.2 pF 1,2
Input capacitance delta,
CK and CK
CDCK 0 0.15 pF 1,2,3
Input capacitance, all
other input-only pins
CI 0.5 1.1 pF 1,2,4
Input capacitance delta,
all other input-only pins
CDI -0.20 0.20 pF 1,2,5
Input/output capacitance,
DQ,DM,DQS, DQS
CIO 1.0 1.8 pF 1,2,6,7
Input/output capacitance
delta,DQS, DQS
CDDQS 0 0.2 pF 1,2,7,8
Input/output capacitance
delta,DQ,DM
CDIO -0.25 0.25 pF 1,2,7,9
Input/output capacitance
ZQ Pin
CZQ 0 2.0 pF 1,2
(TOPER,VDDQ=1.14-1.3V;VDDCA=1.14-1.3V;VDD1=1.7-1.95V,VDD2=1.14-1.3V)
Note1: This parameter applies to die device only(does not include package capacitance)
Note2: This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured
according to JEP147(procedure for measuring input capacitance using a vector network analyzer(VNA) with VDD!,
VDD2,VDDQ,VSS,VSSVSS applied and all other pins floating.
Note3: Absolute value of CCK-C CK
Note4: CI applies to CS ,CKE,CA0-CA9,ODT
Note5: CDI=CI-0.5*(CCK+C CK )
Note6: DM loading matches DQ and DQS.
Note7: MR3 I/O configuration DS OP3-OP0=0001B(34.3Ω typical)
Note8: Absolute value of CDQS and C DQS
Note9: CDIO =CIO-0.5*(CDQS+C DQS ) in byte-lane.
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19. IDD Specification
IDD values are for the entire operating voltage range, and all of them are for the entire standard range.
IDD Specification Parameters and Operating Conditions
Notes 1, 2, 3 apply for all values.
Parameter/Condition Symbol Power Supply Notes
Operating one bank active-precharge current:
tCK=tCK(min),atRC=tRC(min),CKE is HIGH, CS is HIGH between valid
commands, CA bus inputs are switching, Data bus inputs are stable, ODT
is disabled.
IDD01 VDD1
IDD02 VDD2
IDD0in VDDCA,VDDQ 4
Idle power-down standby current: tCK=tCK(min),CKE is low, CS is
HIGH;All banks are idle;CA bus input are switching;Data bus input are
stable;ODT is disabled
IDD2P1 VDD1
IDD2P2 VDD2
IDD2P,in VDDCA,VDDQ 4
Idle power-down standby current with clock stop:
CK=LOW; CK =HIGH;CKE is LOW; CS is HIGH;All banks are idle;CA
bus input are stable;Data bus input are stable;ODT is disabled
IDD2PS1 VDD1
IDD2PS2 VDD2
IDD2PS,in VDDCA,VDDQ 4
Idle non-power down standby current:
tCK=tCK(min);CKE is HIGH; CS is HIGH;All banks are idle;CA bus input
are switching;Data bus input are stable;ODT is disabled
IDD2N1 VDD1
IDD2N2 VDD2
IDD2N,in VDDCA,VDDQ 4
Idle non-power-down standby current with clock stopped:
CK=LOW; CK =HIGH;CKE is HIGH; CS is HIGH;All banks are idle;CA
bus inputs are stable;Data bus inputs are stable;ODT is disabled
IDD2NS1 VDD1
IDD2NS2 VDD2
IDD2NS,in VDDCA,VDDQ 4
Active power don standby current:
tCK=tCK(min);CKE is LOW; CS is HIGH;One bank is active;CA bus inputs
are switching;Data bus inputs are stable;ODT is disabled
IDD3P1 VDD1
IDD3P2 VDD2
IDD3P,in VDDCA,VDDQ 4
Active power-down standby current with clock stop:
CK=LOW; CK =HIGH;CKE is LOW; CS is HIGH;One bank is active;CA
bus inputs are stable;Data bus inputs are stable;ODT is disabled
IDD3PS1 VDD1
IDD3PS2 VDD2
IDD3PS,in VDDCA,VDDQ 4
Active non-power down standby current:
tCK=tCK(min);CKE is HIGH; CS is HIGH;One bank is active;CA bus
inputs are switching;Data bus inputs are stable;ODT is disabled
IDD3N1 VDD1
IDD3N2 VDD2
IDD3N,in VDDCA,VDDQ 4
Active non-power-down standby current with clock stopped:
CK=LOW, CK =HIGH;CKE is HIGH; CS is HIGH;One bank is active; CA
bus inputs are stable;Data bus inputs are stable; ODT is disabled
IDD3NS1 VDD1
IDD3NS2 VDD2
IDD3NS,in VDDCA,VDDQ 4
Operating burst READ current:
tCK=tCK(min); CS is HIGH between valid commands;One bank is
active;BL=8,RL=RL(min);CA bus inputs are switching;50% data change
each burst transfer;ODT is disabled
IDD4R1 VDD1
IDD4R2 VDD2
IDD4R,in VDDCA
IDD4RQ VDDQ 5
Operating burst WRITE current: IDD4W1 VDD1
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Parameter/Condition Symbol Power Supply Notes
tCK=tCK(min); CS is HIGH between valid commands;One bank is
active;BL=8,WL=WL(min);CA bus inputs are switching;50% data change
each burst transfer; ODT is disabled
IDD4W2 VDD2
IDD4W,in VDDCA,VDDQ 4
All-bank REFRESH burst current:
tCK=tCK(min);CKE is HIGH between valid
commands;tRC=tRFCab(min);Burst refresh;CA bus inputs are
switching;Data bus inputs are stable;ODT is disabled.
IDD51 VDD1
IDD52 VDD2
IDD5IN VDDCA,VDDQ 4
All-bank REFRESH average current:
tCK=tCK(min);CKE is HIGH between valid commands;tRC=tREFI;CA bus
inputs are switching;Data bus inputs are stable;ODT is disabled
IDD5AB1 VDD1
IDD5AB2 VDD2
IDD5AB,in VDDA,VDDQ 4
Per-bank REFRESH average current:
tCK=tCK(min);CKE is HIGH between valid commands,tRC=tREFI/8;CA bus
inputs are switching;Data bus inputs are stable;ODT is disabled
IDD5PB1 VDD1
IDD5PB2 VDD2
IDD5PB,in VDDCA,VDDQ 4
Self refresh current (TC≦+85℃):
CK=LOW, CK =HIGH;CKE is LOW;CA bus inputs are stable;Data bus
inputs are stable;Maximum 1x self refresh rate;ODT is disabled
IDD61 VDD1 6,7
IDD62 VDD2 6,7
IDD6IN VDDCA,VDDQ 4,7
Note1: Published IDD values are the maximum of the distribution of the arithmetic menu.
Note2: ODT disabled:MR11 0:2 =000B
Note3: IDD current specifications are tested after the device is properly initialized
Note4: Measured currents are the summation of VDDQ and VDDCA.
Note5: Guaranteed by design with output load=5pF and RON=40 ohm.
Note6: The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh before going into the
elevated temperature range.
Note7: This is the general definition that applies to full-array SELF REFRESH.
Note8: Published IDD values of DDP can support x32 and x16 I/O configuration.
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IDD6 Partial Array Self-Refresh Current
Parameter Unit
IDD6 Partial Array Self-Refresh
Current
Full Array μA
1/2 Array μA
1/4 Array μA
1/8 Array μA
Note1: IDD6 currents are measured using bank-masking only.
Note2: IDD values published are the maximum of the distribution of the arithmetic mean.
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IDD Specifications
Parameter Condition Symbol Power Supply SDP DDP Unit
Operating one bank
active-precharge current
IDD01 VDD1 15 30 mA
IDD02 VDD2 70 140
IDD0in VDDCA, VDDQ 12 24
Idle power-down standby
current
IDD2P1 VDD1 600 1200 μA
IDD2P2 VDD2 800 1600
IDD2P,in VDDCA, VDDQ 120 240
Idle power-down standby
current with clock stop
IDD2PS1 VDD1 600 1200 μA
IDD2PS2 VDD2 800 1600
IDD2PS,in VDDCA, VDDQ 120 240
Idle non-power-down
standby current
IDD2N1 VDD1 2 4 mA
IDD2N2 VDD2 24 48
IDD2N,in VDDCA, VDDQ 12 24
Idle non-power-down
standby current with clock
stopped
IDD2NS1 VDD1 1.7 3.4 mA
IDD2NS2 VDD2 10 20
IDD2NS,in VDDCA, VDDQ 6 12
Active power-down
standby current
IDD3P1 VDD1 1000 2000 μA
I V 7.5 15 mA
IDD3P,in VDDCA, VDDQ 150 300 μA
Active power-down
standby current with clock
stop
IDD3PS1 VDD1 1300 2600 μA
IDD3PS2 VDD2 7.5 15 mA
IDD3PS,in VDDCA, VDDQ 150 300 μA
Active
non-power-down standby
current
IDD3N1 VDD1 2 4 mA
IDD3N2 VDD2 25 50
IDD3N,in VDDCA, VDDQ 12 24
Active
non-power-down standby
current with clock stopped
IDD3NS1 VDD1 2 4 mA
IDD3NS2 VDD2 20 40
IDD3NS,in VDDCA, VDDQ 6 12
Operating burst READ
current
IDD4R1 VDD1 3 6 mA
IDD4R2 VDD2 300 600
IDD4R,in VDDCA 12 24
Operating burst
WRITE current
IDD4W1 VDD1 3 6 mA
IDD4W2 VDD2 300 600
IDD4W,in VDDCA, VDDQ 45 90
All-bank REFRESH
burst current
IDD51 VDD1 20 40 mA
IDD52 VDD2 150 300
IDD5IN VDDCA, VDDQ 12 24
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Parameter Condition Symbol Power Supply SDP DDP Unit
All-bank REFRESH
average current
IDD5AB1 VDD1 5 10 mA
IDD5AB2 VDD2 25 50
IDD5AB,in VDDCA, VDDQ 12 24
Per-bank REFRESH
average current
IDD5PB1 VDD1 5 10 mA
IDD5PB2 VDD2 25 50
IDD5PB,in VDDCA, VDDQ 12 24
Self refresh current
(Full Array; TC ʀ +85±C)
IDD61 (full Array) VDD1 1000 2000 μA
IDD62 (full Array) VDD2 4000 8000
IDD6IN (full Array) VDDCA, VDDQ 120 240
Self refresh current
(1/2 Array; TC ʀ +85±C)
IDD61 (1/2 Array) VDD1 950 1900
IDD62 (1/2 Array) VDD2 2300 4600
IDD6IN (1/2 Array) VDDCA, VDDQ 120 240
Self refresh current
(1/4 Array; TC ʀ +85±C)
IDD61 (1/4 Array) VDD1 900 1800
IDD62 (1/4 Array) VDD2 1500 3000
IDD6IN (1/4 Array) VDDCA, VDDQ 120 240
Self refresh current
(1/8 Array; TC ʀ +85±C)
IDD61 (1/8 Array) VDD1 850 1700
IDD62 (1/8 Array) VDD2 1060 2120
IDD6IN (1/8 Array) VDDCA, VDDQ 120 240
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20. Electrical Characteristic and AC Timing
REFRESH Requirement
LPDDR3 Refresh Requirement Parameters
Parameter Symbol 4Gb(SDP) 8Gb(DDP) Unit
Number of Banks 8
Refresh Window:Tcase≦85℃ tREFW 32 ms
Refresh Window:1/2-Rate Refresh tREFW 16 ms
Refresh Window:1/4-Rate Refresh tREFW 8 ms
Required number of REFRESH
commands (min)
R 8,192 --
Average time between
REFRESH commands (for
reference only)
Tcase≦85℃
REFab tREFI 3.9 μS
REFpb tREFIpb 0.4875 μS
Refresh Cycle Time tRFCb 130 130 ns
Per Bank Refresh Cycle Time tRFCpb 60 60 ns
LPDDR3 Read and Write Latencies
Parameter Value Unit
Max. Clock
Frequency
166 400 533 600 667 733 800 MHz
Max. Data Rate 333 800 1066 1200 1333 1466 1600 Mbps
Average Clock
Period
6 2.5 1.875 1.67 1.5 1.36 1.25 ns
Read Latency 31 6 8 9 10 11 12 tCK(avg)
Read Latency(Set
A)
11 3 4 5 6 6 6 tCK(avg)
Write
Latency(Set B)2
11 3 4 5 8 9 9 tCK(avg)
Note1: RL=3/WL=1 setting is an optional feature. Refer to MR0 OP<7>
Note2: Write Latency (Set B) support is an optional feature. Refer to MR0 OP<6>
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21. CA and CS Setup, Hold and Derating
For all input signals(CA and CS ) the total tIS(setup time) and tIH(hold time) required is calculated
by adding the datasheet tIS(base) and tIH(base) value(see tIS/tIH Base Table) to the tIS and
tIH derating value(see tIS/tIH Derating Table) respectively. Example:tIS (total setup
time)=tIS(base)+ .tIS
Setup(tIS) nominal slew rate for a rising slignal is defined as the slew rate between the last crossing
of VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signl is
defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac) max. If
the actual signal is always earlier than the nominal slew rate line between shaded „VREF(dc) to ac
region), use nominal slew rate for derating value(see following typical slew rate Figure of tIS). If the
actual signal is later than the nominal slew rate line anywhere between shaded‟ VREF(dc) to ac region,
the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating
value (see following angent line figure of tIS).
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate betwwn the last crossing of
VIL(dc)max and the first crossing of VREF(dc). If the actual signal is always later than the nominal
slew rate line between shaded „dc to VREF(dc) region,use nominal slew rate for derating value(see
following slew rate Figure of tIH), If the actual signal is earlier than the nominal slew rate line
anywhere between shaded „dc to VREF(dc) region, the slew rate of a tangent line to the actual
signal from the dc level to VREF(dc) level is used for derating value (see following angent line
figure of tIH).
For a valid transition the input signal has to remain above/below VIH/IL (ac) for some time tVAC
(see table of required tVAC for CA).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached VIH/IL (ac) at the time of the rising clock transition) a valid input signal is still required
to complete the transition and reach VIH/IL(ac).
For slew rates in between the value listed in derating Table, the derating values may be obtained by
linear interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
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CA Setup and Hold Base-Values
unit ps Data Rate Reference
Value
tlSCA(base) 75 VIH/L(ac)=VREF(dc)+/-150mV
tlSCA(base) - VIH/L(ac)=VREF(dc)+/-135mV
tlHCA(base) 100 VIH/L(ac)=VREF(dc)+/-100mV
Note1 AC/DC referenced for 2V/ns CA slew rate and 4Vns differential CK- CK slew rate.
CS Setup and Hold Base-Values
unit ps Data Rate Reference
1600
tlSCS(base) 195 VIH/L(ac)=VREF(dc)+/-150mV
tlSCS(base) - VIH/L(ac)=VREF(dc)+/-135mV
tlHCS(base) 220 VIH/L(ac)=VREF(dc)+/-100mV
Note1 AC/DC referenced for 2V/ns CS slew rate and 4Vns differential CK- CK slew rate.
Derating Values tlS/tIH-ac/dc based AC150
tISCA, tIHCA, tISCS, tIHCS derating in ps AC/DC based
AC150 Threshold->VIH(ac)=VREF(dc)+150mV,VIL(ac)=VREF(dc)-150mV
DC100 Threshold->VIH(dc)=VREF(dc)+100mV,VIL(dc)=VREF(dc)-150mV
CK, CK Differential Slew Rate
8.0V/ns 7.0V/ns 6.0V/ns 5.0V/ns 4.0V/ns 3.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CA, CS
Slew
Rate(v/n
s)
4.0 38 25 38 25 38 25 38 25 38 25 -- --
3.0 -- -- 25 17 25 17 25 17 25 17 38 29
2.0 -- -- -- -- 0 0 0 0 0 0 13 13
1.5 -- -- -- -- -- -- -25 -17 -25 -17 -12 -4
Note1: Cell contents shaded in yellow are defined as ‘not supported’
Derating Values tlS/tIH-ac/dc based AC135
tISCA, tIHCA, tISCS, tIHCS derating in ps AC/DC based
AC135 Threshold->VIH(ac)=VREF(dc)+135mV,VIL(ac)=VREF(dc)-135mV
DC100 Threshold->VIH(dc)=VREF(dc)+100mV,VIL(dc)=VREF(dc)-100mV
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CK, CK Differential Slew Rate
8.0V/ns 7.0V/ns 6.0V/ns 5.0V/ns 4.0V/ns 3.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CA, CS
Slew
Rate(v/n
s)
4.0 34 25 34 25 34 25 34 25 34 25 -- --
3.0 -- -- 23 17 23 17 23 17 23 17 34 29
2.0 -- -- -- -- 0 0 0 0 0 0 11 13
1.5 -- -- -- -- -- -- -23 -17 -23 -17 -12 -4
Note1: Cell contents shaded in yellow are defined as ‘not supported’
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Required time tVAC above VIH(ac) )(acbelowVIL for valid transition for CA
Slew Rate (V/ns) tVAC at 150mV(ps) 1600Mb/s
Min Max
>4.0 48 --
4.0 48 --
3.5 46 --
3.0 43 --
2.5 40 --
2.0 35 --
1.5 27 --
<1.5 27 --
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22. Data Setup, Hold and Slew Rate Derating
For all input signals (DQ,DM) the total tDS (setup time) and tDH(hold time) required is calculated by adding
the data sheet tDS(base) and tDH(base) value (see the following tDS/tDH base table) to the
tDHtDSand (see tDS/tDH derating table) derating value respectively. Example: tDS(total setup
tome)=tDS(base)+ tDS
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max(see following
typical slew rate Figure of tDS). If the actual signal is always earlier thaan the nominal slew rate line
between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the atual signal is later
than the nominal slew rate line anywhere between shaded “VREF(dc) to ac region, the slew rate of a
tangent line to the actual signal from the ac level to dc level is used for derating value(see following angent
line figure of tDS).
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold(tDH) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc)(see following
typical slew rate Figure of tDH). If the actual signal is always later than the nominal slew rate line between
shaded’dc level of VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier
than the nominal slew rate line anywhere between shaded’dc to VREF(dc) region’, the slew rate of a
tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see following
angent line figure of tDH).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC(see table of
required tVAC for DQ/DM).
Although for slow slew rates the total setup time might be negtive(i.e. a valid input signal will not have
reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete
the transition and reach VIH/IL(ac). For slew rates in between the values listed in the tables the derating
values may be obtained by linear interpolation. These values are typically not subject to production test.
They are verifiede by design and characterization.
Data Setup and Hold Base-Values (>400MHz,1V/ns Slew Rate)
unit ps Data Rate Reference
1600
tDS(base) 75 VIH/L(ac)=VREF(dc)+/-150mV
tDS(base) - VIH/L(ac)=VREF(dc)+/-135mV
tDH(base) 100 VIH/L(ac)=VREF(dc)+/-100mV
Note1 AC/DC referenced for 2V/ns DQ,DM slew rate and 4Vns differential DQS- DQS slew rate.
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Derating Values tDS/tDH-ac/dc based AC150
tDS tDH, derating in ps AC/DC based
AC150 Threshold->VIH(ac)=VREF(dc)+150mV,VIL(ac)=VREF(dc)-150mV
DC100 Threshold->VIH(dc)=VREF(dc)+100mV,VIL(dc)=VREF(dc)-100mV
DQS, DQS Differential Slew Rate
8.0V/ns 7.0V/ns 6.0V/ns 5.0V/ns 4.0V/ns 3.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
DQ,DM
Slew
Rate(v/n
s)
4.0 38 25 38 25 38 25 38 25 38 25 -- --
3.0 -- -- 25 17 25 17 25 17 25 17 38 29
2.0 -- -- -- -- 0 0 0 0 0 0 13 13
1.5 -- -- -- -- -- -- -25 -17 -25 -17 -12 -4
Note1: Cell contents shaded in yellow are defined as ‘not supported’
Derating Values tlS/tIH-ac/dc based AC135
tDS, tDH derating in ps AC/DC based
AC135 Threshold->VIH(ac)=VREF(dc)+135mV,VIL(ac)=VREF(dc)-135mV
DC100 Threshold->VIH(dc)=VREF(dc)+100mV,VIL(dc)=VREF(dc)-100mV
CK, CK Differential Slew Rate
8.0V/ns 7.0V/ns 6.0V/ns 5.0V/ns 4.0V/ns 3.0V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CA, CS
Slew
Rate(v/n
s)
4.0 34 25 34 25 34 25 34 25 34 25 -- --
3.0 -- -- 23 17 23 17 23 17 23 17 34 29
2.0 -- -- -- -- 0 0 0 0 0 0 11 13
1.5 -- -- -- -- -- -- -23 -17 -23 -17 -12 -4
Note1: Cell contents shaded in yellow are defined as ‘not supported’
Required time tVAC above VIH(ac) )(acbelowVIL for valid transition for CA
Slew Rate (V/ns) tVAC at 150mV(ps) 1600Mb/s
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Min Max
>4.0 48 --
4.0 48 --
3.5 46 --
3.0 43 --
2.5 40 --
2.0 35 --
1.5 27 --
<1.5 27 --
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23. Basic Functionality
Mobile LPDDR3 is a high speed SDRAM internally configured as an 8-bank memory device.
LPDDR3 uses double date rate architecture on the command/address (CA) bus to reduce the
number of input pins in the system. The 10-bit CA bus is used to transmit command, address, and
bank information. Each command uses one clock cycle, during which command information is
transferred on both the rising and falling edges of the clock.
LPDDR3 uses double data rate architecture on the DQ pins to achieve high speed operation. The
double data rate architecture is an 8n prefetch architecture with an interface designed to transfer
two data bits per DQ every clock cycle at the I/O pins.
A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide, one-clock
cycle data transfer at the internal SDRAM core and eight corresponding nbit-wide,
one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the device are burst
oriented; accesses start at a selected location and continue for a programmed number of locations
in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or WRITE
command. The address and BA bits registered coincident with the ACTIVATE command are used
to select the row and bank to be accessed. The address bits registered coincident with the READ or
WRITE command are used to select the bank and the starting column location for the burst access.
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Power-Up, Initialization, and Power-Off
LPDDR3 devices must be powered up and initialized in a predefined manner. Power-up and initialization by
means other than those specified will result in undefined operation.
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified otherwise, this procedure is
mandatory and applies to devices.
1) Voltage Ramp
While applying power (after Ta),CKE must be held LOW(≦0.2xVDDCA), and all other inputs must be
between VIL min and VIHmax. The device outputs remain at Hign-Z while CKE is held LOW. Following
the completion of the voltage ramp(Tb), CKE must be maintained LOW. DQ,DM,DQS and DQS voltage
levels must be between VSS and VDDQ during voltage ramp to avoid latch up. CK, CK ,CS , and CA
input levels must be between VSS and VDDCA during voltage ramp to avoid latch up. Voltage ramp
power supply requirements are provided below.
Voltage Ramp Conditions
After… Applicable Conditions
Ta is reached
VDD1 must be greater than VDD2(200 mV)
VDD1 and VDD2 must be greater than VDDCA(200 mV)
VDD1 and VDD2 must be greater than VDDQ(200 mV)
VREF must always be less than all other supply voltages
Notes:
1. Ta is he point when any power supply first reaches 300mV
2. Noted conditions apply between Ta and power-down(controlled or uncontrolled)
3. Tb is the point at which all supply and reference voltages are within their defined operating ranges.
4. Power ramp duration tINIT0(Tb-Ta) must not exceed 20ms.
5. The voltage difference between any of VSS pins must not exceed 100mV.
Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The
clock must be stable at least tINIT2 prior to the first CKE LOW-to-HIGH transition(Tc). CKE, CS and CA
inputs must observe setup and hold requirements (tIS,tIH) with respect to the first rising clock edge(as
well as to subsequent falling and rising edges).
If any MRRs are issued, the clock period must be within the range defined for tCKb,MRW commands
can be issued at nomal clock frequencies as long as all AC timings are met. Some AC parameters (for
example,tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is approximately
configured. While keeping CKE HIGH,NOP commands must be issued for at least tINIT3(Td). The ODT
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input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal shall be statically held at either LOW or HIGH. The ODT input signal remains
static until the powre up initialization sequence is finished, including the expiration of tZQINIT.
2) RESET Command
After tINIT3 is satisfied, the MRV RESET command must be issued (Td). An optional PRECHARGE ALL
command can be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE
asserted and issuing NOP commands.
3) MRRs and Device Auto Initialization (DAI) Polling
After tINIT4 is satisfied(Te), only MRR commands and power-down entry/exit commands are supported.
Aftr Te, CKE can go LOW in alignment with power-down entry and exit specifications. Use the MRR
command to poll the DAI bit and report when device auto initialization is complete; otherwise, the
controller must wait a minimum of tINIT5, or until the DAI bit is set before proceeeding. As the memory
output vuffers are not properly configured by Te, some AC parameters must have relaxedd timings
before the system is appropriately configured. After the DAI bit(MR0,DAI) is set to zero by the memory
device (DAI complete), the device is in the idle state (Tf). DAI status can be determined by issuing the
MRR command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The
controller must wait at least tINIT5 or until the DAI bit is set before proceeding.
4) ZQ Calibration
After tINIT5(Tf), the MRW initializtion calibration (ZQ_CAL) command can be issued to the
memory(MR10). This command is used to calibrate output impedance over process, voltage, and
temperature. In systems where more than one LPDDR3 device exists on the same bus, the controller
must not overlap MRW ZQ_CAL commands. The device is ready for normal operation after tZQint.
5) Normal Operation
After tZQint(Tg), MRW commands must be used to properly configure the memory (for example the
output buffer drive strength, latencies, etc.). Specificlly, MR1,MR2, and MR3 must be set to configure
the memory for the target frequency and memory configuration after the initialization sequence is
complete, the devie is ready for any valid command. After Tg, the clock frequency can be changed using
the procedure described in the LPDDR3 specifiation.
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24. Contact Information
Big Innovation Company Limited (BIG-INNO)
9F., No.32, Jihu Road,
Neihu District, Taipei,
Taiwan 11492
Support +886-2-2268-3466
Fax +886-2-5569-7558
DISCLAIMER OF LIABILITY
Big Innovation Company Limited (BIG-INNO) reserves the right to make changes to specifications and product
descriptions such as but not limited to numbers, parameters and other technical information contained herein without
notice. Please contact BIG-INNO. to obtain the latest specifications. BIG-INNO grants no warranty with respect to this
datasheet, explicit or implied, and is not liable for direct or indirect damages. Some states do not grant the exclusion of
incidental damages and as such this statement may not be valid in such states. The provisions of the datasheet do not
convey to the purchaser of the device any license under any patent right or other intellectual property right of BIG-INNO
Customers must not use BIG-INNO products in applications that the products failure or malfunction may
cause death of life or body injury such as life support system or devices.
BIG-INNO shall not be liable for any loss, injury or damage caused by use of the products in any of the following
applications.
Medical related devices, life support, medical measurement devices, etc.
Control device for train, ship, mass transportation system or automotive vehicles, etc.
Specific applications, military/defense related equipment, aerospace, nuclear facility control system, etc.
Safety system for disaster prevention/crime prevention, etc.
COPYRIGHT NOTICE
Copyright © 2017 by BIG-INNO all rights reserved. Information contained in this document, including but not limited to
any instructions, descriptions and product specifications, is considered proprietary and confidential to BIG-INNO and
shall not be modified, used, copied, reproduced or disclosed in whole or in part, in any form or by any means, electronic
or mechanical, for any purpose, without the written consent of BIG-INNO