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EMI
Chris Herrick
Applications Engineer
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EMI source
EMI sourceEmission
Space & FieldConduction
Coupling process
Capacitive Inductive RadiativeConductive
Low Middle & Hi h
LC Resonance
Frequency
EMS
EMS
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EMI source
EMI source Emission
Coupling process Shields
ShieldsEMI Filters
EMI Filters
Capacitive Inductive RadiativeConductive
Low & Middle Frequency High FrequencyLow, Middle & High
Shields
Shields Shields
Shields Shields
ShieldsEMI Filters
EMI Filters
EMS
Immunity
Immunity
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PCB Noise Sources
Emissions from intentional signals include loop-mode and
common-mode sources.
Unintentional Signals ( more than 90% of EMI ) m ss ons rom un n en ona s gna s nc u e common-mo e,
crosstalk coupling to I/O traces (both PCB and IC level), powerplanes, and above board structures.
*Reference from PCBDesign for Real-World
on ro , ruceArchambeault
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Focus on Clock and High Speed Signals
Stripline not necessarily better than Microstrip Examine Clock Harmonics
Common Mode ConversionSCD11=0.5*(S11-S13+S31-S33)
SCD21=0.5*(S21-S23+S41-S43)
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Beware the low speed nets; use post-layout
Coupling may be direct, through intermediate
Common mode will always exist
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Loop Mode & Common Mode Noise
A PC Board & Cables
Loop mode
A victim device
current
A Driver & Receiver
by AC Analysis of
Differential mode current flows --- LoopCommon mode current flows --- Open
We can see Common mode current ismore serious than Normal mode.
Common modecurrent
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-A Differential mode current flow Loop antenna theory-A Common mode current flow Dipole antenna theory
rAI)(f.E
-
sin106131216
=
rlIfE sin)(104
7
=
r : distance rA : area of the loo
Length :l
II
Illustration of a loop antenna Illustration of a dipole antenna
FCC B level Mag. E limit :40dBuV/m @ 3m.
Mag. E( Dipole antenna) : 8uA
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Impedance Analysis
Ensure a low impedance as seen byactive partsResonance Analysis
ange s ac up, p ane cu ou s andecoupling as necessary
Signal Extraction
Emissions Analysis
Enclosure Simulation
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Decoupling CapacitorDecoupling Capacitor on Package
Chip
Via
On-chip Pwr/Gnd
VRM
Ball Bonding
Power/Ground
Wire Bonding Ball Bonding VRM
PCB P/GNetwork
Package P/GNetwork
Chip Decoupling
Capacitor on Chip
Decoupling Capacitor
on Package
Decoupling Capacitor
on PCB
Bulk Capacitor
Near VRM
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Decoupling Impedance of PDN
Bare PCB
0.01uF
0.1uF
10uFTotal PDN
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Plasma Screen Example
Changed Return PathWidened section of GND plane
GND
GND
New modelOld model
Impedance test port near C3,4,5
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Im edance Plot
Impedance : Old model
Impedance New model
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EMI Test Results : Old model
CISPR spec.
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EMI Test Results : New model
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Impedance Analysis
Ensure power planes do not resonant incritical locations
Resonance AnalysisChange stackup, plane cutouts anddecoupling as necessary
Signal Extraction
Emissions Analysis
Enclosure Simulation
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Even though resonances ALWAYSexist, you dont need to excite them:
Kee them awa from Clock harmonics
Examine Via Transitions
Move discrete parts
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Z11
18
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Impedance Analysis
Resonance Analysis
Signal Extraction
bandwidth
Change routing as necessary
Emissions Analysis
Enclosure Simulation
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Image Plane Violations
Always Consider Return Current
PathCapacitor bridging
the moat to transfer
RF currents between
artitionsRF current return path
Si nal Trace Moat or slot in
ground plane
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EMI Reduction using Ferrites
Insert High Q Ferrite
Insert Low Q Ferrite
Without Ferrite
Internal Clock Line
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EMI Test Results
e ore err e
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Clock Distortion
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Clock Distortion
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Clock Distortion
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Clock Distortion
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Clock Distortion
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Clock Distortion
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Impedance Analysis
Resonance Analysis
Signal Extraction
Ensure EMI is at acceptable levelEmissions Analysis
Enclosure Simulation
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Full Channel Analysis
0 A
00
U1_8VCC_1GND
U1_pair1_neg
U1_pair1_pos
U2_1VCC_1GND
U2_pair1_neg
U2_pair1_pos
VCC_main
100
R545
100
R546
inn
inp
outn
outp
diffout_probe
Vcc
Vss
100
R558
R5590.5
/datarate
C560
0.1
R563
R564
inn
inp
outn
outp
diffout_probe
Vcc
Vss Load
0
V475 V541
1000.1 wave o e
Differential PRBS
0
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Real Drivers as Noise Source
MaxE Radiated from PCB
PCB Data-Line
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Near-Fields
VV
Low |Z| at 50 MHz
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Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis
enclosures
Iterate design as necessary
Enclosure Simulation
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A noise analysis by SIwave
A excitation source
SIwave to HFSSHFSS to HFSS
A ECU analysis by HFSS
A EM analysis by HFSS
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310 MHz
Peak on PCB
A cable
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Prevents Emission and Self Interference
Simulating throughout the design cyclecan help you avoid trouble in the chamber
