EN5339QI 3A PowerSoC Datasheet - Altera · 2020-03-31 · Page 1 EN5339QI 3A PowerSoC Step-Down...

Page 1

EN5339QI 3A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor

DESCRIPTION The EN5339QI is an Intel® Enpirion® Power System on a Chip (PowerSoC) DC-DC converter. It integrates the inductor, MOSFET switches, small-signal circuits and compensation in an advanced 4mm x 6mm x 1.1mm 24-pin QFN package.

The EN5339QI PowerSoC is designed specifically to meet the driving demand for higher power density by providing a fully integrated buck converter. It features high efficiency, excellent line and load regulation and guarantees the full 3A output current over temperature.

The EN5339QI operates at high switching frequency and allows for the use of tiny MLCC capacitors. It also enables a very wide control loop bandwidth providing excellent transient performance and reduced output impedance.

Intel Enpirion integrated inductor solution significantly helps to reduce noise. The complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements.

All Enpirion products are RoHS compliant and lead-free manufacturing environment compatible.

FEATURES • Integrated Inductor • Solution Footprint as Small as 55 mm2 • Low Profile, 1.1mm • High Reliability Solution: 280k Years MTBF • High Efficiency, up to 95% • Low Output Ripple Voltage; <5mVP-P Typical • ±3% Output Variation Over Line, Load, Temp • 2.4 V to 5.5 V Input Voltage Range • 3A Continuous Output Current Capability • Output Enable and Power OK Signal • Under Voltage Lockout, Over Current, Short

Circuit, and Thermal Protection • RoHS Compliant; Halogen Free; 260°C Reflow

APPLICATIONS • Applications with Low Profile Requirement such as

SSD and Embedded Computing • SAN/NAS Accelerator Appliance • Controllers, Raid, Processors, Network Processors,

DSPs’ FPGAs, and ASICs • Noise Sensitive Applications

EN5339QI

VOUT

PVIN

AGND

VIN

POK

TST0TST1TST2

ENABLE

AVIN PGND

CIN22µF

COUT3x 22µF

or2x 47µF

100k

VOUT

PGND

Ra

Rb

VFB

POK

Ca

1µF

Figure 1: Simplified Applications Circuit

Figure 2: Highest Efficiency in Smallest Solution Size

DataSheeT – enpirion® power solutions

0102030405060708090

100

0 0.5 1 1.5 2 2.5 3

EFFI

CIEN

CY (%

)

OUTPUT CURRENT (A)

Efficiency vs. Output Current

VOUT = 2.5V

VOUT = 1.2V

CONDITIONSVIN = 3.3V

Actual Solution Size55mm2

Datasheet | Intel® Enpirion® Power Solutions: EN5339QI

Page 2

ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description

EN5339QI EN5339 -40°C to +125°C 24-pin (4mm x 6mm x 1.1mm) QFN

EVB-EN5339QI EN5339 QFN Evaluation Board

Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html

PIN FUNCTIONS

NC(SW)

NC

(SW)

NC

(SW)

NC

(SW)

NC

(SW)

PGND

PGND

VOUTVO

UT

VOU

T

VOU

T

PGN

D

PGN

D

NC

VFB

AGND

AVIN

POK

ENABLE

PVIN

PVIN

26PGND

25PGND

1

2

3

4

5 6 7 8 9 10 11 12

13

14

15

16

1718192021222324

Keep-Out

Keep-Out

TST2

TST1

TST0

Figure 3: Pin Diagram (Top View)

NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.

NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically connected to the PCB. There should be no traces on PCB top layer under these keep out areas.

NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.


Page 3

PIN DESCRIPTIONS PIN NAME TYPE FUNCTION

1, 21-24 NC(SW) -

NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage.

2-3, 8-9 PGND Power

Input and output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more details.

4-7 VOUT Power Regulated converter output. Connect to the load and place output filter capacitor(s) between these pins and PGND pins 8 and 9. See layout recommendation for details

10 TST2 - Test Pin. For Intel Enpirion internal use only. Connect to AVIN at all times.



13 NC -

NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other pin or to any external signal, voltage, or ground. This pin may be connected internally. Failure to follow this guideline may result in device damage.

14 VFB Analog

This is the external feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is required parallel to the upper feedback resistor (RA). The output voltage regulation is based on the VFB node voltage equal to 0.600V.

15 AGND Power The quiet ground for the control circuits. Connect to the ground plane with a via right next to the pin.

16 AVIN Power Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN) at a quiet point. Decouple with a 1uF capacitor to AGND.

17 POK Digital POK is an open drain output. Refer to Power OK section for details. Leave POK open if unused.

18 ENABLE Analog Output Enable. A logic high level on this pin enables the output and initiates a soft-start. A logic low signal disables the output and discharges the output to GND. This pin must not be left floating.

19-20 PVIN Power Input power supply. Connect to input power supply and place input filter capacitor(s) between these pins and PGND pins 2 to 3.

25,26 PGND Ground Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-sinking purposes. See Layout Recommendation section.


Page 4

ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Absolute Maximum Pin Ratings

PARAMETER SYMBOL MIN MAX UNITS

PVIN, AVIN, VOUT -0.3 6.5 V

ENABLE, POK, TST0, TST1, TST2 -0.3 VIN+0.3 V

VFB -0.3 2.7 V

Absolute Maximum Thermal Ratings

PARAMETER CONDITION MIN MAX UNITS

Maximum Operating Junction Temperature +150 °C

Storage Temperature Range -65 +150 °C

Reflow Peak Body Temperature (10 Sec) MSL3 JEDEC J-STD-020A +260 °C

Absolute Maximum ESD Ratings

PARAMETER CONDITION MIN MAX UNITS

HBM (Human Body Model) ±2000 V

CDM (Charged Device Model) ±500 V

RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS

Input Voltage Range VIN 2.4 5.5 V

Output Voltage Range VOUT 0.6 VIN – VDO (1) V

Output Current Range IOUT 3 A

Operating Ambient Temperature Range TA -40 +85 °C

Operating Junction Temperature TJ -40 +125 °C


Page 5

THERMAL CHARACTERISTICS PARAMETER SYMBOL TYPICAL UNITS

Thermal Shutdown TSD 150 °C

Thermal Shutdown Hysteresis TSDHYS 15 °C

Thermal Resistance: Junction to Ambient (0 LFM) (2) θJA 36 °C/W

Thermal Resistance: Junction to Case (0 LFM) θJC 6 °C/W

ELECTRICAL CHARACTERISTICS NOTE: VIN = PVIN = AVIN = 5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25°C.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Input Voltage VIN 2.4 5.5 V

Feedback Node Initial Accuracy VVFB

TA = 25°C; VIN = 5V

ILOAD = 100 mA 0.588 0.600 0.612 V

Output Variation (3) (Line, Load, Temperature)

VOUT 2.4V ≤ VIN ≤ 5.5V

0 ≤ ILOAD ≤ 3A -3 +3 %

VFB, ENABLE, TST0/1/2 Pin Input Current (4) +/-40 nA

Shutdown Current ENABLE Low 20 µA

Under Voltage Lock-out – VIN Rising VUVLOR Voltage Above Which UVLO

is Not Asserted 2.2 V

Under Voltage Lock-out – tVIN Falling VUVLOF Voltage Below Which UVLO

is Asserted 2.1 V

Soft-start Time Time from Enable High (4) 0.91 1.40 1.89 ms

Dropout Resistance 150 300 mΩ

ENABLE Voltage Threshold

Logic Low 0.0 0.4 V

Logic High 1.4 VIN V

POK Threshold VOUT Rising 92 %

POK Threshold VOUT Falling 90 %

POK Low Voltage ISINK = 1 mA 0.15 0.4 V


Page 6

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

POK Pin VOH Leakage Current POK High 0.5 2 µA

Current Limit Threshold 2.4V ≤ VIN ≤ 5.5V 3.2 5 A

Operating Frequency FOSC 3.2 MHz

Output Ripple Voltage VRIPPLE

COUT = 3 x 22 µF 0805 X5R MLCC, VOUT = 3.3 V, ILOAD = 3A

4.2 mVP-P

COUT = 3 x 22 µF 0805 X5R MLCC, VOUT = 1.8 V, ILOAD = 3A

5.5 mVP-P

(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.

(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards.

(3) The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.

(4) Parameter not production tested but is guaranteed by design.


Page 7

TYPICAL PERFORMANCE CURVES

0102030405060708090

100

0 0.5 1 1.5 2 2.5 3

EFF

ICIE

NC

Y (%

)

OUTPUT CURRENT (A)


VOUT = 2.5VVOUT = 1.8VVOUT = 1.2VVOUT = 1.0V


0102030405060708090

100

0 0.5 1 1.5 2 2.5 3

EFF

ICIE

NC

Y (%

)

OUTPUT CURRENT (A)


VOUT = 3.3VVOUT = 2.5VVOUT = 1.8VVOUT = 1.2VVOUT = 1.0V

CONDITIONSVIN = 5V

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4

OU

TPU

T VO

LTAG

E (V

)

INPUT VOLTAGE(V)

Dropout Voltage

IOUT = 1AIOUT = 2AIOUT = 3A

CONDITIONSVOUT = 3.3V

3.24

3.26

3.28

3.3

3.32

3.34

3.36

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)

Output Voltage vs. Output Current

VOUT = 3.3V

CONDITIONSVIN = 5V

2.44

2.46

2.48

2.5

2.52

2.54

2.56

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 2.5V

CONDITIONSVIN = 5V

1.74

1.76

1.78

1.8

1.82

1.84

1.86

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 1.8V

CONDITIONSVIN = 5V


Page 8

TYPICAL PERFORMANCE CURVES (CONTINUED)

1.14

1.16

1.18

1.2

1.22

1.24

1.26

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 1.2V

CONDITIONSVIN = 5V

2.44

2.46

2.48

2.5

2.52

2.54

2.56

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 2.5V


1.74

1.76

1.78

1.8

1.82

1.84

1.86

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 1.8V


1.14

1.16

1.18

1.2

1.22

1.24

1.26

0 0.5 1 1.5 2 2.5 3

OU

TPU

T V

OLT

AGE

(V)

OUTPUT CURRENT (A)


VOUT = 1.2V


1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

2.5 3.1 3.7 4.3 4.9 5.5

OU

TPU

T V

OLT

AG

E (V

)

INPUT VOLTAGE (V)

Output Voltage vs. Input Voltage

CONDITIONSLoad = 5mA

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

2.5 3.1 3.7 4.3 4.9 5.5

OU

TPU

T V

OLT

AG

E (V

)

INPUT VOLTAGE (V)


CONDITIONSLoad = 500mA


Page 9

TYPICAL PERFORMANCE CURVES (CONTINUED)

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

2.5 3.1 3.7 4.3 4.9 5.5

OU

TPU

T V

OLT

AG

E (V

)

INPUT VOLTAGE (V)


CONDITIONSLoad = 2A

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

2.5 3.1 3.7 4.3 4.9 5.5

OU

TPU

T V

OLT

AG

E (V

)

INPUT VOLTAGE (V)


CONDITIONSLoad = 3A

0.960

0.970

0.980

0.990

1.000

1.010

1.020

1.030

1.040

-40 -15 10 35 60 85

OU

TPU

T V

OLT

AG

E (V

)

AMBIENT TEMPERATURE ( C)

Output Voltage vs. Temperature

LOAD = 3A

LOAD = 100mA

CONDITIONSVIN = 5VVOUT_NOM = 1.0V

1.760

1.770

1.780

1.790

1.800

1.810

1.820

1.830

1.840

-40 -15 10 35 60 85

OU

TPU

T V

OLT

AG

E (V

)

AMBIENT TEMPERATURE ( C)

Output Voltage vs. Temperature

LOAD = 3A

LOAD = 100mA

CONDITIONSVIN = 5VVOUT_NOM = 1.8V

00.5

11.5

22.5

33.5

44.5

5

-40 -15 10 35 60 85GU

AR

AN

TEE

D O

UTP

UT

CU

RR

EN

T (A

)

AMBIENT TEMPERATURE( C)

No Thermal Derating

ConditionsVIN = 5.0VVOUT = 3.3V

CONDITIONSVIN = 5.0VVOUT = 1.0V

00.5

11.5

22.5

33.5

44.5

5

-40 -15 10 35 60 85GU

AR

AN

TEE

D O

UTP

UT

CU

RR

EN

T (A

)

AMBIENT TEMPERATURE( C)

No Thermal Derating

ConditionsVIN = 5.0VVOUT = 3.3V

CONDITIONSVIN = 5.0VVOUT = 3.3V


Page 10

TYPICAL PERFORMANCE CHARACTERISTICS

VOUT(AC Coupled)

Output Ripple at 20MHz

CONDITIONSVIN = 5VVOUT = 1.8VIOUT = 3ACIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)

VOUT(AC Coupled)



VOUT(AC Coupled)


CONDITIONSVIN = 3.3VVOUT = 1.8VIOUT = 3ACIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)

VOUT(AC Coupled)



VOUT

Startup Waveforms at 0A

VIN = 5V, VOUT = 1.8VCIN = 1 X 22µF (0805), COUT = 3 x 22µF (0805), IOUT = 0A

LOAD

ENABLE

POK

VOUT

Startup Waveforms at 3A

VIN = 5V, VOUT = 1.8VCIN = 1 X 22µF (0805), COUT = 3 x 22µF (0805), IOUT = 3A

LOAD

ENABLE

POK


Page 11

TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)

VOUT(AC Coupled)

Load Transient from 0 to 1A

CONDITIONSVIN = 3.3VVOUT = 1.8VCIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)

LOAD

VOUT(AC Coupled)


CONDITIONSVIN = 3.3VVOUT = 1.8VCIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)LOAD

VOUT(AC Coupled)


CONDITIONSVIN = 5VVOUT = 2.5VCIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)

LOAD

VOUT(AC Coupled)


CONDITIONSVIN = 5VVOUT = 2.5VCIN = 1 X 22µF (0805)COUT = 3 x 22µF (0805)

LOAD


Page 12

FUNCTIONAL BLOCK DIAGRAM

DAC

VREF

(+)

(-)Error Amp

VFB

VOUT

Package Boundary

P-Drive

N-Drive

UVLO

Thermal Limit

Current Limit

Soft Start

SawtoothGenerator

(+)

(-)PWM Comp

PVIN

ENABLE

PGND

Logic

CompensationNetwork

NC (SW)

POK

POK

AVIN AGND

BIAS

TST

Figure 4: Functional Block Diagram


Page 13

FUNCTIONAL DESCRIPTION

Synchronous DC-DC Step-Down PowerSoC

The EN5339QI is a highly integrated synchronous buck converter with an internal inductor utilizing advanced CMOS technology to provide high switching frequency, while also maintaining high efficiency. The EN5339QI is a high power density device packaged in a tiny 4x6x1.1mm 24-pin QFN package. Its high switching frequency allows for the use of very small MLCC input and output filter capacitors and results in a total solution size as small as 55mm2.

The EN5339QI buck converter uses Type III voltage mode control to provide pin-point output voltage accuracy, high noise immunity, low output impedance and excellent load transient response. The EN5339QI features include Power OK, under voltage lockout (UVLO), over current protection, short circuit protection, and thermal overload protection.

Stability and Compensation The EN5339QI utilizes an internal compensation network that is designed to provide stable operation over a wide range of operating conditions. The output compensation circuit may be customized to improve transient performance or reduce output voltage ripple with dynamic loads.

Soft-Start The EN5339QI has an internal soft-start circuit that controls the ramp of the output voltage. The control circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETs and the integrated inductor.

The EN5339QI has a constant startup up time which is independent of the VOUT setting. The output rising slew rate is proportional to the output voltage. The startup time is approximately 1.4ms from when the ENABLE is first pulled high until VOUT reaches the regulated voltage level.

Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Maximum allowable output capacitance depends on the device’s minimum current limit as indicated in the Electrical Characteristics Table, the output current at startup, the minimum soft-start time also in the Electrical Characteristics Table and the output voltage. The total maximum capacitance on the output rail is estimated by the equation below:

COUT_MAX = 0.7 * (ILIMIT - IOUT) * tSS / VOUT

COUT_MAX = maximum allowable output capacitance

ILIMIT = minimum current limit = 3.2A

IOUT = output current at startup

tSS = minimum soft-start time = 0.91ms

VOUT = output voltage

NOTE: Device stability still needs to be verified in the application if extra bulk capacitors are added to the output rail.


Page 14

Over Current/Short Circuit Protection When an over current condition occurs, VOUT is pulled low and the device disables switching internally. This condition is maintained for a period of 1.2ms and then a normal soft-start cycle is initiated. If the over current condition still persists, this cycle will repeat.

Under Voltage Lockout An under voltage lockout circuit will hold off switching during initial power up until the input voltage reaches sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable switching. Hysteresis is included to prevent chattering between UVLO high and low states.

Enable

The ENABLE pin provides means to shut down the converter or initiate normal operation. A logic high on the ENABLE pin will initiate the converter to start the soft-start cycle and regulate the output voltage to the desired value. A logic low will allow the device to discharge the output and go into shutdown mode for minimal power consumption. When the output is discharged, an auxiliary NFET turns on and limits the discharge current to 300 mA or below.

The ENABLE pin should not be left floating as it could be in an unknown and random state. It is recommended to enable the device after both PVIN and AVIN is in regulation. At extremely cold conditions below -30°C, the controller may not be properly powered if ENABLE is tied directly to AVIN during startup. It is recommended to use an external RC circuit to delay the ENABLE voltage rise so that the internal controller has time to startup into regulation (see circuit below).

The RC circuit may be adjusted so that AVIN and PVIN are above UVLO before ENABLE is high. The startup time will be delayed by the extra time it takes for the capacitor voltage to reach the ENABLE threshold.

Figure 5: ENABLE Delay Circuit

AVIN

ENABLE

1k

1µF


Page 15

Thermal Shutdown When excessive power is dissipated in the device, its junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature of 150°C, the thermal shutdown circuit turns off the converter, allowing the device to cool. When the junction temperature drops 15°C, the device will be re-enabled and go through a normal startup process.

Power OK

The Power OK (POK) feature is an open drain output signal used to indicate if the output voltage is within 92% of the set value. Within this range, the POK output is allowed to be pulled high. Outside this range, the POK output is maintained low. During transitions such as power up and power down, the POK output will not change state until the transition is complete for enhanced noise immunity.

The POK has 1mA sink capability. When POK is pulled high, the worst case pin leakage current is as low as 500nA over temperature. This allows a large pull up resistor such as 100kΩ to be used for minimal current consumption in shutdown mode.

The POK output can also be conveniently used as an enable input of the next stage for power sequencing of multiple converters.

Power-Up/Power-Down During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, and ENABLE) together during power up or power down meets these requirements.

Pre-Bias Start-up

The EN5339QI supports startup into a pre-biased output of up to 1.5V. The output of the EN5339QI can be pre-biased with a voltage up to 1.5V when it is first enabled.


Page 16

APPLICATION INFORMATION

Output Voltage Setting

The EN5339QI uses a simple and flexible resistor divider network to program the output voltage. A feed-forward capacitor (Ca) is used to improve transient response. Table 3 shows the recommended component values for the feedback network as a function of VOUT. It is recommended to use 1% or better feedback resistors to ensure output voltage accuracy. The Ra resistor value is fixed at 348k as shown in Table 3. Based on that value, the bottom resistor Rb can be calculated below as:

V0.6VV0.6RaRb

OUT−×

=

The VOUT is the nominal output voltage. The Rb and Ra resistors have the same units based on the above equation.

EN5339QI

VOUT

PVIN

AGND

VIN

POK

TST0TST1TST2

ENABLE

AVIN PGND

CIN22µF

COUT3x 22µF

or2x 47µF

100k

VOUT

PGND

Ra

Rb

VFB

POK

Ca

1µF

Figure 6: Typical Application Circuit

NOTE: Enable can be separated from PVIN if the application requires it.

AVIN Filter Capacitor

A 1.0 µF, 10V, 0402 MLCC capacitor should be placed between AVIN and AGND as close to the pins as possible. This will provide high frequency bypass to ensure clean chip supply for optimal performance.

Input Filter Capacitor Selection

A single 22µF, 0805 MLCC capacitor is needed on PVIN for all applications. Connect the input capacitor between PVIN and PGND as close to the pins as possible. Placement of the input capacitor is critical to ensure low conducted and radiated EMI.

Low ESR MLCC capacitors with X5R or X7R or equivalent dielectric should be used for the input capacitors. Y5V or equivalent dielectrics lose too much capacitance with frequency, DC bias, and temperature. Therefore, they are not suitable for switch-mode DC-DC converter filtering, and must be avoided.

Table 1: Recommened Input Capacitos

Description MFG P/N

22µF, 10V,

X5R, 0805

Taiyo Yuden LMK212BBJ226MG-T

Murata GRM21BR61A226ME51


Page 17

Output Filter Capacitor Selection

The EN5339QI output capacitor selection may be determined based on two configurations. Table 3 provides the allowed output capacitor configurations based on operating conditions. For lower output ripple, choose 3 x 22µF for the output capacitors. For smaller solution size, use two 47µF output capacitors. Table 2 shows the recommended type and brand of output capacitors to use.

In some rare applications modifications to the compensation may be required. The EN5339QI provides the capability to modify the control loop response to allow for customization for specific applications.

Table 2: Recommened Output Capacitos

Description MFG P/N

47µF, 6.3V,

X5R, 0805

Taiyo Yuden JMK212BBJ476MG-T

Murata GRM21BR60J476ME15

22µF, 10V,

X5R, 0805

Taiyo Yuden LMK212BBJ226MG-T

Murata GRM21BR61A226ME51

Table 3. Required Critical Components

VIN IOUT VOUT COUT Ra Ca

2.5V - 5.5V 3A

0.9V

3x 22µF (0805)

Or

2x 47µF (0805)

348kΩ

10pF

1.0V

1.2V

1.5V

1.8V

2.5V

8.2pF 2.85V

3.3V

Note: Follow Layout Recommendations


Page 18

THERMAL CONSIDERATIONS Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated needs to be accounted for. Intel’s Enpirion PowerSoCTM helps alleviate some of those concerns. Intel’s Enpirion EN5339QI DC-DC converter is packaged in a 4x6x1.1mm 24-pin QFN package. The QFN package is constructed with exposed thermal pads on the bottom of the package. The exposed thermal pad should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150°C. The EN5339QI is guaranteed to support the full 3A output current up to 85°C ambient temperature. The following example and calculations illustrate the thermal performance of the EN5339QI. Example:

VIN = 5V

VOUT = 3.3V

IOUT = 3A

First calculate the output power.

POUT = 3.3V x 3A = 9.9W

Next, determine the input power based on the efficiency (η) shown in Figure 7.

Figure 7: Efficiency vs. Output Current

0

10

20

30

40

50

60

70

80

90

100

0 0.5 1 1.5 2 2.5 3

EFF

ICIE

NC

Y (%

)

OUTPUT CURRENT (A)

VOUT = 3.3V CONDITIONSVIN = 5VCONDITIONSVIN = 5VCONDITIONSVIN = 5VCONDITIONSVIN = 5V

~90%


Page 19

For VIN = 5V, VOUT = 3.3V at 3A, η ≈ 90%

η = POUT / PIN = 90% = 0.90

PIN = POUT / η

PIN ≈ 9.9W / 0.90 ≈ 11W

The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power.

PD = PIN – POUT

≈ 11W – 9.9W ≈ 1.1W

With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN5339QI has a θJA value of 36°C/W without airflow.

Determine the change in temperature (ΔT) based on PD and θJA.

ΔT = PD x θJA

ΔT ≈ 1.1W x 36°C/W = 39.6°C ≈ 40°C

The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in temperature. We assume the initial ambient temperature to be 25°C.

TJ = TA + ΔT

TJ ≈ 25°C + 40°C ≈ 65°C

The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.

TAMAX = TJMAX – PD x θJA

≈ 125°C – 40°C ≈ 85°C

The ambient temperature can actually rise by another 60°C, bringing it to 85°C before the device will reach TJMAX. This indicates that the EN5339QI can support the full 3A output current range up to approximately 85°C ambient temperature given the input and output voltage conditions. Note that the efficiency will be slightly lower at higher temperatures and these calculations are estimates.


Page 20

ENGINEERING SCHEMATIC

Figure 8. Engineering Schematic with Critical Components


Page 21

LAYOUT RECOMMENDATIONS This layout only shows the critical components and top layer traces for minimum footprint with ENABLE as a separate signal. Alternate ENABLE configurations & the POK pin need to be connected and routed according to customer application. Please see the Gerber files on EN5339QI’s product page at www.altera.com/powersoc for details on all layers.

Figure 9: Optimized Layout Recommendations

Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN5339QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN5339QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors.

Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors.

Recommendation 3: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter.

Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops.

Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 9 this connection is made at the input capacitor. Connect a 1µF capacitor from the AVIN pin to AGND.

http://www.altera.com/powersoc


Page 22

Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 9. See the section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers.

Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node.

Recommendation 8: Keep RA, CA, RB close to the VFB pin (See Figures 6). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane.


Page 23

DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES

Exposed Metal on Bottom of Package

QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the package that provide improved thermal dissipation, lower package thermal resistance, smaller package footprint and thickness, larger lead size and pitch, and excellent lead co-planarity. As the EN5339QI package is a fully integrated module consisting of multiple internal devices, the lead-frame provides circuit interconnection and mechanical support of these devices resulting in multiple exposed metal pads on the package bottom.

Only the two large thermal pads and the perimeter leads are to be mechanically/electrically connected to the PCB through a SMT soldering process. All other exposed metal is to remain free of any interconnection to the PCB. Figure 10 shows the recommended PCB metal layout for the EN5339QI package. A GND pad with a solder mask "bridge" to separate into two pads and 24 signal pads are to be used to match the metal on the package. The PCB should be clear of any other metal, including traces, vias, etc., under the package to avoid electrical shorting.

The Solder Stencil Aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Please consult EN5339QI QFN Package Soldering Guidelines for more details and recommendations.

Figure 10: Lead-Frame exposed metal (Top View)

Note: Grey area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.


Page 24

RECOMMENDED PCB FOOTPRINT

Figure 11: Landing Pattern with Solder Stencil (Top View)

The solder stencil aperture for the thermal pads (shown in blue) is based on Intel Enpirion’s manufacturing recommendations


Page 25

PACKAGE DIMENSIONS

Figure 12: EN5339QI Package Dimensions (Bottom View)

Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html

https://www.altera.com/support/quality-and-reliability/packing.html


WHERE TO GET MORE INFORMATION For more information about Intel® and Enpirion® PowerSoCs, visit:

www.altera.com/enpirion

© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others.

Page 26

REVISION HISTORY Rev Date Change(s)

F August, 2018 • Changed datasheet into Intel format.

I April, 2019 • Formatting changes

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