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Enabling the ARM Learning in INDIA LPC2148 Programming Using BLUEBOARD
Enabling the ARM Learning in INDIA
LPC2148 Programming
Using BLUEBOARD
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AGENDA LPC214x Block Diagram Pin Diagram BlueBoard Schematic PIN Select Block General Purpose Input/Output First Program
Bus Structure
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In LPC2148 three types of busses are used to connect the core with other peripherals on chip.
1. Local Bus to connect the onchip memory controllers and fast GPIO’s2. AMBA Advance High Performance Bus (AHB) for interrupt controller3. VLSI Peripheral Bus (VPB) for other onchip peripherals.
AHB acts as a bridge for VPB.VPB is mainly meant for connect slower peripherals then that of processor.VPB can dive the peripherals at ¼ CPU clock frequency.
Bus Structure
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Memory MAP
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To access any peripheral we need its address. The entire address space can be divided in to several sections.
Memory MAP
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Memory Access Module
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The MAM block in the LPC2148 maximizes the performance of the ARMprocessor when it is running code in Flash memory,
Two general methods for achieving code execution performance.Using RAM for code execution.Using Cache memory.
Memory Access Module
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The MAM block in the LPC2148
Bootloader
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A small piece of software executed after every reset. This software is used toload the new user program in to the flash memory using any communication channel like UART, USB, Ethernet or CAN.
For LPC2000 Series the Bootlader can be activated by maintaining low level on P0.14 while reset.
Bootloader
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ISP
Philips microcontroller have a great feature called ISP (In System
Programming).
It enables the user to flash the microcontroller with an ease. In LPC2148 the ISP
mode can be activated by maintaining low level on P0.14 while reset.
Boot Process
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ISP Commands
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IAP
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In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code.The bootloader code provides API to access flash memory from the user program. The API are called using their codes.
IAP Command Command Code in DecimalsPrepare sector(s) for write operation 50
Copy RAM to Flash 51
Erase sector(s) 52
Blank check sector(s) 53
Read Part ID 54
Read Boot code version 55
Compare 56
Reinvoke ISP 57
Phased Lock Loop
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PLL is a closed loop control system to generate high frequency by multiplyingwith given factor to the input frequency.
Div
FoutFin
Basic PLL Block Diagram
Mul
In LPC2148 microcontrollers there are 2 PLLs which provides programmable frequencies to the CPU and USB system.The input clock frequency to PLL0 and PLL1 is in the range of 10MHz to 25 MHz only. It is multiplied up the range of 10MHz to 60MHz for CCLK and 48MHz for the USB cock using Current Controlled Oscillator (CCO).
PLL Programming
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PLL RegistersGen. Name Description PLL0 PLL1
PLLCON PLL Control Register. Holding register forupdating PLL control bits
0xE01F C080PLL0CON
0xE01F C0A0PLL1CON
PLLCFG PLL Configuration Register. Holding register forupdating PLL configuration values
0 0xE01F C084PLL0CFG
0xE01F C0A4PLL1CFG
PLLSTAT PLL Status Register. Read-back register for PLLcontrol and configuration information
0xE01F C088PLL0STAT
0xE01F C0A8PLL1STAT
PLLFEED PLL Feed Register. This register enablesloading of the PLL control and configurationinformation from the PLLCON and PLLCFGregisters into the shadow registers that actuallyaffect PLL operation.
0xE01F C08CPLL0FEED
0xE01F C0ACPLL1FEED
Detail Register Bits LPC214X User Manual Page 27
PLL Programming
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Programming Steps:1. Select the desired operating frequency for your system ( Processor operating frequency) CCLK.2. Check the oscillator connected to the controller on board. (FOSC) 3. Calculate the value of PLL multiplier “M”. CCLK = M × FOSC4. Find the value of PLL Divider “P” in such a way that is in the range of 156 MHz
to 320 MHz. 156 < FCCO < 320 = CCLK x 2 x P5. Write the values PLLCON and PLLCFG.6. Write the PLLFEED Values 0xAA and 0x55.7. Wait for PLL to lock.8. Connect the PLL.
VBP Divider
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VLSI Bus connected to various peripherals can be operated at different speeds using the VBP Divider.
The VPB Divider serves two purposes: 1. Provides peripherals with desired PCLK via VPB bus, the VPB bus may be slowed down to one half or one fourth of the processor clock rate 2. VPB Divider allow power savings when an application does not require any peripherals to run at the full processor rate.
VBP Divider
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VPBDIV registers least 2 significant bits can be changed for desired PCLK Peripherals on LPC2000 series can run at the full 60 MHz clock.
POWER CONTROL
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LPC214x support two reduced power modes Idle mode and Power-down mode.
Idle Mode: The CPU stops execution is suspended until a Reset or Interrupt from peripheral occurs. Peripheral runs in idle mode and may generate interrupts to resume the CPU execution.
Power-Down Mode: The oscillator is shutdown and the chip receives no internal clocks. All the information of current execution state is preserved in this mode. A Reset signal or External Interrupt can terminate the power-down mode.
PCON Register:Bit 0 : When set to 1, causes the processor clock to be stopped.Bit 1 : When set to 1, causes the on-chip clock to be stopped.
In LPC214x the power down mode have dependency on USB Block
Peripheral Power Control
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LPC2000 peripherals can be turned of individually using the PCONP Register bits setting,
to save the power. Few peripherals like GPIO, Watchdog timer, Pin connect block and System Control block
cannot be turned off. After reset the PCONP contains the value to enable all peripherals, so no need to
configure PCONP bits in-order to use any peripheral.
Page 37 LPC2148 User Manual
INTERRUPT SYSTEM
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Interrupt System
• ARM PrimeCell™ Vectored Interrupt Controller
• 32 interrupt request inputs
• 16 vectored IRQ interrupts
• 16 priority levels dynamically assigned to interrupt requests
• Software interrupt generation
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