End-to-End_Design_and_Simulation_of_Handset_Modules_02-27-2012.pdf

8/13/2019 End-to-End_Design_and_Simulation_of_Handset_Modules_02-27-2012.pdf

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Skyworks Solutions, Inc. Proprietary Information 1

End-to-End Design and Simulation of

Handset ModulesPete Zampardi and Hongxiao Shao

Skyworks Solutions, Inc.


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Research vs. Production Design Flows

Research Design Flow

Work?

Simulate

Fabricate

Test

Apply forFollow-on

Ask forMore

Funding

Yes

No

Work?

Simulate

Fabricate

Test

Re-Tune

Repeat50 Million

Times

No

Yes

Production Design Flow


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Simulation Philosophy

What Does a Handset Amplifier Design Look L ike?

Example Design Flows GSM (Controller + PA)

WCDMA (Bias/Logic Integrated with PA) Design Automation and Modeling Requirements/Strategy to Support This

Flow

Modeling Approach Device Models

Inductor Tool

Thermal Considerations

Circuit Level Modeling

Laminates Man Does Not Live by GaAs Die Alone

Conclusions

Outline


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Modeling/Design Philosophy

Goal of Modeling (for PA) is to Get Designer on the Green Compact Models are the Drivers, Irons, and Wedges

Correlation of Lab and Simulation Benches is like reading the green

Behavioral Models could be the Putter

Modeling VARIATION of the Process is More Important than Modeling a

Hero Device Variation is Important for Yield and System Performance

Use Best Available Software for Each Piece,

Glue Together with Custom Solut ions

What are the Expectations?

Goal of Simulation is to Get Close as

Fast as Possible, Predict Trends

The time needed for measuring a PAM with Pout sweepingfrom -5 to + 28 dBm (1dBm/step) and three frequencies, plus changingoneSMT component was about 1500 sec.(V. Ho)


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What Does a Handset Amplif ier Design Look Like?

HINT: NOT MADE OF DISCRETES

Control/Logic IC

Substrate and

Assembly

Power Amp IC

ComponentsSMT, Filter, etc

Power Amp Product

WCDMA UsuallyCombine These

On-chip

GlasbrenerBreaking EDA BarriersRFIC Panel 2002

Simulation: DC, Trans., S-par

and HBLayout: GDSII

EM SimulationLayout: Gerber

Simulation: DC, Trans., S-par

and HBLayout: GDSII

Simulation: DC, Trans. S-parand HB


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Simulation and Design Issues

Components (Simple Small Signal Models Okay)

Fit for Design Flow:

Tunable for Optimization

Sensitivity Analysis for Tolerance Selection

Fixed Predefined Sizes

NO Double-Counting

Substrate (Feature Size Determined by Customer/Product Needs) EM Simulate as Soon andMuch as Possible

Variation is Important (Weed Out Bad Layouts) Design Issue

Need to Run DRC and LVS on Substrates

ICs (Contro ller and PA) DC, Time Domain, Small Signal S-parameter and Possibly HB/Envsims

Design Library Supported by Foundry/Fab

EM Sim. for on Chip Passives (Inductors, MIM Caps, Bad wiring)

Design Issue Need to Run DRC and LVS on ICs

Challenges for Controller

Predictable Interface with PA for Co-Simulation/Co-Development

Challenges for PA

Models Need to Work in DC, Small Signal, and Large Signal with Correct DC Predictions Under Large Signal

Need to Simulate with Everything Else Substrate, Logic/Control and Components

Components

Substrate

Control/Logic ICPower Amp IC


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8/32Skyworks Solutions, Inc. Proprietary Information 8

IC Centric Design Flow Real Example

ChipsControl and Bias Chip

GaAs HBT PA ChipPower DetectorSwitch ChipDiplexer

PackagesEmbedded devicesDiscreteMCM

Multiple Process Technologies (Multi-Chip)ICs Active/Passive Device Models, Interconnect/Inductor ModelingPackage Bond wire/Bump, SMT, Embedded Devices, Package Passive Modeling

pHEMT Switch ChipGaAs IC + Wire bond + Package (EM/Meas.)

CMOS ChipCMOS IC + Wire bond + Discrete Components

GaAs HBT Power Amp ChipGaAs IC + CMOS IC (at circuit or behavior level) + Wire bond + SMT + Package (EM/Meas.)

DesignElectrical DesignPhysical Constraints (IC/Package)Thermal Management

Part Tuning



GaAs HBT PA / PHEMT Switch Design Flow

Design, Analysis,

and Simulation

MMIC Schematic

Preliminary

MCM Schematic

Test Bench

Schematic

EM SimulationHBT Models

Package Models

SMT, BW,

Laminate

MMIC Netlist PA MMIC Layout

HBT Layout

Library, DRC

Rule Deck

Si Models

Models forsupplies, stimuli,

measurement, etc.

HBT Mask

Generation

Die Symbol

for MCM

Layout

Die Symbol

for MCM

Schematic

LVS

HBT PA Design Flow

Hierarchical Schematic

.die file

Simulation

Bench


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MCM Design Flow

Design, Analysis,

and Simulation

MMIC Schematic

Preliminary

MCM Schematic

Test Bench

Schematic

EM Simulation

MCM

MMIC NetlistMCM Layout

MCM Package

Library

Die Symbol

for MCM

Layout

Die Symbol

for MCMSchematic

Wirebond Diagram

MCM Design Flow


From HBT / pHEMT Flow

.die file

MCM

Package Level

Schematic

Assembly Diagram

PCB Fab Drawing

Prototype BOMText File Manipulation

and UpdatesBOM

Generation

(1st time only)

Tuning, Alternate

Component Eval,

DC/AC Simulations

to Verify Functionali ty

RFDE Dynamic Link

Required for Si

MCM Schematic pdf

DMS



PA Module Design Optimization and

Verif ication RFDE ADS Dynamic Link

ADS

Design, Analysis, and Simulation

ADS MMIC

Die Schematic

Package Models

SMT, BW,

Laminate

HBT Models

Models for

Supplies, Stimuli,

Measurement, etc.

Si PA Controller / HBT PA / MCM Co-Simulation

ADS


ADS MCM

Level Schematic

ADS Top

Level Schematic

Cadence


Si Models

Cadence Si Die

Schematic

ADSDYNAMICLINK



WCDMA Considerations

Control Circuitry is ON-CHIP! What the PA must do now is complicated

Power Level Switching/Control

No Vref Bias Circuits

Barrie Gilbert RF design is 30% RF,70% Bias Circuit Analog-mixed Signal Modeling Methodology Must be Applied

Fully Scalable Device Models (for Optimization)

Statistical Simulations (Physically Based is Better)

For High Volume Commercial Products, Yield Matters! Statistics for Laminate Variations are Important (Not Just the Die)

Power

Transistors

Power

Transistors

PAs are More than Just Two Transistors

Most of the Chip is

NOT Power Transistors



(W)CDMA PA/FEM Product

Development Flow

Dont Know Layout or off-chip stuff

Understand Critical BlocksWith Estimated Tolerance to Parasitics

Provide Tools

For 1stOrderBest Guess of

Things Youll

Layout

(Inductors/Caps)

Know Variations

Simulate Stuff

You Didnt Know

Earlier (Passives)For Production,

Statistical

Simulation

Over Die Process

And

Package Variation

Best Guess

At Bond Wires

Scalable

DeviceModels

IC Design LayoutCo-

Simulation

IC Design

Feasibility

Study

Initial Simulation

Schematic

Connectivity/

DC/Functionality

Layout

Module Design(Layout)

Extend

Simulation

MCM_RF

IC Layout Parasitic

EM Simulation

Co-Simulation

IC+Module

Design for

Manufacturing(Partial)

BuildingBlock



Compact Models

Compact Models Provided (at Schematic Phase) for: Transistors HBTs (for Logic and for Power Chain)

MESFETs (for Logic and Switching Functions)

Diodes (Used in Logic Circuits and ESD)

Resistors (Precision Thin-film and Semiconductor) Inductors (Inductor Tool Provided to Help Selection, Assume EM Sim Later)

Simulation Based on Method of Line, Momentum and S-parameters Pulled in

Capacitors (Tool Provided for Selection, Assume EM Sim Later)

Compact Models are Required for Bias CircuitDesign and for Device Selection for Power

Devices

Provides an Easy Path for Statistical Simulation



Tech Devices Supported

Wafers

Meas.

Sites per

Wafer Temperature # of Epi Statistics

GEN2 3 HBTs, 3 Diodes, Ls 1 1 HBT Only 1 No

GEN3 4 HBTs, 2 Diodes, Ls 1 1 HBT Only 1 No

GEN4 4 HBTs, 2 diodes, Ls,

Cs

1 1 HBT/Diode 2 No

Current Scalable HBTs

(Fixed-cell Rings,

Many Geometries of

Straight Finger)

Scalable Diodes

Rs, Ls, Cs

FETs for BiFET

Multiple 5 All 5 Yes

Evolution of Models at Skyworks

RingHorseshoe

CEBEC (QSF)CEBEC (QSB_ALT)

QSB

QSMCEB, BEC, 1, 2, 4 finger

IncreasingNumber ofDevices and

Materials toSatisfy MoreDiverseDesignDemands

Curve Fit

Physics Based

Zampardi, CMRF 2007

Physics-Based Scalable Approach Makes This a Tractable Problem


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Thermal Approaches/Considerations

Maximum Junction Temperature Simulations (Reliabili ty)

Thermal only Simulation (Okay if Properly Ballasted) Usually Compared/Validated Against IR Scans

Thermal Coupling/Average Transistor Temperature (Electrical) Bias Circuit

Array Design

Array to Array Interactions

Complications Inter-transistor interaction through interconnect/semiconductor/etc.

Thermal is Not Just Because of the Die: Laminate, Epoxy, Overmold, etc

AbsoluteTemperature

Coupling

What Matters Thermally Depends on

What You are Designing



The Simulation Problem

Circuit Simulation

Power Supply VoltagesPower Dissipation Per Transistor

Die Layout

Placement of Transistors(Heat Sources)

Coupling Between Heat Sources(Metal and Semiconductor)

Package Layout

Epoxy (Shape and Thickness)Placement of PTH

Coupling Between Heat Sources(Metal and Laminate)

Thermal Simulations Require Inputs FromAll of These

Electro-thermal Couples the TemperatureInformation Back into the Simulation

Compared to Digital/Analog Circuits, for aPA this Will Need to be Done Several Timesat Any Given Power Since ElectricalParameters and Thermal Conductivitiesare Functions of Temperature

Much of the Packaging Information(Epoxy Thickness, Shape,

Die Placement, Die Thickness) is DifficultTo collect Statistical Information on

PA Module/Phoneboard Cross-Section

PAM

PHONEBOARD



Gaps in Circuit Level Thermal Simulation?

User Friendly Interface/translator from Simulation to Thermal andBack Scripts to Map Simulator Information (power) and Layout Information

(Position) Needed

Scripts to Back-Annotate Temperature Information (From T simulator) into

Circuit Simulators Determination/Characterization of How Much of the Output Array Needs to be

Lumped Together

First Order Estimate (During Simulation Pass) of Coupl ing and Array

Average Temperature (Analytical Equations Embedded in Simulator)

Needs Some Background Work to Make it Generally Applicable Rather Thanfor Each Array/Device/Technology


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-15 -10 -5 0 5 10 15-20 20

0

10

20

30

-10

40

RFpow er

Gain

gain

Pout

poutgainRFpower=Gain=17.317

-18.000

poutRFpower=Pout=31.425

18.000

-15 -10 -5 0 5 10 15-20 20

20

40

0

60

0.2

0.3

0.4

0.5

0.60.7

0.8

0.9

0.1

1.0

RFpow er

_

PAE

re

al(Ic.i[::,0])

Icc

PAERFpower=PAE_C=58.930

18.000

IccRFpower=real(Ic.i[::,0])=0.638

18.000

RFpow er

-18.000

gain

17.317

RFpow er

18.000

pout

31.425

PAE

58.930

Icc

0.638

Temperature Simulations on Array

Simulation No. Descript ion Gain Pout PAE

1 No T Rise 17.317 31.425 58.93

2 T Rise = 10 17.938 31.48 58.893

3 Avg T Rise = 2.1 17.456 31.439 58.926

4 Avg T Rise = 4.54 17.61 31.455 58.917

5 Avg T Rise = 7.27 17.755 31.473 58.96 Avg T Rise = 20.9 18.324 31.565 58.745

7 Hotspot Avg T=6.8 17.607 31.479 58.856

22 Transistor ArrayOptimal Load for AllQs at same tempBallast and Pre-matched

Average Temperature is What Matters

For Electrical Simulation

CMRF 2007


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Array Parasitic Approaches

(Teaching Designers to Fish)

Simple Multiplicity FactorPro: Fast/Simple

Con: Phase Error >8GHz

Lumped ElementPro: Fast

Con: Layout Specific, Hard to Scale

EM SimulationReduced Number of HBTs or All HBTsPro: Easy to Do, No Modeler Required

Con: Simulation Speed Bogs Down with Increased Transistor Count

Transmission Line:Pro: Moderate Speed, Scalable, Easy

Con: Accurate Up to 12GHz

L d P ll P S ith Diff t EM


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Load-Pull Power Sweep with Different EM

Approaches

Gain Comparison

10

12

14

16

18

20

22

-15 -10 -5 0 5 10 15

Pin (dBm)

Gain(dB)

Gain, meas

Gain, EM-1HBT

Gain, EM-2HBT

Gain, EM-3HBT

Gain,EM--12HBT

Gain, Simple_M

Gain, TLM

Gain, Lumped

Pout Comparison

0

5

10

15

20

25

30

-15 -10 -5 0 5 10 15

Pin (dBm)

Pout(dBm)

Pout, meas

Pout, EM-1HBT

Pout, EM-2HBT

Pout, EM-3HBT

Pout,EM-12HBT

Pout, Simple_M

Pout, TLM

Pout, Lumped

Ic Comparison

0

20

40

60

80

100

120

140

160

180

200

-15 -10 -5 0 5 10 15

Pin (dBm)

Ic(mA)

Ic(mA), meas

Ic(mA), EM-1HBT

Ic(mA), EM-2HBT

Ic(mA), EM-3HBT

Ic(mA),EM-12HBT

Ic(mA),simple_M

Ic(mA), TLM

Ic(mA), Lumped

On-wafer LP measurement at freq=1.9GHz,Vc=3.4V, Ic=14.6mA

No Huge Differences Based on

Approach!

EM Slight ly Better

Simple Approach Off at High Power


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25/32


Statist ics Understand Expected Variation

Compared with measurement, PA circuit simulation

shows good tracking of DOE variations.

Statistical Inputs:

PCM Parameters fromMeasured

DOE Wafers

Power Sweep Performed


26/32


Statistics: Identify Issues and Improve Design!

-20 - 10 0 10 20 30 40 50 60 70 80-30 85

25

26

27

28

29

30

31

32

24

33

Temperature (C)

dB(S21)

m1

db(S21) vs temp

m1indep(m1)=plot_vs(dB(S(2,1)), SP.temp)=29.12freq=836.500 0MHz,doeIter=0

25.000

-20 - 10 0 10 20 30 40 50 60 70 80-30 85

0.015

0.020

0.025

0.030

0.010

0.035

Temperature (C)

Ic

q1(A)

-20 -10 0 10 20 30 40 50 60 70 80-30 85

0.04

0.05

0.06

0.07

0.08

0.09

0.03

0.10

Temperature (C)

Icq2(A)

Performance Ranges (at 25C):

dB(S21)(25.64 to 31.54)=5.9

Icq1(13 to 28)=15mA (79%)

Icq2(44 to 90)=46mA (72%)

Performance Ranges (at 25C):

dB(S21)(25.88 to 29.42)=3.5

Icq1(19 to 30)=11mA (46%)

Icq2(35 to 53)=18mA (41%)

-20 -10 0 10 20 30 40 50 60 70 80-30 85

25

26

27

28

29

30

31

32

24

33

Temperature (C)

dB(S21)

m1

db(S21) vs temp

m1indep(m1)=plot_vs(dB(S(2,1)),S P.temp)=27.892freq=836.5000 MHz,doeIter=969

25.000

-2

0

-1

0

0 10

20

30

40

50

60

70

80

-30

85

0.015

0.020

0.025

0.030

0.010

0.035

Temperature (C)

Icq1

(A)

-2

0

-1

0

0 10

20

30

40

50

60

70

80

-30

85

0.04

0.05

0.06

0.07

0.08

0.09

0.03

0.10

Temperature (C)

Icq2(A)

dB(S21)

Icq1

Icq2

Variation Significantly

Reduced!

BEFORE AFTER


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Laminate DOE Simulation

Batch Based Momentum Simulations on DOE states to

capture the laminate process variations : Layer over Layer Misalignment Geometry Size Variations

Dielectric and Layer Thickness Variations

Can Also Be Applied at Die Level

Af ter Completion o f the Batch Based simulation, aSymbol is Generated to Enable the Passive Block, withDOE Analysis Results , to Simulator wi th Other Blocksat the Circuit Level

Pareto charts in ADS Data Display is created once thecircuit level DOE analysis is complete.

Portion of OutputMatch Symbol

in ADS schematic

7 laminate re-related variablesare defined forDOE analysis

Layer over layer offset in X-axisL1 trace width

Assume SMT

cap variation asfollows:C = +/- 0.1 pFL = +/- 0.05 nH,R = +/- 0.1Ohm


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Issues for Behavioral Modeling

We Use Multiple Materials to Address Diverse Product Needs = NmaterialAllow Different Unit Cells for Application = NcellsDifferent Ballasting/Feedback For Different Designs = NballastDifferent Array Layouts/Size Requirements for Applications = NarrayProcess Variation (Say a Few Parameters Will Multiply this by 2Nvariation)

Using Behavioral Models For Simulating

Integrated PA Designs Creates an Intractable Problem!

arrayballastcellsmaterialModels NNNNN =

For FETs, This is an Easier Problem Single Gate Length, Gate Width Scaling (by Adding Cells), No

Ballasting. Process Variation is a Bigger Headache!

Wh D B h i l


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Where Does Behavioral

Modeling Fit In?

Designs Using Discrete Transistor Blocks

Not as Prevalent in Handset Designs Anymore but Used to be Common 10 year ago

Simple Behavioral Models of PA for Bias Design, and of Bias for PA Design (Usually

Implemented in VerilogA)

Package Centric Product Design (Re-use of Controller and/or PA Engines)

System Level Simulations (Still Issues with Statistics, but More Manageable)If It Can Be Used to Improve Speed of Characterization

When the Technology is Not Well Understood

Could Be Used as Putter Once Compact Models get You Close

Things That Still Need to Be Ironed OutIncorporation of Statistics

Memory Effects (especially thermal)

Validation that Insides of Black-Box are Independent of What Happens Outside


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Conclusions

Compact Models Provide a Greatest Leverage in SimulatingHandset PAs, Especially Statistics

The Real Issues Facing PA Designers are Often Misunderstood

Layout ParasiticsThermal Impact on Electrical Performance

Stuff Besides Die is also Critical

Behavioral Models are Useful at System/FEM Design Level and for

Technologies that are not Well Understood.

Statistics are Critical, Even for Package and Embedded Passives


31/32


Acknowledgments

Mats FredrikssonMike GlasbrenerKai KwokYingying Yang

Juntao HuShing Li


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References

M. Glasbrener, Breaking EDA Barriers 2002 IEEE MTT Panel DiscussionR. Jos, Future developments and technology options in Cellular Phone PowerAmplifiers: from power amplifier to integrated RF front-end module, BCTM Technical Digest, 2000, pp. 118-125B. Gilbert, Biasing techniques for RF/IF signal processing, presented at the MEAD Lecture Series short-courselecture, UC Berkeley, CA,1987P. Zampardi, III-V HBT Modeling Issues and Future Directions, CMRF 2004 Workshop, Montreal, Quebec, CanadaK. Kwok, Simple DOE-based inductor tool for design automation, 2008 CS Mantech Conference, Paper 17.2Y. Yang, An Innovative and Integrated Approach to III-V Circuit Design, Microwave Journal, September 2008, pp. 136-156

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