Engineering 303 Lab 1 Folsom Lake College Page 1 of 12

Engineering 303 Digital Logic Design

LAB 1 Introduction to Combinatorial Logic and Quartus Design Tool

Deliverables:

0) A Simple Verilog Combinatorial Circuit 1) A Simple Block Diagram Combinatorial Circuit 2) A Hierarchical Circuit -- Block Diagram Implementation

Please KEEP this handout for future reference. YOU WILL NEED IT.

Demonstration Requirement: To get credit for this lab, you must download the last design from part 2 to the DE2 board and demonstrate it to the instructor. Lab reports are due on the assigned due date, but demos can be done any time before, and up to 2 weeks after, the lab report due date. PROCEDURE This handout contains 3 tutorials. Complete all three tutorials and write a report documenting what you did. REPORT REQUIREMENTS Reports are an important part of this class. You must create nice reports for every lab. Reports should reflect your professionalism. Your report must be nicely formatted using a word processor and easy to follow. Manually create all the truth tables using Excel and paste them into the Word doc. Capture screen images of all the designs and all the waveform output windows for your report. (Using Windows Snipping Tool to capture screen images and paste into your report). Format your report with appropriate headings and titles as outlined in the course syllabus. Narrate your report appropriately so that some other reader who is unfamiliar with this lab could figure out what is going on. Include results of your testing and any conclusions. LAB FILE MANAGEMENT In this course it is important to manage you design files and store them on a removable USB drive. The Quartus design program requires each design by stored in a separate folder to avoid files being over written. Before starting each lab create a new folder on your USB drive labeling them Lab1, Lab2, Lab3, etc. In each Lab folder create separate subfolders for each design in the lab. For this lab you will create three folders:

➢ <Your USB Drive>:/Lab1/SimpleVerilog ➢ <Your USB Drive>:/Lab1/SimpleDiagram ➢ <Your USB Drive>:/Lab1/SimpleHierarchy

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Use Windows file explorer to double check your directory structure. Turn on file extensions in Windows explorer search File Explorer Options select View and check Show hidden files, folders,and drives -- uncheck Hide extensions for known file types.

Part 0 - Quartus Tutorial: System Verilog Design 1. Start the Quartus II Program on the PC. a. For the Altera DE2-115 Board

a. Start > Intel FPGA 18.1.0.625 Lite Edition > Quartus (Quartus Prime 18.1) b. For the Altera DE2 Board

a. Start > Altera 13.0.1.232 web edition > Quartus II 13.0sp1 (64-bit) NOTE: Intel FPGA 18.1.0.625 Lite Edition is an updated version that works only with the DE-115 board. Altera 13.0sp1 is the latest version that supports both the Altera DE2 board based on the Cylone II FPGA as well as the DE-115 board based on the Cyclone IV FPGA.

2. Make a new project. a. Start Quartus application in your PC. b. Click File//New Project Wizard. c. Click Next d. Enter Working directory: “<Your USB Drive>:/Lab1/SimpleVerilog” e. Enter Name of project: “SimpleVerilog” (this name must be the same as your folder name) f. Click Next on the Project Type page leaving Empty Project selected g. Click Yes if a prompt asks if you want to create a new directory. h. Click Next on the page where it asks you to add design files. i. Select the family and Device you want to target for your compilation:

a. For the Altera DE2-115 board select i. Family: Cyclone IV E ii. Available Devices: EP4CE115F29C7

b. For the Altera DE2 board select: i. Family: Cyclone II ii. Available Devices: EP2C35F672C6

j. Click Finish NOTE: Project names are case sensitive and must start with a letter. Project names that start with a number may result in a compile error. Next time you want to work on this project you can Open Project select the project file named SimpleVerilog.qpf file.

3. Enter Verilog code. a. Click File//New. Select “System Verilog HDL file” under Design Files . b. Type the following code as shown below:

If you close the code window, you can get it back by using the Project Navigator.

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c. Click File//Save As. The file name should come up as "SimpleVerilog.vs" Leave the name as

shown and click Save.

4. Compile.

Click the blue arrow (its purple in Quartus 13.1) to Start Compilation ~~~> If asked do you want to resave the file click yes If there are errors, view the errors at the bottom of the screen, fix them and recompile. You will get warnings about licensing, no clocks, load capacitance assignments, etc. You can ignore them and continue.

5. Simulate. a. Click File//New. Select “University Program VWF” under Verification/Debugging Files and OK b. In the Simulation Waveform Editor window, select Edit > Insert > Insert Node or Bus or double-

click under Name to open the "Insert Node or Bus" dialog box c. Verify Radix is set to Binary d. Click on Node Finder e. Check that the Filter is set to Pins: All f. Click List g. Click >> h. Click OK, OK again i. Click Edit//Grid Size and set to 100ns j. Click Edit//Set End Time and set to 0.4us ( or 400ns ) k. At this point you need to change the input signals “a” & “b” to 00, 01, 10, 11 for the respective time

segments as shown by the waveform below

l. You may set several signals at once using the count feature. To do this, first select a then hold shift key and select b to highlight both input signals “a” & “b”, right click > grouping > group to

group them, and give them a name like “input.” Next select a count icon on the menu bar to open the Count Value dialog box. Verify starting value is 00 with increment of 1 and transition count occurs every 100ns. Select OK and the Input should be set as an incrementing binary sequence (eg 00, 01, 10, 11). You can select the > in front of the group name input to display the inputs “a” & “b”. It should look like this now:

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Note: You may also use the mouse to highlight a time segment you wish to change (click-and-

drag on the waveform) then click: to set it to a logic 0 or 1. This method is helpful when you need to enter an input different from a binary count sequence.

m. Next Click the Run Timing Simulation button to simulate: ~~~>

If asked to save the file Waveform.vwf select Yes and Save. Do not change the file name given as this can result in an error. Quartus will add a number to the file name for subsequent simulations of the same file.

n. A Simulation Flow Process window should open, and you should get a simulation report in a separate window as shown below, which you can use to verify that your design works properly.

As shown, the output waveform “f” goes high when “a” & “b” are both high which is the expected operation of the logical AND function. Also note “f” goes high approximately 10nS after the transition of “b” at 300ns. This represents the propagation delay of the hardware found by the timing simulation.

If you ran a functional simulation by selecting the icon it would not evaluate delay.

Note: If using Quartus 13.1 and the simulation report doesn’t display or gives an error, verify that you are using the Quartus II Simulator tool and not “ModelSim”, which may not be installed. On the menu bar select Simulation and then select Options and within the pop-up select “Quartus II Simulator”. Re-run the simulation.

6. Assign Pin Numbers. a. On the Quartus main window Click Assignments//Pin Planner the Pin Planner window should

appear. b. Click the Location boxes and assign pins as provided in the table below. For example, we will

assign Switch 17 on the board for input “a”, which is pin number PIN_Y23 (PIN_V2 on the DE2 board). Likewise we assign switch 16 for input “b” and LEDR0 to output “f”. Note: The Altera DE2-115 User Manual can be found online and includes the complete list of pin assignments.

Signal Name Board Name DE2 Pin DE2-115 Pin

a SW[17] PIN_V2 PIN_Y23

b SW[16] PIN_V1 PIN_Y24

f LEDR0 PIN_AE23 PIN_G19

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7. ReCompile The design must be recompiled after any source code, device, or pin number

changes. ~~~~> 8. Connect the DE2 Board a. Connect the AC power supply to Altera board. b. Connect USB cable to the DE2 board USB port that is closest to the power connector. c. Power on the board by pressing red power switch

9. Program the DE2 Board a. On the Quartus Prime main menu Click Tools//Programmer b. Make sure the Program/Configure box is checked c. Click Hardware Setup. In the Hardware Setup window select USB Blaster under the currently

selected hardware dropdown then select close. USB Blaster should now appear in the upper left dialog box next to Hardware Setup. Note: The board must be connected and powered on for USB-Blaster to appear in the Hardware Setup dialog box, and you must have the USB Blaster driver installed on your computer. _____________________________________________________________________________ If you are using your own Windows PC to connect to the DE2 board you will need to install the drivers. The drivers are stored in the directory where the Quartus II program was installed; typically: c:\alter\quartus\drivers\usb-blaster. Installation instructions for Altera USB Blaster can be found here -> https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/drivers/dri-eb-ii-firmware.html 1. Plug the USB-Blaster cable into your PC 2. Open the Device Manager, and right-click on the Unknown device under the Other devices

branch, the one with the yellow warning triangle and question mark 3. Select Update Driver Software 4. Select Browse my computer for driver software

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5. Enter the location of the Quartus Prime software USB-Blaster II driver files directory; typically: c:\alter\quartus\drivers\usb-blaster (not USB Blaster II). Check the include subfolders box

6. Click Next 7. Click Install in the ‘Would you like to install this device software?’ security dialog box 8. Close the Update Driver Software - Altera USB-Blaster II configured successful installation

notification 9. Open the Quartus Prime Programmer. Within a few seconds, the JTAG cables branch

displays two nodes Altera USB-Blaster II (JTAG interface) and Altera-USB Blaster II (System Console interface)

10. Your installation is complete. ____________________________________________________________________________

d. Verify the RUN/PROG switch on the DE2 board, located left of the LCD display, is set in the RUN position to configure the JTAG programming of the FPGA by the Quartus II Programmer. Do NOT select the PROG position which is used to download a configuration file into the on board Flash.

e. Click Start to program the Altera Device (The board LEDs should stop blinking) and when done the progress bar should show 100% (Successful)

f. Test your design by flipping the switches (SW17 and SW16) and checking if the LED (LEDR0) lights up correctly when both SW17 and SW16 are in the up position. Document the measured results and compare to your expected truth table in your report.

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Part 1 - Quartus Tutorial: Block Diagram Design 1. Start the Quartus Prime Program on the PC. 2. Make a new project.

a. Start Quartus Prime application on your PC. b. Click File//New Project Wizard. c. Click Next d. Enter Working directory: “<Your USB Drive>:/Lab1/SimpleDiagram” e. Enter Name of project: “SimpleDiagram” f. Click Next g. Click Yes if a prompt asks if you want to create a new directory. h. Click Next on the page where it asks you to add design files. i. Select the family and Device you want to target for your compilation:

a. For the Altera DE2-115 board select i. Family: Cyclone IV ii. Available Devices: EP4CE115F29C7

b. For the Altera DE2 board select: i. Family: Cyclone II ii. Available Devices: EP2C35F672C6

j. Click Finish Next time you want to work on this project you can Open Project and select the project file SimpleDiagram.qpf file to open this project.

3. Enter Design Diagram.

a. Click File//New. Select “Block Diagram/Schematic File” under Design Files . b. Click File//Save As. Do not change the given file name "SimpleDiagram.bdf" as this must be the

same as the project name.

c. Click the Symbol Tool icon on the menu bar d. The Symbol Window should open. Expand the tree > c:/intelfpga_lite/18.1/quartus/libraries/ >

primitives > logic > and select the and2 logic primitive. (If using Quartus 13.1 then c:\altera\13.0.sp1\quartus\libraies\primitives\logic)

You should see this now:

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Note: Look through the other directories to become familiar where to locate primitives. Buffer (I/O buffers), Logic (AND, OR, NAND, NOR, XOR, XNOR,..), Other (Gnd, Vcc), Pin (I/O), Storage (D-flip flop, Latch, SR-flip flop, JK-flip flop,..)

e. Click OK f. Move and Click to place the icon on your block diagram design. g. Repeat to add 2 input pins and 1 output pin. You can place items next to each other to connect

them, and you can also use the “Orthogonal Node Tool” to draw wires to connect things. You can also just mouse over things and drag to draw lines. Warning: Don’t confuse Orthogonal Bus Tool as the Orthogonal Node Tool. The bus tool is for multiple node lines.

h. Double click the pin names to change them as shown. i. Play around with the graphical editor for a while. Should look like this now.

4. Compile.

Click the blue arrow to compile ~~~~> If there are errors, fix them and recompile.

The following steps are identical to the previous tutorial. Please refer to the previous section of this document. 5. Simulate. 6. Assign Pin Numbers. You can use the same pin assignments as in Part 0. 7. ReCompile 8. Connect the DE2 Board 9. Program the DE2 Board. Test your design by flipping the switches and verifying the

LED lights as in Part 0.

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Part 2 - Qartus Prime Tutorial: Hierarchical Diagram Design Simulation In this tutorial, you will combine 2 smaller designs into one larger design. NOTE: To do heirarchical design, you will be working with several projects simultaneously. Some projects will reference other projects, so the system needs to be able to find them.

1. Export Symbol Files for each Subproject.

a. It is possible to run several instances of Quartus at the same time. Start an instance of Quartus for each of your subprojects from the previous tutorials: SimpleVerilog and SimpleDiagram. Helpful Hint: double click the QPF file from Windows File Explorer to start a separate session for each file. You should have 2 instances of Quartus running, one for each project.

b. Open the Verilog file and the diagram file, for each project, respectively. c. Click File//Create / Update//Create Symbol Files for Current File. Do this for both projects.

2. Make a new Top Level Project.

a. Start a THIRD instance of Quartus. b. Click File//New Project Wizard. c. Click Next d. Enter Working directory: “<Your USB Drive>:\Lab1\SimpleHierarchy” e. Enter Name of project: “SimpleHierarchy” f. Click Next g. Click Yes if a prompt asks if you want to create a new directory.

3. Add User Library References to Sub-Projects. a. When it asks you to Add Files, click User Libraries

b. Under Project Libraries, Click c. Navigate to find the SimpleVerilog

folder and Click Select Folder, click Add.

d. Repeat step c to add the SimpleDiagram folder. You should see this ~~~>

e. Click OK, Click Next

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4. Select Device Same Cyclone IV EP4CE115F29C7 for the DE2-115 board or Cyclone II EP2C35F672C6 device for the DE2 board as usual.

5. Enter Top Level Design Diagram. a. Click File//New. Select “Block Diagram/Schematic File” under Design Files . b. Click File//Save As. Name the file "SimpleHierarchy.bdf". The block file name must be the

same as the project name.

c. Click the Symbol Tool icon on the menu bar d. Expand the folders and find the SimpleVerilog.bsf symbol file. Should see this now:

e. Click OK f. Click to place the SimpleVerilog icon on your block diagram design. g. Repeat the previous steps except for the SimpleDiagram.bsf symbol file.

h. Click the Pin Tool and add input and output symbols.

i. Connect things with wires using the Orthogonal Node Tool , using the mouse to make connections.

j. Double click the pin names to change them as shown. k. Play around with the graphical editor for a while. It should look like this now:

l. Practice using the Project Navigator to navigate thru the design hierarchy. You can also double click on the SimpleVerilog and SimpleDiagram blocks to go to their respective design files.

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6. Compile.

Click the blue arrow to compile ~~~~> If there are errors, fix them and recompile.

7. OPTIONAL - Edit Block Symbol Files (useful for large designs) a. You can Right Click a block, select Edit Selected Symbol, then drag the signal wires around on

the block symbol, the signal name will follow the movement of the signal wire. Below, I have stretched out the block and moved the g signal to the bottom.

NOTE: Do not select and move the signal name as this will disconnect it from the wire. Make sure to select the wire before moving it.

b. Select File->Save when you are done editing the Block Symbol File

c. Then go back to the SimpleHierarchy block diagram, Right Click the symbol you just edited, select Update Symbol or Block, choose an option, click OK.

d. You will need to fix the wires as appropriate.

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Recompile, simulate, assign pin numbers, recompile, program the DE2 board, and test as usual. Refer to previous tutorials for detailed steps. Your simulation report should look like below. Here the inputs have been grouped and named them Bob… although you will typically name them for their purpose like Input. Pin Assignments

Lab SIGNAL DE2 Name DE2 Pin DE2-115 Pin

x SW[16] PIN_V1 PIN_Y24

y SW[17] PIN_V2 PIN_Y23

f2 LEDR0 PIN_AE23 PIN_G19

f1 LEDR1 PIN_AF23 PIN_F19

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