Design for Manufacture Methodology for SiP
Stacked Structures
Side-by-Side Structures
Embedded Structures
A Two Year IeMRC Supported Project
LANCASTERU N I V E R S I T YCentre for Microsystems EngineeringFaculty of Applied Sciences
LANCASTERU N I V E R S I T YCentre for Microsystems EngineeringFaculty of Applied Sciences
SiP-Design
• Two Year Funded Project– January 2006 – December 2007
• Funding £200,000K : – Supports RA’s at Greenwich and Lancaster– Additional financial support from FP6 NoE in Design for
Micro & Nano manufacture (PATENT-DfMM)
SiP-Design : Industrial Support
• NXP– Wafer Level SiP Producer
• Selex– Avionics Systems
• Flomerics– Thermal/Electrical Design
Solutions• Coventor
– SiP Design Tools and Design for Manufacture Methodology
Objectives
• Realise algorithms and associated code to generate an integral thermal map across a behavioural model of an SiPfunction.
• Realise algorithms and associated code to model and couple electromagnetic and electrostatic fields into functional devices and materials within an SiP structure.
• Realise a method of injecting defects and degradation into behavioural SiP models. Address the Test Issue.
• Demonstrate the above advances in an industrial Virtual Prototype environment.
Key Challenges addressed
• Thrmo-mechanical modelling of Assembly and interconnect
• Stress and electromagnetic contamination monitoring within SiP packages
• Embedded Test
Lancaster University
• Centre for Microsystems Engineering– 4 academic staff, 5 RA’s, 4 PhD’s– Delivered against £3.4M in grant income over the past 10
years– Leads the European Design for Micro & Nano manufacture
community through the FP6 Network of Excellence (PATENT-DfMM)
Research, training and industrial services in the Engineering ScResearch, training and industrial services in the Engineering Science ience associated with Design for Manufacture Technology for Micro & associated with Design for Manufacture Technology for Micro & NanoNano
Technology based ProductsTechnology based Products
Key SkillsDesign methodology, modelling & simulation of MNT based structures and systems.Fault tolerant design, design for test, condition monitoring and test engineering for MNT based systems.Integration technology for MNT based systems (packaging)
Active ProjectsEU FP6 “INTEGRAMplus" Integrated MNT Platforms & Services (IP), “PATENT-DfMM” Design for Micro & Nano Manufacture (NoE) and “MINOS-EURONET”Micro-Nanosystems European Network pursuing the integration of NMS and ACC in ERA.EPSRC "Nanoelectronics”: from novelty toys to functional systems" 2006 – 2009 and IeMRC projects SiP-Design and I-Health.HEIF / NWDA Science & Entrepreneurship training award in MNT
Centre for Microsystems Engineering - Mission
University of Greenwich
• Centre for Numerical Modelling and Process Analysis– 5 Profs, 20+ Post Docs, 40 + PhD’s– One of largest groups in UK
• Electronics and Microsystems – 2 Profs, 3 Post Doc’s, 5 PhD’s– Over £2m of support since 1998 in electronics and microsystems
modelling.
Expertise - Reliability
• Physics of Failure approach• Exploitation of COTS • Modelling to support HALT
– Thermal, Power Cycling, Vibration• BGA’s, Flip-Chip, etc.• Consumer, Medical, Aerospace,
automotive, etc.
Accelerated Life Testing Fatigue, etc
Interest from NXP
• Solder Joint Reliability– Wafer Level CSP SiP Modules– Virtual Design of Experiments
• Thermo-mechanical Analysis– Vertical Metallic Structures in Silicon
• Electro-magnetic analysis– shielding of TV tuner device– Diagnostics/Test Bench
• Embedded Test– Low cost, high throughput embedded
test solutions
Interest from Selex
• E-Scan Radar Technology– Transmission/Receive Modules
• Power Amplifier + Core Chip
– High Power Density– High Frequency
• Concerns– Thermal Management– CTE Miss-match– Lead-Free Solders
• Modelling– Transient Analysis for High Frequency– Trade-off between electrical, thermal and mechanical
ASICMMIC
GaAs
3W
Si
ASIC
0.5W
Progress to Date (1st 9 months)
• NXP main driver with Flomerics and Coventorproviding tool access– Build a modeling & Simulation infrastructure to build a
reliable SiP infrastructure (assembly and interconnect)– Build a solution to monitoring stress and
electromagnetic contamination within SiP packages– Investigate embedded test solutions for both the SiP
infrastructure and RF / functions with non-electrical interfaces.
Reduced Order Modelling (ROM): Model Reduction
Full Model PDES
System of n ODEs
Space
discre-tisation
Model
Reduction
Reduced system of r<<n ODEs
• Techniques• Order Reduction Techniques
• Proper Orthogonal Decomposition• Krylov Subspace Methods
• Response Surface Analysis• Compact Models
Assembly & Interconnect (NXP Demonstrator)
UF2
PCB
Passive die
Active die
UF3UF1
Top passivation
Objectives:• Investigate the influence of various design parameters and their
combinations on the reliability (life time) of SiP• Perform sensitivity analysis and identify the most influential
factor(s)
Failure Models
• Solder (SAC)– Creep
• Failure Model (Fatigue)
)exp()(sinhRT
QA n
cr
−×=
•
ασγ
A n α Q/R
Sn37Pb 9.6E4 3.3 0.087 8058
Sn3.5Ag 9.0E5 5.5 0.065 8690
1)0014.0( −= WpN f
Creep Strain Energy
Geometry
PCBBalls
Passive die
Active die
UF1
UF2UF3
One-eight of the SiP modelled due to symmetry
Von Misses Stress and Deformation Modes for SiP 11× 11
Identifying Suitable Underfills
• Design Space– Youngs Modulus– CTE
• Design of ExperimentsE (GPa)
6
4
2
20 40 60 CTE (ppm/°C)
2040
60
2
4
6
0
50000
100000
150000
200000
250000
300000
350000
400000
450000
500000
Damage (Pa)
CTE(ppm/C)
E(GPa)
UF2
PCB
Passive die
Active die
UF3UF1Top passivation
Reduced Order Model for Underfills
2 2( , )E ECF a b d E g hC C E kC= + + + + +
a 35473. 67b -1659.33d 13784g 192779h 2635.667k 217253.6
The cost function that expresses Accumulated Creep Energy Density in terms of CTE (C) and Young Modulus (E) found by Composite Design Method appears to be quadratic
1 4 7
10 13 16 19
S1
S6
S11
S16S21
050000
100000150000200000
250000
300000
350000
400000
450000
500000
Damage (Pa)
CTE (ppm/C)
E (GPa)
22 6(GPa)0 60(ppm/ C)C
E≤≤≤
≤ o
Identifying Critical Design Paramters
• What can designer change?– Underfill 2 & 3– Die Size– Die Thickness
UF2
PCB
Passive die
Active die
UF3UF1Top passivation
Actual values7×7; 9×9; 11×11mmNo; YesNo; Yes200µm; 400 µm
Die SizeReinforcement (UF2)Underfill (UF3)Passive Die Thickness
Sensitivity Analysis
1 2 3 4 1 2 3 4( , , , )f x x x x ax bx cx dx e= + + + +
• A contribution of a critical parameter to the cost function appears linear
Accumulated Creep Energy Density
Actual values Values in f7×7; 9×9; 11×11No; YesNo; Yes200µm; 400 µm
x1 Size -1; 0; 1x2 Reinforcement (UF2)
UF3Passive Die Thickness
-1; 1x3 -1; 1x4 -1; 1
Sensitivity Analysis
1 2 3 4 1 2 3 4( , , , )f x x x x ax bx cx dx e= + + + +The coefficients of the function have been determined by the Least Squares Method based on 18 experiments
-40000
-30000
-20000
-10000
0
10000
20000
30000
40000
50000
a b c d
Sensitivity Analysis
1 2 3 4 1 2 3 4( , , , )f x x x x ax bx cx dx e= + + + +Most influential parameters:
a (Size) – the highest absolute value ≈ 40,000, positive
The larger the size, the morethe damage, the less reliable SiP
-40000
-30000
-20000
-10000
0
10000
20000
30000
40000
50000
a b c dc (UF3) – the second highest absolute value ≈ 36,000, negative
If present, the less the damage, the more reliable SiP
Status
• The presence of UF3 can improve reliability of the SiPPackage
– CTE is the most influential– CTE as low as possible– Elastic Modulus as high as possible
• SiP design parameters– SiP size and presence of UF3 are the most influential parameters– Passive Die thickness and Presence of UF2 have smaller effect
on solder joint reliability– Recommendation: to improve reliability smaller package
size with suitable UF3 and thinner Passive Die
Inter Metallic Layer (IMC)
Solder Ball Reliability
Weibulldistribution
β : Weibull slope parameterη : Characteristic life parameterN : Random thermal life cycles to failureδ : IMC layer thickness
So ACK, Chan YC. Reliability studies of surface mount solder joints–effect of Cu-Sn intermetallic compounds. IEEE Trans Comp Pack Manuf Technol–Part B 1996; 19:661-668.
Objective : Build an Analytic Method of Reliability for Solder Joint in Package
Inter Metallic Layer growth
t : Reflow time
Dependence on reflow time (given temperature) :
δ : IMC layer thickness
T : Temperature of reflow
Dependence on temperature (given time) :
Reflow profile
* More accurate than polynomial fitting proposed in Huang W, Loman JM, Sener B. Study of the effect of reflow time and temperature on Cu-Snintermetallic compound layer reliability. Microelectronics reliability. 42(2002) 1229-1234.
Ts : saturated temperature
*
Results : 3D plots
- Low reflow temperature
Desirable interval [190,240]
- As small a reflow time as possible
• Reliability and MTTF of solder joint (63Sn37Pb) depend on reflow time and temperature.
• For high reliability we suggest reflow temperature between 190oC & 240oC. Avoid temperature between 250oC and 270oC . Reflow time is as low as possible.
• Next• Investigate the lower limit of the reflow time.• Extend this method to other solder material.
Status
Electromagnetic Contamination Monitoring
Investigated two antenna architectures :
• Dipole • Loop
Analytical model for these two antennas exists
Dipole: Simulation versus analytical model
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+001.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09
Cl (F)
Sens
itivi
ty (V
/V/m
)
AnalyticalSimulation /1Simulation /pt
h = 7.5cm
he = 7cm
Smax = 0.07 V/V/m
Ca = 1.37 pF
MicroStripessimulation
Without load
Hz (centre)= 1.33mA/A
Dipole: Simulation versus analytical model
Status
• Initiated work on standard EM probes• Initiated simulation work using MicroStripes• Working with Philips technology to design the EM
probes• Working with Philips to evaluate the shield
effectiveness using MicroStripes• Investigating Intra SiP coupling
Digital ICRF Electronic
MEMS
Analog IC
MemoryHealthmonitor
Standard test access
SiP
- Production testing- Online testing- Reconfiguration
Embedded Test – Health Monitor Concept
• Reusable, flexible, standard: programmable, reconfigurable• Low performance -> low frequency• Share by a lot of components• Have a lot of functionalities : production testing, online testing
and reconfiguration/reparation of the SiP to improve yield or reliability.
Low cost
• Vision : An embedded tester – challenge : non-electrical interfaces
Example 1
• RF Receiver / transceiver
MEMS inductors, MEMS variable capacitance, MEMS switches, MEMS resonator, MEMS micro machined cavity, Micromachined transmission lines
Case study : RF MEMS capacitive switch
Cup / Cdown
RF in RF out
RF choke
DC blockDC block
Vbias
Bridge Dielectric
Substrate
UP DOWN
Equivalent schematic with passive components to superpose the actuation signal
MEMS switch : bias superposition
Cup / Cdown
RF in RF out
Vbias
Actuation generator
Test generator
Cp
RF switch controller
Test response analyser
Health Monitor
Ract
Rtf
Ctf
Enveloppedetector
Cstim
Cbl Cbl
Lch
Switch with passive components
Vin Vout
Vs
Vstim
Vtr
Vact
Passive components integrated on the substrate
MEMS switch : bias superposition
Actuation generator output RF line voltage
UPDOWN
UPDOWN
Amplitude variationAmplitude variation
Test response Switch output
In the UP state, the capacitance measurement is affected by parasitic capacitances.
Stiction and breakdown of the dielectric should be detected
Status
• Low frequency testing of a RF MEMS switch by the a low cost Health Monitor is possible although limited by parasitic impedances
• The feasibility of this technique should be proven on other devices to build a Health Monitor
Outputs
• 3 Conference Papers– IEEE IMSTW, June 2006, Edinburgh.– NMI / EPPIC workshop on wafer level packaging, June
27th 2006, Cambridge.– IEEE EPTC, December 2006, Singapore
• Invitation for Journal Article in Circuit World• Invitation for FP7 Proposal Collaboration
Conclusions
• SiP technology is complex and now the primary packaging platform for integrated MEMS
• Research challenges associated with manufacturability extensive and beyond the scope of the project
• Initial work focused on 4 challenges– Assembly reliability, solder ball reliability, electromagnetic
contamination and embedded test• Future focus on assembly and interconnect reliability
simulation– Electromagnetic contamination and embedded test handled by I-Health
• Looking to FP7 for further support in cooperation with French national project AMELIA.
