Engineering of a CDMA radio uplink for a mobile rad i o demr o nst r a t i o n system

J .I? Ald is A.H. Kemp S.K. Barton

Indexing terms: Cellular radio, Power control mechanism, Rake receiver, Spread spectrum

Abstract: A CDMA mobile radio demonstration system has been sreated by a joint industry/ university project in the UK. The paper describes the engineering of the reverse link (from mobile to base station). The link hardware is described. The main features of interest are the power control mechanisni and the all-digital rake receiver. Results presented illustrate the BER performance over a multipath channel simulator and the power cont eo1 mechanism performance.

1 introduction

The Department of Trade and Industry and the Engi- neering and Physical Sciences Research Council of the UK government are running a programme called Link which aims to encourage co-operation between univer- sities and industry. One of the projects funded under phase one of the Link Personal Communications initia- tive is entitled ‘A rigorous evaluation of CDMA for future european persorial communications systems’ [I]. As well as extensive theoretical research, one of the key objectives of the project has been to design and build a demonstration mobile radio system using code division multiple access (CDMA). Its purpose is to provide real measured data (bit error ratios, channel impulse responses, power control loop performance data, etc.) for further analysis ancl to prove the practicality of the system concept developed within the project. As the system is a research tool rather than a consumer prod- uct, there are no restrictions on physical size or power consumption for its components. Fig. 1 shows the reverse link being bench tested.

The project has been undertaken by a consortium of four organisations: AT&T Network Systems UK are the project leaders. Within the demonstratilm system development they are responsible for providing a fixed network to connect the base stations and provide mobility management.

0 IEE, 1997 IEE Proceedings online no. 19971503 Paper first received 15th March 1996 and in revised form 19th February 1997 J.P Aldiu i s with Ascom STU, Gewerbcpark, 5506 MBsenwil, Switzerland

A.H. Kemp and S.K. Barton are with the Telecommunications Research Group, Department of Electronic and Electrical Engineering, University of Bradford, Bradford, West Yorkshire BD7 IDP, UK

Hewlett Packard Research Labs are primarily responsi- ble for development of assessment tools and artificial system loading for the demonstration system. University of Bradford are responsible for development of reverse link radio hardware. University of Bristol are responsible for development of forward link radio hardware.

This paper describes the development work done in the Telecommunications Research Group at the Uni- versity of Bradford. It is exclusively concerned with the reverse link hardware. The design of the modulation and detection scheme is only briefly described. More detailed descriptions may be found in the references, particularly [2] for the overall reverse link air interface and [3] for the design of the rake receiver.

Fig. 1 Bench testing of reverse link

1.1 System overview The demonstration system is a simple cellular radio system, consisting of a switching centre and mobility manager, base stations and mobile stations. Full duplex links are supported between terminals attached to the mobility manager and terminals attached to the mobile stations. The decoding of the base station received data takes place in the mobility manager so that diversity combining can take place during soft handover. The terminals are ISDN terminals and may be telephones, fax machines, computer modems or any other basic- rate ISDN equipment.

The user bit rate is 64kbitls which data is obtained from one or both of the two ISDN B channels in the

ries the signalling required to set up and support the ISDN connection, is translated into a more compact form for transmission over the radio link. This control

basic rate interface. Thc ISDN D chaniiel, which car-

IEE Proc.-Commun., Vol. 144, No. 5, October I997 341

channel also operates at 64kbitis in the physical layer, but it is only used when needed and hence is silent nearly all the time. In previous papers [2, 41 the design of the air interface has been presented. Some of the important parameters of the air interface are listed in Table 1.

Table 1: System parameters

frame timing

Parameter Item Detail

Frequency division duplex forward link carrier 1823MHz reverse link carrier 1727.5MHz

Modulation forward link QPSU reverse link BPSK

Chip rate 8.192 MHz Transmit bandwidth 3dB point 7.8MHz

40dB point < 9.8MHz

Bit rate ISDN-B channel 64kb/s

Spreading sequences length 229 - 1 period = 66s m-sequences

Coding convolutional U = 7, R = 112

Coherent detection Rake receivers Reverse link aower control closed 1001)

i polarity symbols position in frame trafficchannel

offset PRBS

The reverse link radio hardware is divided into four parts. These are baseband processing in the mobile sta- tion transmitter (coding, interleaving, spectral spread- ing, pulse shaping), analogue and radio frequency (RF) processing in the mobile station transmitter (up-conver- sion, power control), R F and analogue processing in the base station receiver (amplification, filtering, down- conversion, automatic gain control) and baseband processing in the base station receiver (rake receiver). Each of these four parts is described in more detail.

2 Mobile transmitter baseband processing

The physical platform for the mobile station in the demonstration system is a VME rack. The rack can contain up to 21 double-eurocard sized printed circuit boards (PCBs). All the digital signal processing (DSP) functionality within the mobile station is contained on such boards. The boards may be controlled either through the VME bus or through the VME subsystem bus (VSB). All the baseband processing in the mobile station transmitter is contained on one six-layer PCB. Two layers are used for signal routing and the other

activitv flaa

four are reserved for low-impedance ground and power planes. There are two ground planes and two power planes (+5V) so that the digital-to-analogue converters (DACs) may have separate digital and analogue sup- plies.

Fig. 2 shows a simplified schematic of the baseband processing in the mobile transmitter. Two channels are processed in parallel. They are called the reverse traffic channel (RTC), ‘a continuous ISDN B-channel at 64kbitis’ and the reverse control channel (RCC), a noncontinuous channel at 64kbith composed partly of the translated ISDN D-channel, partly of radio resource control channel information and partly of reg- ular bursts of all-zero data, which provide a polarity reference for the rake receiver in the base station. These two channels are processed to produce separate base- band analogue signals, which will be upconverted to the same carrier frequency in quadrature with each other.

Both channels are rate 112 convolutionally encoded for error control. This increases the on air bit rate to 128kbitis for each channel. The RTC data is inter- leaved before transmission. The RCC is not inter- leaved. A physical switch is provided so that the coding and interleaving may be bypassed and raw data injected instead. This permits bit-error measurements to be made over the radio channel.

The two channels are spectrally spread by modulo-2 addition of pseudorandom bit sequences (PRBSs). The two PRBSs used are both offset versions of the same m-sequence. The offset between them is 512 chips, or 6 2 . 5 ~ . The m-sequence is generated using a 29-stage shift register with feedback, and the shift and add property of m-sequences is used to generate the offset versions from it. Each PRBS is formed by the sum (modulo 2) of a fixed subset of the shift-register taps. The PRBSs for the two channels thus appear to be dif- ferent and statistically independent of each other. The m-sequence generator is under software control. Through a sequence of write Operations on the VSB, it may be stopped and the shift register put into an arbi- trary state and restarted.

The convolutional coding, spectral spreading and m- sequence generation are all implemented using pro- grammable logic devices (PLDs). The interleaver is implemented using a PLD and a single static random access memory chip (SRAM). PLDs are used widely in

control channel offset PRES

enable I I

alternative data source (128 kb/s)

up- conversion On phase) data continuous souTce jpH-bw convolutional encoder interleaver block PSF

( 6 L kb/s)

convolutional data source up- conversion bur (6L kb/s) ~ ~ ~ - - ~ ~ H - & ’ - t - zero (quadrature 1

Fig. 2 PSF = pulse shaping filter

342

Schematic of mobile station transmitter baseband processing

IEE Proc-Commun., Vol. 144, No. 5, October 1997

the reverse link hardware; they save space on circuit boards and often permit design changes to be made without the need for physical changes to the PCBs.

The transmitted spectrum is controlled by digital finite impulse response (FIR) filters clocked at 24.576MHz, i.e. three times the chip rate. It is not nec- essary to have a tightly controlled pulse shape at the transmitter because 1 he signal will pass through an unknown multipath channel. The rake receiver approx- imates the matched filter to the combined channel and transmitter pulse shape, which is optimum in AWGN (or near optimum when the gaussian approximation applies). The FIR is designed to control out-of-band radiation above 4.92MHz to at least 40dB below the band-centre spectral density to avoid deep nulls in band and to minimise the delay spread it introduces. In band ripple was thus specified as 2dB to 3.93MHz and achieved with an impulse response of 11 chips. As the filter inputs are binary it was implemented as a stored waveform filter. The last 11 chips are stored in a shift register and this shift register, along with two interpola- tion bits which count from 0 to 2 at 24.576MHz, form the address bus for a fast SRAM which contains all possible waveforms which could be transmitted. The SRAM is loaded from an erasable programmable read only memory (EPROM) at power-up.

The outputs of the DACs which follow the lowpass filters provide the inputs to the first upconversion stage in the mobile station transmitter. These outputs have a mean power of -1OdElm each into 50 ohm loads. The RCC is switched off when there is no message or polar- ity symbol to be transmitted by forcing its DAC input to zero.

3 Mobile station transmitter analogue and RF stages

The up-conversion and power amplification stages of the mobile station transmitter are complicated by the power control requirements. In a CDMA radio system it is essential that the received power level should be as low as possible (within some quality of service con- straint) because one user’s signal is every other user’s interference. In a cellular radio system path losses between mobile and base stations may vary over a range of up to 80dB [5 ] , as the distance from mobile to base and the level of shadowing changes. The mobile station therefore needs an 80dB range on its transmit power.

Fig. 3 shows a schematic of the up-conversion and power control processing within the mobile station. Physically these components are either purchased as connectorised modules or else mounted on PCBs in metal boxes at the University of Bradford. All the con- nections between components use semirigid coaxial cable. The whole assembly is contained within a 19 inch rack-mounting metal tray, separate from the VME rack which contains thr: baseband (digital) processing.

The design of the up-conversion stages is quite straightforward. The two baseband signals are up-con- verted in quadrature tct an IF at 70MHz using a com- mercial QPSK modulalor. Following a filter there is a further up-conversion to the carrier frequency 1727.5MHz. An interdigital filter is used to remove the image frequency. Sinail-signal amplifiers are used to increase the signal level and then the signal is attenu- ated by between 10 and 70dB by a cascade of digitally controlled attenuators. A further small-signal amplifier

IEE Proc -Conimun , Vol 144, Nc 5, October 1997

is used as a preamplifier for the power amplifier (PA), which is linear up to about 1 watt of output power. Following the PA there is a further digitally controlled attenuator, a filter to reduce any spurious signal com- ponents, and a directional coupler to permit the trans- mit signal to be monitored. The output of the mobile station transmitter is then fed (through a circulator) to the antenna. A lOMHz reference frequency and a 70MHz intermediate frequency are available as inputs to the transmitter.

resonant small signa( cavity PA: amp

I 5-pole ANP-O111S MAR-7 ( i)

1OdB directional coupler digitally controlled ZFDC-10-5 attenuators ( i i )

digitally controlled attenuators ( i i i )

r--- 1 mixer:

-10dBm per channel

L + I O dBm

10MHz 70 MHz reference +IO dBm + I O dBm

Fig. 3 ing Final 5-pole resonant cavity filter ins. loss = 2SdB PA gain = 33.2dB (i) gain = IOSdB, IdB compression pt, +4dBm (ii) ins. loss between 2.5 and 33.5dB (iii) ins. loss between 10.0 and 70.0dB (iv) gain = 21 dB, 1 dB compression pt. +4dBm

Schematic of mobile station transmitter analogue and RFprocess-

The positions of the digitally controlled attenuators and the small-signal amplifiers are largely determined by noise-figure considerations. If attenuation poten- tially as high as 80dB is inserted before an amplifier then it is possible that the signal out of the attenuators will be below the amplifier’s noise floor. Thus the sig- nal power before the attenuators must be kept as high as possible. One consequence of this is the positioning of the final attenuator block after the PA.

1 d0 2dB LdB 8dB 16dB

- 1 2 digital control word

Fig. 4 Internal operation of digitally controlled attenuator block

The internal structure of one of the digitally control- led attenuators is shown in Fig. 4. These are proprie- tary devices mounted in an aluminium box with SMA connectors. They comprise five fixed attenuators, whose values are 1, 2, 4, 8 and 16dB. Each of the fixed attenuators may be switched into the signal path or bypassed. Thus a five-bit digital control word can be

decibels between 0 and 31. In practice there is a mini- mum insertion loss of about 2.5dB, to which the pro- grammed attenuation is added.

used to set the insertion loss to any integer number of

343

In theory, just three of these attenuator blocks should be required to provide a power range of more than 80dB with a 1 dB resolution. In practice, the 16dB attenuators are somewhat less accurate than the smaller ones, and also introduce much greater phase shifts. These problems could have severe effects on system performance. The power setting need not be very accu- rate but it must be monotonic with the desired level, or the power control loop could become unstable. Phase shifts introduced by the power control attenuation can produce serious transient effects in the bit-error ratio (BER) performance of the coherent receiver. To avoid these problems the 16dB attenuators were all hard- wired out of the signal path, except for the one in the final attenuator block. Hence the 16dB attenuator is only used when the required attenuation exceeds 75 dB, i.e. all five attenuators switch to 8 + 4 + 2 + 1 = 15dB before the last one switches in 16dB. This improves the accuracy of the power setting and guarantees that phase steps caused by power level switching are not a problem. On the other hand, it means that five rather than three attenuator blocks are required.

A plot showing the spectrum of the transmit signal is shown in Fig. 5. The significant inband ripple is a fea- ture of the frequency response of the digital FIR filter. This spectrum is for a midrange power level. The max- imum transmit power is approximately +20dBm, or 0.1 watts.

llKR 1 . 7 2 7 5 8 GHz $F - 1 5 8 d B m RT I8 dB - 2 6 . 1 2 d B n S N P L L O G 18 d 8 / NRRKER

MRRKLR RMPTO

A U G S E L E C T 1 8 8 1 2 3 4

nn 5 6

NARKER

- 2 6 . 1 2 QBm 1 . 7 2 7 5 8 G H Z

M R R K E R I Ut OFF

M O ? * - I O f 2

S C F C C O R R

S P R N 4 8 . 8 8 M H Z UBW 100 k H z SWP 2 8 . 0 m 5 e r

C E N T E R I 7 2 7 5 8 G H Z R E S B W 388 k H Z

Fig.5 Spectrum of trunrmitted signal

ase station receiver analogue and RF processing

As with the mobile stations, the base stations in the demonstration system each consist of a 21-slot VME rack and a separate 19-inch tray. The DSP and control functions are contained on PCBs within the VME rack and the tray contains the RF and analogue circuitry.

The downconversion chain in the base station is illus- trated in Fig. 6. It is largely composed of similar, or the same, components as the upconversion chain in the mobile station. It is also constructed similarly to the analogue and RF sections in the mobile station, com- prising components in separate connectorised boxes with semirigid coaxial cable joining them together.

The noise figure for the receiver is determined almost entirely by the low-noise amplifier (LNA) whose gain is

the receive chain are a filter and a circulator, both of whose insertion losses are less than 0.5dB. The overall noise figure is approximately 2.5dB. A directional cou- pler is available so that additional interference may be inserted, for simulation of a fully loaded network. As in the mobile station transmitter, 70 and 10MHz sig- nals are available as inputs, A large amount of overall amplification is required in the receiver. As well as the LNA there are three cascades of amplifiers, which pro- vide a total amplification of more than 90dB. A SAW

greater than 30dB. The only things which precede it in

344

filter is used as a noise rejection filter at IF. This filter has a bandwidth of 10MHz with a centre frequency of 70 MHz

additional interference input

circulator: I resonant

transmitter ref +7dBm - I

L SLP-21.4

- - 3 MAR-7 3 MAR-7

AGC 70 MH2 c o h h t + 7 d B voltage

Fig. 6 (i) noise figure = 1.92dB, gain = 34.6dB (ii) ins. loss = 27dB

Schematic of base station receiver analogue and RFpvocessing

An automatic gain control (AGC) loop is used to ensure that the signal power is correct at the input to the analogue-to-digital converters (ADCs). This is important because it minimises quantisation noise. The AGC loop consists of a variable gain amplifier and an AGC detector. The variable amplifier provides a range of about 40dB in gain, controlled by the current into one of its pins. A resistor network makes this effec- tively a voltage controlled device, with a linear-in-dB gain characteristic over most of its range. The wide bandwidth of the signals (= 10MHz) ensures that the AGC loop may be very accurate.

The received signal is downconverted from 70MHz to baseband using a quadrature demodulator and then fed to a pair of ADCs. These ADCs are clocked at 24.576MHz, three times the chip rate. They each out- put four bits per sample. Four bits are sufficient because the despreading process combines 64 samples to produce the decision variable for each bit suppress- ing the quantisation noise to the equivalent of over seven bits of resolution. The quantisation noise is thus suppressed by the processing gain of 64 in the same way as all other sources of noise. The I and Q outputs of the ADCs together form an eight bit word which is updated at 24.576MHz. This signal forms the input to the baseband digital rake receiver(s) in the base station.

5 processing

The radio link uses a coherent rake receiver It is implemented in hard-wired digital logic and is by far the most complex part of the reverse link hardware. It consists of five double-eurocard sized PCBs. Fig. 7 shows the division of functionality between these cards. The dashed boxes represent the PCBs and the outlined boxes represent the low-level functions. All five PCBs are supplied with the same 24.576MHz clock. The clock is buffered on each board and the buffered clock is used to clock all the logic. On some of the boards it has proved necessary to have multiple clock nets and

Base station receiver baseband digital

IEE Proc -Commun , Vol 144, No 5, October 1997

PCC PCC - - - - - - - - - - - - -

channel estimator

decision feedbock Fig.7 Simplzjied structure of base station digital procesring

hence multiple clock buffers to ensure that the clock distribution is satisfactory.

The physical interfaces between the PCBs are mainly based on IDC ribbon cable although some signals, such as the clock, are carried separately on coaxial cables. High-density ribbon cable (0.035 inch spacing) has been used to save space. The interfaces are synchro- nous with the 24.576MHz clock. That is, data is read in at the receive end of the interface using a clock rising edge and new data is put on to the interface directly following a clock rising edge at the transmit end. Clock distribution and crosstalk levels proved good enough for such interfaces to work reliably for ribbon cable lengths up to 0.15m.

The rake receiver f o r m an adaptive matched filter to the received pulse shap:, which itself depends on both the fixed transmitter FIR filter and the varying multip- ath channel. There is nl3 separate filter matched to the transmitted pulse shape because broadband white noise is suppressed by the SAW filter at IF.

5. I The basic mechanism by which the receiver works is very simple. There are separate channel estimation and data recovery functions. The channel estimator esti- mates the impulse response of the radio channel. It produces a continuous stream of channel estimates and is completely reset after producing each one. Every time a new channel estimate becomes available it is used to reconfigure the rake receiver, which is where the data is recovered. The data recovery is thus per- formed using the last completed channel estimate, so the assumptions about carrier phase, etc. are always slightly out of date.

The channel filter finds the crosscorrelation between the received signal and an estimate of the transmitted signal. This crosscorrela tion depends on the blockwise autocorrelation of the transmitted sequence (i.e. the PRBS modulated by the data) the noisehterference and the impulse response of the radio channel. Both the noise and autocorIelation contributions will be additive and random (wjth mean zero) and so the out- put of the channel filter I S a noisy estimate of the radio channel impulse response.

The estimate of the transmitted signal is obtained by modulating the traffic channel PRBS with the data recovered from the rake. This is referred to as decision feedback and is shown i n Fig. 7. To use this decision feedback both the PRBS and the received signal must be delayed until the daia bit they refer to has been recovered by the rake.

Channel estim(3tor: channel filter

The channel filter is thus formed from a pair of delays and a complex FIR filter. The taps of the filter are (real and) binary and must be updated in parallel (i.e. block- wise) after every symbol period, that is once every 7 . 8 ~ . The filter has 192 taps, because there are 192 samples of the 24.576MHz clock in each symbol period.

This functionality was implemented using commer- cially available devices. Programmable data buffers form suitable delays and six binary correlators are used for the filter. Two cascades of three correlators are required, one for the in-phase part and one for the quadrature part of the received signal.

5.2 Channel estimator: channel averager The channel filter produces a stream of complex sam- ples at 24.576 mega samples per second. These samples may be divided into vectors of length 192. The function of the channel averager is to find the elementwise mean of these vectors over some time period. This process enhances the channel impulse response relative to the noise, interference and autocorrelation components.

The rate at which the channel estimates are produced should be optimised. The shorter the period allowed for averaging, the noiser the channel estimate. The longer the period, the more out of date the channel estimate used in the rake becomes, and the more the receiver performance is degraded by a time-variant channel. On the channel averager PCB the averaging period may be set by moving a jumper. It may be set to N symbol periods, where N is a power of two between 2 and 128. Thus the averaging time can be varied between 1 5 . 6 ~ and lms. The channel averager stores a complex channel estimate in a continuously circulating shift register of length 192, and simply adds the sym- bols from the channel filter to the circulating compo- nent.

When the receiver is first started it will not have a correct channel estimate and will not be able to recover data until it locks to the signal from the mobile station. During this time the channel filter has no decision feed- back and so the channel impulse response components from it will be modulated by data at the symbol rate. The average of the output of the channel filter would be zero, rather than the channel impulse response. To overcome this problem the channel averager can dou- ble the phase of the channel filter output, and halve the phase of the channel estimate when it is complete. This nonlinear operation removes the data modulation from the channel impulse response estimate at a cost of some noise enhancement and, more seriously, a loss of rela- tive coherency between different multipath echoes. The

IEE Pro<.-Commun., Vol. 144, No. 3, October 1997 345

phase doubling and phase halving functions are per- formed using lookup tables. The lookup tables are stored in EPROM and written to fast SRAMs on power-up.

5.3 Channel estimator: peak searcher The principle of the rake receiver is that if multipath echoes exist separated by more than the chip period, they may be used to give a diversity gain. There are several receivers, each one locked to a different multip- ath echo, whose outputs are combined. The function of the peak searcher is to search the channel estimate for the most useful multipath echoes, and to reconfigure the rake receiver to use them. The peak searcher finds the four (the rake has four tines) components of the channel impulse response estimate which have the larg- est complex magnitudes, subject to the constraint that none of them should be within a chip period (three clock cycles) of each other. The search algorithm requires four symbol periods. The complete channel estimate is cycled through the peak searcher four times. Each time the peak component found on the previous cycle and its neighbours are set to zero, and the com- ponent with the next largest magnitude is found.

5.4 Rake receiver The rake receiver comprises four identical sections, called tines [Note 11, each of which is a complete spread spectrum receiver (except that it has no acquisi- tion or tracking circuitry). Each tine consists of

5.4.1 Variable delay element: The signal must be delayed by the additive inverse of the delay in the radio channel. This design is based on delaying the signal rather than the PRBS because this enables reconfigura- tion without symbol erasure. It is possible to design a rake receiver which delays the local PRBS rather than the received signal, but such designs cause problems with alignment of outputs as well as symbol erasures when the rake is reconfigured. The variable delay ele- ment is implemented using programmable data buffers. These are not ideal because it takes some time for the outputs to stabilise when a new delay is programmed; consequently two are used in each tine, and the output switched between them.

5.4.2 Despreader: To despread the received signal it must be multiplied by the local PRBS. This needs to be done for the in-phase and quadrature components for both the RTC and RCC PRBSs.

5.4.3 Integrate and dump: After despreading, the signals must be integrated over the symbol period to filter out the wideband noise. Four integrate-and-dump filters are required in each tine, as for the despreading function.

Physically, each tine consists of the two programma- ble data buffers and a pair of PLDs. One of these PLDs is used to store the combining coefficients and to control the delay elements. The other contains all the despreaders and integrate-and-dump filters. The tine outputs are combined using an FIR filter device.

5.5 Other receiver functions

5.5. ’I PRBS generation: PRBSs are generated in the same way as those in the mobile station transmit-

Note 1’ tine n Point, prong, e g. of antler, harrow, or fork (The Concise Oxford Dictionary, 1967)

ter. In the base station receiver, however, the acquisi- tion and tracking functions also affect the PRBS generation. The acquisition strategy uses a reduced search. Because the mobile station has recovered sys- tem timing information from the forward link it can be assumed that the PRBS being used to spread the data in the mobile station transmitter is delayed no more than a few tens of microseconds relative to the forward link reference PRBS, plus a predetermined offset, in the base station. During the acquisition process channel estimates are found and searched as normal. If no sig- nal component is found in a channel estimate then the local PRBS is delayed by one symbol period for the next channel estimate. If the delay becomes more than 16 symbol periods then the PRBS is resynchronised with the free running PRBS.

5.5.2 Output formatting ; Symbols from the rake receiver are eight bits wide. They are translated to three-bit wide symbols before being sent from the base station to the mobility manager. In the mobility man- ager the traffic channel is deinterleaved in software and both the traffic and control channels are decoded using halfrate Viterbi decoder devices. The thresholds for eight to three bit translation are under software con- trol.

5.5.3 Power control channel: Power control chan- nel is a forward link channel used to send power con- trol instructions to the mobile station. The instructions are binary, either ‘turn power up’ or ‘turn power down’. This data is generated in the base station receiver, by forming an estimate of the signal-to-noise ratio after the rake receiver and comparing it with a threshold. The threshold is under software control. The signal-to-noise ratio estimation uses the eight-bit sym- bols output by the rake and the current channel esti- mate from the peak searcher.

6 Performance testing

The reverse link is not designed to stand alone, but depends on the rest of the system for timing, PRBS generator set up information and carrier frequency recovery. However, these things may be simulated to test the hardware.

For the purpose of testing, a multipath channel simu- lator was used. It is a set of reels of coaxial cable of different lengths, with power splitters and combiners at either end, and with manually controllable gains. There are eight paths, seven of which have fixed delays between 15 and lOOOns relative to the first. One of the paths may be mixed with a low-frequency signal to simulate fast fading or a frequency offset.

Two sets of tests are reported here. First, the initial tesing, before the mobility manager was operational, measuring raw BERs at 128kbith for the reverse link under various simulated channel conditions. The sec- ond set, including mobility manager and the forward link, show the performance of the power control loop. During these tests the power control channel (PCC) on the forward link was not transmitted through the chan- nel simulator but simply using a coaxial connection.

6. I In these tests, the 70 and lOMHz references were pro- duced by frequency synthesisers. Also the 24.576MHz clock was produced from a clock oscillator module and a synchronisation ‘cheat-wire’ was run from mobile sta-

lnital reverse link BER testing

346 IEE Proc.-Commun., Vol. 144, No. 5, October 1997

tion to base station to ensure PRBSs were sufficiently aligned for the reduced search acquisition algorithm to operate. Both PRBS generators were put into the same state and then started simultaneously.

q... \

\ \

'., \ \ I I I

0 2 4 5 8 10 12 14 16 18 e:; t imated Eb/N, ,dB

Bit-error ratios measured using multipath channel simulator

(2) two equal paths

(4) single path (150Hz Doppler) (5) Doppler N = 32 ( 6 ) static path N = 32

Fig. 8 ___ (1) single static path . . . . . . . . . . _ _ _ _ (3 ) three equal paths

-~ (7) ideal coherent reception

Fig. 8 shows the measured BERs, the parameters of the loci are summarised in Table 2. These are raw BERs at 128 kbit/s, bypassing the coding and interleav- ing. The mobility martager was not available at the time of these tests so BI3R measurements which include the error control coding are not included.

Table 2: BER loci of Fig. 8

Number Averacing Doppler, Locus Note of paths period, ms Hz

1 1 0.5 0 AWGN channel

2 2 0.5 0 AWGN channel

3 3 0.5 0 AWGN channel

4 1 0.5 150 Static amplitude

5 1 0.25 150 Static amplitude

6 1 0.25 0 AWGN channel 7 1 - 0 AWGN channel

The different curves c n the graph represent different simulated channels and different averaging periods in the rake receiver channel estimation loop. Two periods are considered, 0.5 and 0.25ms, which correspond to averaging 64 and 32 channel filter outputs, respectively. Some of the curves have a limited range. This is because of limitations in the dynamic ranges of the var- ious paths in the chanrel simulator. Equal amplitude paths are used, which provides a worst-case scenario.

The system performs best with the single static path channel, as expected. There is an implementation loss (relative to the theoretical performance of a perfect coherent receiver on an AWGN channel, also shown on the graph) of between 1 and 2dB. This implementa- tion loss is slightly worse for high BERs than for low ones, being around 1.5dB at a BER of a possible operating point for the coded system.

The BER over a static two-path channel is only slightly worse than for a single-path channel. This proves the rake receiver to be giving a multipath gain.

IEE Proc -Commun, Vol 144, No 5, October 1997

Without the rake a degradation of 3dB would be inevi- table. A further and more severe degradation is appar- ent when the channel moves to three static paths. The degradation of about 2.5dB is still significantly less than the 4.7dB minimum that would occur without diversity combining.

When a 150Hz frequency offset between mobile and base station is included [Note 21, the performance is severely degraded. This is because the channel estima- tion loop is too slow to track the changing carrier phase accurately. There is however no cycle slipping and no irreducible BER. A degradation of between 3 and 6dB is suffered. To overcome this problem the averaging period in the tracking loop may be reduced. With a faster loop the performance of the system with a frequency offset is much improved. The loss (relative to the static channels) is only around IdB in the area of interest. The faster loop does however degrade the quality of the carrier phase estimate for a static chan- nel. To assess the significance of this effect a final curve is provided, for a single static path channel with the faster tracking loop. This curve shows that no discerna- ble BER degradation occurs, compared with the slower

To estimate the EbINo it was necessary to record the channel estimates produced by the channel averager. These estimates are stored in first-in first-out memories on the PCB and may be recovered by a PC with a dig- ital U 0 card. The channel estimates permit the calcula- tion of the mean correlation amplitude for each path in the channel. The square of the correlation amplitude is proportional to the received power from that path. The total received power is simply the sum of the received powers in each path because the path delays are sepa- rated by more than the chip period and so the signals from the paths appear statistically independent. The total received signal power is a constant, thanks to the AGC loop before the analogue-to-digital conversion, and the noise power is simply the remainder after the subtraction of the signal power.

The EbINo estimation will not be accurate when it becomes large, especially with few paths in the channel. This is because the AGC loop does not use true RMS detection but works simply on mean amplitude. There- fore for the total received power to be as expected the received signal must be gaussian in nature. In other words the signal must be buried in the noise. The link described here has l8dB of processing gain so the sig- nal will be sufficiently buried for nearly all the EbINo range in Fig. 8.

6.2 Testing of closed-loop power control Accurate power control is of crucial importance in CDMA communications systems to alleviate the near/ far problem and to prevent excessive noise loading by other users [6, 71. These results (Figs. 9 and 10) show the performance at varying rates (250Hz to 4kHz) for a single user and of course show a slight implementa- tion loss (of less than 0.5dB). The transmitter power control resolution of IdB accounts for this loss. To see the advantage of accurate power control requires testing in a multiple user scenario. The calculation of Eb/No during this second set of tests is identical to the manner of calculation during the first Set of tests as described above.

loop.

Note 2: This 150Hz Doppler corresponds to travelling at 94kmih at the carrier frequency.

347

10-6 0 2 I, 6 8 10 12 14 16

es t tmated Eb/No,dB Fig.9 power control ( N = 32) __ no power control

4 kHz 1 kHz 250Hz

Reverse link BER measurntents with a single static path and

- _ _ -

es t imated Eb/N,,dB Fig. 10 control ( N = 32)

Uplink BER measurements with single Doppler path and power

~ no power control

. . . . . . . . . . 4 kHz - _ _ - 1 kHz

Fig. 9 shows the result of power control with a single static path and similarly Fig. 10 the result for a single path with Doppler. For these results the variation of EblNo was achieved by varying the PCC threshold in the BS. This threshold defines the post-detection signal to noise ratio which the power control loop attempts to maintain. The PCC on the forward link transmits 1 bit adjustment information (at the rates indicated) which results in the MS transmitter adjusting the power up or down in 1dB steps. The reason for the restricted range of the BER curves is that the SNR estimation algo- rithm is only designed to work for a certain range, where the BER is of interest. When higher SNRs are requested from the power control loop the performance is unpredictable. These graphs show that the power control is working both with a static path and with the 150Hz Doppler path. It can be seen that the perform- ance at the different power control rates is very similar and as expected the lkHz rate is adequate with the 150Hz Doppler path.

348

7 Summary and conclusions

This paper has described the engineering of a spread- spectrum transmitter and rake receiver. The radio link is destined for inclusion in a mobile radio demonstra- tion system. It will support mobile access for basic-rate ISDN terminals in outdoor (macrocell) environments. The signal-processing hardware is implemented com- pletely in hard-wired logic rather than using general- purpose DSP microprocessors. PLDs have been used extensively to reduce the required PCB count and power consumption. A comprehensive set of assess- ment tool interfaces are built into the link hardware. These provide access to all the important intermediate signals and also permit injection of simulated interfer- ence.

Initial performance testing using a multipath channel simulator shows that the implementation loss of the link is less than 2dB relative to a perfect coherent detector. Testing of the closed-loop power control is shown to introduce a small implementation loss of less than 0.5dB. Results and the design details for the for- ward link are contained in [8]. Also complete system details and comprehensive results are contained in the final report of the Link-CDMA project [l].

8 Acknowledgment

The work described here was carried out at the Univer- sity of Bradford and was supported by the Engineering and Physical Sciences Research Council grant GRI H26307 as part of the DTIiEPSRC LINK Personal Communications project PC019. The results contained in Figs. 9 and 10 include use of a forward link which was the work of the Bristol University consortium part- ners, particularly Dr S. Swales who was also involved during experimentation.

References

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