I680 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 7. JULY 1992

Enhanced Electron Trapping Near Channel Edges in NMOS Transistors

Artur Balasinski and Tso-Ping Ma, Senior Member, IEEE

Abstract-Charge trapping in the gate oxide of NMOS tran- sistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement meth- ods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 pm, and is independent of the channel length. Possible reasons for the observed phenomena are discussed.

I. INTRODUCTION T IS WELL KNOWN that gate oxide contains electron I traps, and electron trapping in the oxide overlapping

the drain junction has been observed after channel hot- electron (CHE) injection [ 11. The preferential electron trapping near the drain junction in this case arises from the localized hot carrier distribution due to the high field in that vicinity. The question to be answered is whether the gate oxide near the source/drain junctions is inher- ently more trappy than the oxide over the rest of the chan- nel, such that preferential trapping takes place even with uniform hot-electron injection.

For the purpose of this discussion, the gate oxide may be roughly divided into three sections as illustrated in Fig. 1: 1) over the bulk of the channel, 2) over the source/ drain metallurgical junctions, and 3 ) over the source/drain diffusion. Intuitively, one might expect some differences in the trapping properties of the gate oxide among these three regions. In addition, charge trapped in each region should cause a different effect on the transistor parame- ters. As the device scaling trend continues, the trapping near the channel edges is expected to be of increasing concern.

The purpose of this work is to investigate the electron trapping properties in these three regions, especially in the vicinity of the source/drain junctions.

11. PRINICIPLES OF MEASUREMENT TECHNIQUES The principle of our experiment is based on the fact that

the Fowler-Nordheim (FN) electron injection current de- creases as electrons are trapped in the oxide. In the case

Manuscript received July 26, 1991; revised November 30, 1991. This work was supported under research grants from NRL and SRC. The review of this paper was arranged by Associate Editor K . Shenai.

The authors are with the Center for Microelectronic Materials and Struc- tures and the Department of Electrical Engineering, Yale University, New Haven, CT 06520-2157.

IEEE Log Number 9200389.

when a significant amount of electrons are preferentially trapped near the channel edges, the FN current near such edges will be essentially blocked, causing the current to flow through a reduced area away from such edges. At the same time, the trapped electrons will cause an increase in the channel resistance for an NMOS transistor. As will be described in more detail below, by monitoring the changes in the FN injection current and channel resistance as a function of time during FN injection for a set of devices having a range of channel lengths, one may reveal the trapping properties near the channel edges. Charge pump- ing currents and gated diode currents are also measured to verify the results.

A. Time-Dependent FN Injection Current as a Function of Gate Length

Consider the geometry depicted in Fig. 1. Suppose ini- tially a uniform FN electron current flux is flowing from the gate to the substrate, with the magnitude of this cur- rent expressed as

(1)

where J,.] is the FN current density, Wg and LR are the width and length of the gate.

The FN current density is a strong function of the oxide field E,,

1. . = J . .W L '"I 1"J g g

.Iinj = k& tx exp (- k' /&ox) (2)

where k and k' are constants in terms of effective mass and barrier heights [2].

Now, suppose there is significant electron trapping in some region (such as the channel ends) after some period of FN injection. This inhibits subsequent electron injec- tion in that region, and causes a drastic local reduction of the FN current flux. In other words, the FN current is practically shut off in the region where significant electron trapping occurs. As a result, the FN current now only flows through a reduced area according to

( 3 ) where AL, is the effective decrease in the gate length for FN injection. This situation is illustrated in Fig. l(b).

In the case the channel length Lch is specified instead of the gate length L,, ( 3 ) can be rewritten as

linj = JinjWg(Lg - AL,)

Iinj = Jinjwg<Lch + Lop - A&) (4)

0018-9383/92$03.00 0 1992 IEEE

BALASINSKI A N D MA: ELECTRON TRAPPING NEAR CHANNEL EDGES IN NMOS TRANSISTORS 1681

’ .eate /I/////

3 2 f 1 ) 2 F

drain

1 L Channel : ; Drain

or Source

Fig. 1. (a) A schematic cross section of MOSFET showing three gate oxide regions. (b) “Bottleneck” effect for current injec- tion due to electron trapping, which reduces the effective gate length for injection (direction of electron flow is indicated). (c) Channel resistance increases due to electron trapping in the gate oxide overlap region, which can be modeled as an increase of the effective channel length. (d) Threshold and flatband voltage distributions along the channel are changed by local electron trapping, which changes the charge pumping current.

where Lop is the gate/drain (source) overlap length (L, = Lch + Lop), and is independent of the channel length.

From (4), if one plots the Iinj versus Lch relationship for a set of devices with a range of Lch’S, a straight line is expected if AL, is independent of Lch (which is indeed the case experimentally), and the intersect of this line on the Lch axis gives the quantity -(Lop - AL,). Since Lo! is fixed, it can be subtracted to obtain ALR, or the region under the gate where significant electron trapping has oc- curred.

It should be noted that the above analysis can be readily applied to the more realistic case where electron trapping occurs throughout the gate oxide area, but there is one region which traps much more electrons. In such a case, the quantity A L, represents the region where excessive electron trapping has taken place.

It will be shown that this A L, changes with time during FN injection, suggesting that the region where excessive electron trapping takes place is spreading as injection con- tinues.

B. Channel Resistance After Electron Trapping

ear region is The channel resistance of a NMOS transistor in the lin-

where R is the channel resistance, G the channel con- ductance, Lch and w,h the effective channel length and width, respectively, p,, the effective channel electron mo- bility, Cox the oxide capacitance per unit area, V, the gate voltage, and VT the threshold voltage.

Equation (5) shows that R is a linear function of Lch. When there is uniform electron trapping throughout the gate oxide, V , increases, and the slope of the R versus Lch plot may increase due to the reduced p,,. However, when

there is substantial electron trapping in the oxide over the source/drain junctions such that the n+ diffusion is de- pleted of electrons, an increase of the effective channel length will be observed. This situation is illustrated in Fig.

As a result, the equation for channel resistance be- 1 (c).

comes

where A Lch is the incremental effective channel length due to electron trapping. Note that p,, and V , may have changed from their pre-injection values, but their changes have no effect on our derivations.

Now if one plots the R versus Lch curve for a set of devices with a range of Lch’S, the intercept of the extrap- olated straight line on the Lch axis gives AI,,,,, or the re- gion where excessive electron trapping has taken place as sensed by the channel resistance measurement.

Note that (6) also indicates that the slope of this straight line is inversely proportional to the effective channel mo- bility p,,. Therefore, information on mobility degradation can also be obtained by such measurements.

C. Changes of Charge Pumping Current After Local Electron Trapping

Similarly to the channel resistance, the charge pumping current Icp is also directly proportional to the effective channel length, and can be expressed as

where J,, the current density, is proportional to the in- terface trap density, L, and Wcp are the length and width of that part of the channel where interface traps participate in the charge pumping process. Note that L, and Wc.p are in general different from L,h and Wch, but we will show

I682 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 39. NO. 7, JULY 1992

that changes in Lch and L, due to electron trapping are closely correlated.

So far we have assumed that the amplitude of the charge pumping pulse is sufficiently large so that the surface po- tential throughout the channel could change from accu- mulation to inversion and back to accumulation in one cycle of the pulse. If significant electron trapping occurs in one part of the channel (say near the source/drain junc- tion), then the corresponding local increase in the thresh- old voltage could cause that part of the channel never to be inverted during the charge pumping measurement. As a result, that part of the channel will not contribute to the charge pumping current. Suppose that part of the channel has an effective length AL,, then the effective channel length contributing to the charge pumping current is L, - ALcp, as illustrated in Fig. l(d). In such a case, (7) becomes

(8)

where A L , is the decremental channel length for charge pumping. It should be noted that J , may have changed after each injection due to the increase in the interface trap density, but it does not affect the outcome of this method.

Again, if one now plots the IC,, versus L, curve for a set of devices with a range of L,’s, the intercept of the extrapolated straight line on the L , axis yields ALcp, or the region of the channel where the charge pumping cur- rent has been turned off due to substantial localized elec- tron trapping.

Icp = Jcp(Lcp - ALcp)Wcp

D. Gate-Controlled Diode Measurements

The gate-controlled diode measurements can provide information about the trapped oxide charge in the channel region and directly over the drain/source junction, as de- scribed below.

In the conventional gate-controlled diode measure- ment, as illustrated in Fig. 2(a) [4], the gate voltage sweeps the channel through weak accumulation, deple- tion, and inversion, and the reverse junction diode current plotted as a function of gate voltage will show a step-up increase at VG (near flatband), and a step-down decrease at V,, (near inversion). The basic physics of this phenom- enon has to do with the change in generation volume (due to the extension of the surface depletion region along the channel) as the gate voltage is changed, and this has been well documented [4].

Now, if some charge is trapped in the gated oxide re- gion, then a rigid shift of the curve along VG will occur according to

AQot = -Cox AVG (9) where Q,, is the trapped oxide charge density, and CO, is the oxide capacitance per unit area. Therefore, such a measurement can provide information about the oxide charge in the channel.

To probe the oxide charge trapped directly over the drain (source) diffusion, an extension of this conventional

Gate Voltage vG (a)

0 20

c 0

U

- 1o 0.15

E 0 1 0

- - 1

> 0.05

0 0 0.1 0 2 0.3 0 4 0 5

X (microns)

(b) Fig. 2. Schematic illustration of the gate-controlled reverse diode current. (a) When the gate is biased from weak accumulation, through depletion, to inversion, the reverse diode current is mostly due to thermal generation in the depletion region. Note the step-up transition near flatband and the step-down transition near inversion (after [4]). (b) When the gate is biased to strong accumulation, the dominant reverse diode current is band-to-band tunneling inside the drain (along A - A ’ ) , as illustrated by 2D simulation results (after [ 5 ] ) .

gate-controlled diode measurement into strong accumu- lation can be used. The basic physics of the reverse diode current when the channel is biased into strong accumula- tion has been described elsewhere [5], and is briefly sum- marized below.

As illustrated in Fig. 2(b) by PISCES simulation, when the channel region is biased into strong accumulation, the drain (source) region near the metallurgical junction un- der the gate is depleted. Due to the high dopant concen- tration, this depletion layer is very narrow, and band-to- band tunneling current will flow through this depletion layer under a reverse-junction bias. For a given reverse- junction bias, this tunneling current increases as the de- gree of accumulation in the channel region increases, due to the narrowing of the tunneling barrier. Thus for an NMOS transistor, the junction tunneling current Ij will increase as the VG becomes more negative.

Here, trapping of oxide charge in the channel region will not affect the I, versus VG curve, since direct tunnel- ing is unlikely underneath the gate oxide in the channel region. However, the trapping of oxide charge directly above the drain (source) region will cause a rigid shift of the Ij versus VG curve along the VG axis according to (9).

BALASINSKI AND MA: ELECTRON TRAPPING NEAR CHANNEL EDGES IN NMOS TRANSISTORS

Thus in this regime the gate-controlled diode measure- ment can provide information about the oxide trapped charge directly above the drain (source) region.

111. EXPERIMENTAL DETAILS A large number of NMOS transistors with channel

lengths from 0.8 to 15 pm, width of 25 pm, gate oxide thickness of 25 nm, and phosphorus-doped poly-Si gate electrode, were used in this study. Constant voltage FN injection at an oxide field of approximately -9 MV/cm was performed with a negative gate voltage and all other terminals grounded. An HP4145 parameter analyzer was used to supply the voltage and monitor the injection cur- rent as a function of injection time.

After the FN injection for a predetermined period of time (ranging from 0 .33 to 3300 s), the transistor dc char- acteristics were measured, and the channel resistance R for each sample was determined at V,, = 50 mV, V,, = V, + 1 V. Standard charge pumping characteristics were measured using triangular gate pumping pulses with an amplitude of 2.5 V and a frequency of 80 kHz. Gate-con- trolled diode measurements were performed with a fixed reverse drain (or source) junction voltage of 3 V while sweeping the gate voltage from depletion to strong accu- mulation.

IV. RESULTS AND DISCUSSION We now present evidence collected by the various mea-

surements described above to show that there is prefer- ential electron trapping near the gate edges during FN in- jection.

A . FN Injection Current as a Function of Time Fig. 3 shows the time-dependent injection current for

several transistors with different channel lengths. One can see that the current is roughly proportional to the channel length, as expected. The current decay is due to electron trapping in the oxide. Upon closer examination of these decay curves, however, we found that the rate of decay is a function of the channel length, especially for short in- jection times.

To investigate this channel-length dependence further, we plotted the injection current as a function of channel length for five different injection times, as shown in Fig. 4. The data indicate that, after an injection time of 3 .3 s, the injection current is directly proportional to the channel length and the experimental points fit almost a perfect straight line. For the 0.33-s case, the data points are more scattered, due largely to the difficulty in controlling the transient and precise timing in such a short period. There- fore, in this case the straight line is formed by a least squares fit.

Note that the intercepts of the straight lines do not go through the origin on the X axis-being to the left of the origin for short injection times and gradually moving to the right as injection time increases.

/ 7 -

I683

Fig. 3 . Time dependence of constant-voltage FN injection current for four transistors with different channel lengths.

Channel Length 1. [ p m ] Fig. 4. Channel lengt:] dependence of injection current for five different

injection times.

The fact that we observed straight lines with nonzero intercepts is consistent with the local electron trapping model described in Section 11-A. Based on (4), this non- zero intercept should give rise to -(Lop. - AL,) , where Lop is the gate overlap length, and A L, is the region that has excessive electron trapping.

Fig. 5 shows this intercept plotted as a function of the injection time. One can see that, due to the continuous increase of AL,, the curve decreases with injection time. This is a clear indication that the region where excessive electron trapping occurs ( A Ls) is spreading with injection time. The initial positive value corresponds roughly to Lop (AL, is relatively small for such a short injection time). As the current injection and electron trapping proceed, the curve decreases past zero and becomes negative after a few tens of seconds, indicating that A L, has exceeded the gate overlap length. Finally, the curve saturates after a long injection time.

Although the A L, obtained from this procedure could correspond to a trapping region anywhere along the chan- nel, we believe this excessive trapping region is near the gate edges based on the following argument.

From (4), such data as the ones presented in Fig. 4 would only form straight lines if A L, were independent of L,, (we already know that Lop is independent of L J . Therefore, if the localized oxide trapping region is some- where in the bulk of the channel, this region must be dif- ferent from the rest of the channel and independent of the channel length. We are not able to identify such a region in the bulk of the channel based on the device layout and

I684 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 7, JULY 1992

1 7 ~

c-T-;.c--2, 5 L , \v-;5,, ! >, (Subs t ra te Grounded) - ' 2 - Drain/Sourcc Groundcd

I L-- 1 1 ~ -,x--A

1 0 0 IO' 10 10 Inlectlon 'rlmr t,,, I s ]

Fig. S. A & (the region where current injection is shut off) increases with injection time due to local electron trapping. The trend is similar whether drain/source terminals are grounded to substrate or left floating during FN injection.

processing steps. On the other hand, all devices have the same gate overlap, same gate width, and identical source/ drain dopant profiles, independent of the channel length. Therefore, we conclude that the excessive electron trap- ping region must be in the oxide near the gate edges.

Since A L, exceeds the gate overlap length after a long injection time, we believe that this method reveals the preferential electron trapping in both regions 2 and 3 de- picted in Fig. l(a).

One minor point may be worth pointing out here. The data in Fig. 4 indicate that the slope of the line is changing with injection time. From (4), the slope is proportional to the injection current density Ji,. Therefore, the change in the slope is due to the change in the injection efficiency as influenced by the oxide trapped charge throughout the gate oxide. Positive oxide charge will increase the slope while negative oxide charge will decrease the slope.

B. Changes in Channel Resistance When there is significant local electron trapping, the

channel resistance could increase according to Section II- B.

Fig. 6 shows the channel resistance as a function of channel length measured at several time intervals after in- jection. Since the threshold voltage changes with electron trapping, for each measurement the gate voltage is ad- justed so that VG - V , = 1 V.

The data indicate that the channel resistance increases with injection time for each device, and for a given injec- tion time the data points fit a straight line very well. Again, the intercepts deviate from the origin, and depend on the injection time.

From (6), the intercept of the line for a given injection time corresponds to an incremental channel length A Lch due to the excessive electron trapping near the channel edges. The fact that the data points for each injection time fit a straight line so well indicates that ALch is indepen- dent of the channel length. This is consistent with the con- clusion drawn from the results discussed previously. This method thus reveals the excessive electron trapping in re- gion 2 (and maybe part of region 3 ) depicted in Fig. l(a).

( tlanllc 1 1 c~lleth L [ / i l I l ]

Fig 6 Channel resistance (meawred at V(, - V , = I V , Vo = S O mV) as a function of chdnnel length, measured after several different injection times

There may be a question as to whether the trapped elec- tron density in region 2 is sufficiently high such that this region is essentially turned off until the gate voltage reaches a value similar to V , of the channel region. Nu- merical simulations in [ 3 ] showed that, for our devices before FN injection, the threshold voltage above drain/ source is of the order of - 3 V, whereas VT in the channel region is less than 1 V. Therefore, the device requires at least 4 V of electron trapping-induced gate voltage shift in region 2 to turn off the gate overlapping regions. Our data obtained from the gated-diode measurement (see, e.g., Fig. 9) show indeed that the shift due to electron trapping is more than 4 V, in agreement with the above analysis.

In addition, the slope of the lines shown in Fig. 6 is changing as the injection and electron trapping proceed. According to (6), the change in slope can be attributed to the change in p,,, most likely due to the increase in the density of interface traps.

C. Changes in Charge Pumping Current The local electron trapping near the channel edges

should also affect the charge pumping current, as de- scribed in Section 11-C.

In Fig. 7 we present peak values of charge pumping current Zc,, plotted against channel length for five injection times. Again we can fit the data nicely into straight lines, with each having a nonzero intercept (the values of the intercepts range from 0.1 to 0.6 pm, but are difficult to visualize on Fig. 7 due to the compressed scale). Accord- ing to (8), this intercept corresponds to a decremental channel length for charge pumping A L, due to localized heavy electron trapping. The well-behaved straight lines again indicate that A L, is independent of channel length, which is consistent with preferential trapping near the channel edges.

The increase in slope with injection time is due to the increase in the charge pumping current density Jcp due to the increase in the density of interface traps.

Fig. 8 compares the results obtained from the channel resistance measurement to those obtained from the charge pumping measurement. The close correlation between the

BALASINSKI AND MA: ELECTRON TRAPPING NEAR CHANNEL EDGES IN NMOS TRANSISTORS

Channel Length L [pm]

Fig. 7 . Peak charge pumping current as a function of channel length, mea- sured after several different injection times.

5 : ' 1

L w ' * ~ ~ From Charge Pumping

Fig. 8 . Change in the effective channel length as a function of injection time as determined from channel resistance and charge pumping current measurements.

two curves suggests that they have the same origin; i.e., they both arise from the excessive electron trapping in region 2 (and maybe also part of region 3) as depicted in Fig. l(a).

D. Gate-Controlled Diode Measurements Since the oxide trapped charge near the gate edges

should cause a shift in the gate-controlled diode Z-V char- acteristics, as described in Section II-D, we also per- formed such measurements to shed more light on the sub- ject.

According to the discussion presented in Section II-D, the reverse junction diode current at a given junction bias is a function of the gate voltage. When the gate is biased in depletion, the gate-controlled reverse-junction current is due to the generation current throughout the depletion region under the gate, and is affected by the oxide charge trapped in the channel region. When the gate is biased in strong accumulation, the reverse junction current is due to band-to-band tunneling inside the draidsource, and is affected by the oxide charge trapped directly over the draidsource.

Fig. 9 shows the gate-controlled reverse diode current as a function of gate voltage for a device before and after FN injection. The regions corresponding to the generation current regime and the tunneling current regime are marked on the graph.

1685

Fig. 9. Gate-controlled reverse diode current as a function of gate voltage biased from strong accumulation to depletion before and after FN current injection. Band-to-band tunneling current inside draidsource dominates in strong accumulation, while thermal generation current dominates in deple- tion.

First, let us examine the tunneling current regime (strong accumulation). One can see that the major effect of the FN injection is to shift the diode tunneling curve toward more positive VG. This indicates substantial local trapping of electrons in the oxide directly above the drain. From the shift in the gate voltage and according to (9), the local density of trapped electrons is approximately 5 X 10l2/cm2. Such a large value is consistent with the changes we observed in the injection current, channel re- sistance, and charge pumping current measurements.

Now, let us look at the generation current regime. In this regime, the major effect of the FN injection is to shift the curve toward more negative VG. This indicates posi- tive oxide charge generated in the channel region, in con- trast to the electron trapping near the edges. In fact, our standard MOSFET threshold voltage measurement ob- tained by extrapolating the ZDs versus VG in the linear re- gion shows that the channel threshold voltage indeed shifts negatively after FN injection due to the generated positive oxide charge in the channel region. The generation of positive oxide charge due to high-field FN injection has frequently been observed (e.g., [ 6 ] ) , and therefore is not surprising. We believe that the positive oxide charge gen- erated by FN injection in our experiments is uniformly distributed in the bulk of the channel, and therefore does not affect our analyses based on (4), ( 6 ) , and (8).

Although we have no experimental evidence to show why there is enhanced electron trapping near the channel edges, we suspect it may be due to the source/drain do- pant impurities which may be introduced into the overlap- ping gate oxide during post-implant high-temperature steps. It has been shown that group V impurities in the oxide are associated with electron traps [7], and the out- diffusion of such impurities into the gate oxide could be responsible for the enhanced electron trapping. Another possibility is the higher gate-induced strain near the gate edges, which has been shown to affect the capture cross sections of electron traps [8].

V. SUMMARY We have used several different methods to demonstrate

that there is enhanced electron trapping near the channel

I686 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39. NO. 7, JULY 1992

edges of NMOS transistors. The results and conclusions obtained from all these methods are consistent with one another. This edge effect could be as large as 0.5 pm, which is especially troublesome for small-geometry MOSFET’s.

ACKNOWLEDGMENT The authors wish to thank N. Saks from NRL for sup-

plying the test devices.

REFERENCES [ I ] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Con-

sistent model for the hot-camer degradation in n-channel and p-chan-

161

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ne1 MOSFET’s,” IEEE Trans. Eleirron Devices, vol. 35, no. ‘12, pp. 2194-2209, 1988. M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO,,” J . Appl. Phys., vol. 40, no. 1, pp. 278-283, 1969. W. Chen, A. Balasinski, and T . P. Ma, “Lateral distribution of radia- tion-induced damage in MOSFET’s.” f E E E Trans. Nucl. Sri., vol. 38. no. 6 , pp. 1124-1129, 1991. A . S. Grove and D. J . Fitzgerald. “Surface effects on P-N junctions- characteristics of surface space-charge regions under non-equilibrium conditions,“ Solid-Stare Electroiz., vol. 9 , pp. 783-805, 1966. A. Acovic, M. Dutoit, and M. Ilegems, “Characterization of hot-elec- tron-stressed MOSFET’s by low-temperature measurements of the drain tunnel current,” IEEE Trans. Electron Devices, vol. 37, no. 6 , pp. 1467-1476, 1990. T . Hosoi, M. Akizawa, and S . Matsumoto, “The effect of Fowler- Nordheim tunneling current on thin SiO, metal-oxide-semiconductor capacitors,” J . Appl. Phys., vol. 57, no. 6, pp. 2072-2076, 1985. R. F. DeKeersmaecker, D. J . DiMaria, and S . T. Pantelides, “Pho- todepopulation of electrons trapped in SiO, on sites related to As and P implantation,” in S . T. Pantelides, Ed., The Physics o f S i 0 , and Its Interfaces. New York: Pergamon, 1978, pp. 189-194. T. B. Hook and T. P. Ma, “Electron trapping during high-field tun- neling injection in metal-oxide-silicon capacitors: The effect of gate- induced strain,” J . Appl. Phys., vol. 62, no. 3, pp. 931-938, 1987.

1987, he spent six months at Scientific-Production Semiconductor Center in Warsaw, participating in MOS device fabrication and measurements. In 1989, he joined Department of Electrical Engineering, Yale University, New Haven, CT, to continue work on MOS device characterization and processing. He contributed to two book chapters, and about forty publi- cations, on radiation effects, process-induced defects, thin dielectric prop- erties, intel-face physics, and new measurement methods. In 1987, he re- ceived an award for his research accomplishments from the Rector (President) O F the Warsaw University of Technology.

Dr. Balasinski is a member of the Electrochemical Society.

Tso-Ping Ma (S’72-M’74-SM’83) was bom in Lan-cho. China, on November 13, 1945. He re- ceived the B.S. degree in electrical engineering in 1968 from the National Taiwan University, Re- public of China, the M.S. degree in 1972, and the Ph.D. degree in 1974, both from Yale University, New Haven, CT.

From 1969 to 1974, he was a graduate student and research assistant at Yale University where he worked on MOS tunnel junctions. From 1974 to 1977 he was employed by IBM’s East Fishkill Fa-

cility, where he worked on exploratory MOS devices fabricated by elec- tron-beam lithography, and invented and developed the RF plasma an- nealing technique. In 1976 he took a leave of absence from IBM, and joined the Department of Engineering and Applied Science at Yale University as a Visiting Lecturer. In 1977 he joined Yale faculty as an Assistant Profes- sor, was promoted to Associate Professor in 1980, and since 1985 has been a Professor in the Department of Electrical Engineering at Yale University. He has served on many committees in the university, was Acting Chairman of the Department in 1988, and is currently the Chairman. His research and teaching have focused on semiconductors, MOS interface physics, ionizing radiation and hot electron effects, and microelectronicioptoelectronic ma- terials and processes. He received the Harding Bliss Award at Yale Uni- versity in 1975, was elected a GE Whitney Symposium Lecturer in 1985, and received a Connecticut Yankee Ingenuity Award in 1991. He was the Arrangement Chairman (1986), the Technical Program Chairman (1987), and the General Chairman (1988) of the IEEE Semiconductor Interface

Artur Balasinski was bom in Warsaw, Poland, Specialists Conference, and served on the program committees and as ses- on June 30, 1957 He received the M S degree sion chairman in numerous other conferences, including IEEEIDRC, IEEEi for work on MOS solar cells in 1980, and the NSREC, ECS, and Intemational Symposium on-VLSI He is a patent Ph D. degree in 1987 for a study on radiation ef- holder, co-editor of a book, and contributed to several book chapters and fects in MOS structures, both from the Warsaw over 100 publications University of Technology, Institute of Microelec- Dr. Ma was the Vice President (1986-1987) and President (1987-1988) tronics and Optoelectronics of the Yale Chapter of the Sigma Xi Society He has served on the Board

He worked at the Warsaw University of Tech- of Directors of the New Haven Chinese School since 1981, and was the nology, as a staff member (1985-1986), research President of the New Haven Chapter of the Organization of Chinese Amer- assistant (1986-1988), and assistant professor icans for 1989 and 1990 He is a member of APS, ECS, MRS, Sigma Xi, (1988-1989) at the Faculty of Electronics In and YSEA