eGaN® FET DATASHEET EPC2022
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EFFICIENT POWER CONVERSIONG
D
SHAL
EPC2022 – Enhancement Mode Power Transistor
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 100V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120
ID
Continuous (TA = 25°C, RθJA = 2.5°C/W) 90A
Pulsed (25°C, TPULSE = 300 µs) 390
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJ Operating Temperature -40 to 150°C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 0.4
°C/W RθJB Thermal Resistance, Junction-to-Board 1.1
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.9 mA 100 V
IDSS Drain-Source Leakage VGS = 80 V, VDS = 0 V 0.1 0.7 mA
IGSSGate-to-Source Forward Leakage VGS = 5 V 1 9 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.7 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 13 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 2.4 3.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V
VDS , 100 VRDS(on) , 3.2 mΩID , 90 A
EPC2022 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die Size: 6.05 mm x 2.3 mm
• High Speed DC-DC Conversion• Motor Drive• Industrial Automation • Synchronous Rectification • Inrush Protection • Class-D Audio
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET
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EPC2022
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VDS = 50 V, VGS = 0 V
1400 1690
pF
COSS Output Capacitance 840 1260
CRSS Reverse Transfer Capacitance 7
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 50 V, VGS = 0 V
1090
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 1410
RG Gate Resistance 0.3 Ω
QG Total Gate Charge VDS = 50 V, VGS = 5 V, ID = 25 A 13 16
nC
QGS Gate-to-Source Charge
VDS = 50 V, ID = 25 A
3.4
QGD Gate-to-Drain Charge 2.4
QG(TH) Gate Charge at Threshold 2.1
QOSS Output Charge VDS = 50 V, VGS = 0 V 71 107
QRR Source-Drain Recovery Charge 0All measurements were done with substrate connected to source.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
300
200
100
00 0.5 1.0 1.5 2.0 2.5 3.0
I D –
Dra
in Cu
rrent
(A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V
I D –
Dra
in Cu
rrent
(A)
VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
300
200
100
0
25˚C125˚C
VDS = 3 V
25˚C125˚C
VDS = 3 V
8
6
4
2
02.5 3.0 3.5 4.0 4.5 5.0
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 25 AID = 50 AID = 100 AID = 150 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
R DS(
on) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ
)
VGS – Gate-to-Source Voltage (V)
25˚C125˚C
VDS = 3 V
25˚C125˚C
ID = 25 A
8
6
4
2
0
eGaN® FET DATASHEET
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EPC2022
All measurements were done with substrate shortened to source.
Capa
citan
ce (p
F)
0 20 40 60 10080
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
2500
2000
1500
1000
500
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capa
citan
ce (p
F)
1000
100
10
10 20 40 60 10080
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Gate Charge
V GS
– Ga
te-to
-Sou
rce V
olta
ge (V
)
5
4
3
2
1
00 1510 5
QG – Gate Charge (nC)
ID = 25 AVDS = 50 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I SD –
Sour
ce-to
-Dra
in Cu
rrent
(A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
300
200
100
0
25˚C125˚C
VGS = 0 V
Figure 8: Normalized On-State Resistance vs. Temperature
Norm
alize
d On
-Sta
te R
esist
ance
RDS
(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.80 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 25 AVGS = 5 V
Figure 9: Normalized Threshold Voltage vs. Temperature
Norm
alize
d Th
resh
old
Volta
ge
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.600 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 13 mA
eGaN® FET DATASHEET
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EPC2022
Figure 12: Transient Thermal Response Curves
I G –
Gate
Curre
nt (m
A)
VGS – Gate-to-Source Voltage (V)
Figure 10: Gate Leakage Current60
50
40
30
20
10
00 1 2 3 4 5 6
25˚C125˚C
0.1
1
10
100
1000
0.1 1 10 100
I D – D
rain
Curre
nt (A
)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width 100 ms
10 ms 1 ms
100 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce
0.5
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
0.0001
0.5
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
0.2
tp, Rectangular Pulse Duration, seconds
Z θJC
, Nor
mal
ized T
herm
al Im
peda
nce
0.5
Junction-to-Case
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
TJ = Max Rated, TC = +25°C, Single Pulse
eGaN® FET DATASHEET
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EPC2022
2022 YYYY ZZZZ Die orientation dot
Gate Pad bump is under this corner
Part Number
Laser Marking
Part #Marking Line 1
Lot_Date CodeMarking Line 2
Lot_Date CodeMarking Line 3
EPC2022 2022 YYYY ZZZZ
DIE MARKINGS
DIE OUTLINESolder Bump View
Side View (685
)
Seating plane
(785
)
100 ±
20
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
A
f
d X30
B
gX4e
c
X30
X28
Pad 1 is Gate;Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29 are Source;Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source
DIM
Micrometers
MIN Nominal MAX
A 6020 6050 6080B 2270 2300 2330c 2047 2050 2053d 717 720 723e 210 225 240f 195 200 205g 400 400 400
2022YYYYZZZZ
TAPE AND REEL CONFIGURATION4 mm pitch, 12 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Dieorientationdot
Gatesolder bar isunder thiscorner
Die is placed into pocketsolder bar side down(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max a 12.00 11.70 12.30 b 1.75 1.65 1.85
c (note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6
EPC2022 (note 1)
eGaN® FET DATASHEET
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EPC2022
RECOMMENDEDLAND PATTERN (units in µm)
RECOMMENDEDSTENCIL DRAWING (units in µm)
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
6050
18070
0X3
0
2300
400
2030
X30
X28
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
6050
400X34
2300
1330
2050
720
200X35
R601 3 5 7 9 11 13 15 17 19 21 23 25 27 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Information subject to change without notice.
Revised August, 2019
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at https://www.epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Land pattern is solder mask definedSolder mask opening is 180 µmIt is recommended to have on-Cu trace PCB vias
Pad 1 is Gate;Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22, 25, 26, 29 are Source;Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain;
Pad 30 is Substrate.*
*Substrate pin should be connected to Source