- 1 -

Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution! Tina Tran, Altera Corporation Gary Pratt, Mentor Graphics Corporation Kazi Asaduzzaman, Altera Corporation Mei Luo, Altera Corporation Simar Maangat, Altera Corporation Toan Nguyen, Altera Corporation Sergey Shumarayev, Altera Corporation Kwong-Wen Wei, Altera Corporation

- 2 -

Abstract This paper describes the challenges of optimizing equalization performance for a 6G transceiver design used to satisfy a wide range of customer platform requirements. The transmitter includes a multi-tap FIR filter and a receiver that provides linear equalization circuitry. Both are required to provide programmable link equalization used to improve the signal quality of highly attenuated legacy back-planes. Choosing the correct TX and RX configurations from the millions of choices for modern SERDES interfaces can be difficult and time-consuming. This presentation introduces PELE (Pre-Emphasis and Equalization Link Estimator), a software design tool that provides the prediction of the PELE settings based on analytical analysis of the s-parameter model of the channel. How this analysis is integrated into a signal integrity (SI) tool to provide a starting point to verify and fine-tune the results will be examined. Authors Biography Tina Tran is the senior design manager at Altera Corporation. She is working in the design group responsible for the development of high-speed transceivers at Altera. She has been in the semiconductor industry for more than 15 years, including almost 10 years with Altera. She holds a BSEE from the University of California, Berkeley. Gary Pratt is the manager of high speed partnerships for Mentor Graphics Corporation's System Design division. He is a graduate of the University of Wisconsin at Madison, a member of IEEE, and a licensed professional engineer with 23 years experience in power electronics; control systems; digital image and signal processing; analog, digital and software design; and engineering management. Pratt has been an evangelist for emerging EDA technologies throughout his career. Kazi Asaduzzaman is a design engineer at Altera Corporation. Asaduzzaman holds a BS in EE from the University of California, Berkeley and a MS in EE from the University of Santa Clara. He has been with Altera over 10 years and is currently a member of the high-speed transceiver design group. Mei Luo is a design engineer at Altera Corporation. Luo holds a MS in EE from Purdue University. She has been with Altera for seven years and is a member of the high-speed transceiver design group working on the 1st generation of transceivers to the current generation (4th).

- 3 -

Simar Maangat is a design engineer at Altera Corporation. Mr. Maangat has around seven years of experience at Altera, mainly in analog design development. Mr. Maangat has worked on 3.125Gbps and 6.375Gbps SERDES in Altera’s Stratix GX and Stratix II GX product lines. Prior to joining Altera Corp., Mr. Maangat interned at Digital Equipment Corp. (DEC) in Palo Alto. He holds a B.S. degree in Electrical Engineering from UC Berkeley. Toan Nguyen is a design engineer at Altera Corporation. Nguyen holds a BS in EE from the University of California, Berkeley. He has been with Altera for eight years and is a member of the high-speed transceiver design group working on the 2rd generation of Altera’s high-speed transceiver to the current generation (4th). Sergey Shumarayev is the Director of Engineering at Altera Corporation in charge of Analog Design. He has worked at Altera for over 10 years in capacities of Design Engineer, Serdes Team Engineering Sr. Design Manager and Analog Group Director. He holds a Masters degree in Electrical Engineering from Cornell University and a B.S. in Electrical Engineering Computer Science and Material Science from the University of California at Berkeley. He has over 30 issued patents and has co-authored several papers. Kwong-Wen Wei is a design engineer at Altera Corporation. Wei holds a MS in EE from the University of California, Berkeley. He worked at Sun MicroSystems for about seven years before joining the high-speed transceiver design group at Altera working on the 3rd and 4th generation of the transceiver.

- 4 -

Introduction Modern SERDES transceivers now offer many combinations of signal conditioning to combat the signal integrity (SI) challenges over the conflicting relationship between data rate increase and system component degradation. Integrated circuits (ICs) make many choices available to designers needing the best fit for their system designs. Motivation Altera® Stratix® II GX 6-Gbps transceivers have more than a thousand equalization settings for both the transmitter and receiver. For each customer link, an engineer starts with an initial estimation of settings for the transceiver and adjust the settings in an attempt to achieve an acceptable eye opening at the end of the link. As a result, if the eye does not meet the pre-determined specification, the designer must choose another setting. The entire process continues until the eye diagram is created to meet the specification. HSPICE is the traditional simulator used by most circuit designers. A single HSPICE simulation can take several hours to complete, resulting in an extremely long turnaround time to verify the transceiver can equalize one customer link. For example, with 5000 RX and TX settings on a single CPU, it could take three hours per setting—625 days!—to perform a blind simulation search of all possibilities for a given link. Instead, SI engineers could perform a targeted simulation search based on the understanding of the transceiver. Conducting such a search would provide a solution for prohibiting long simulations, but would not guarantee discovering the best solution. FPGA products cover a wide range of customer platforms, hence the trend to incorporate large TX and RX signal conditioning capabilities. As a result, SI engineers use FPGA transceivers to determine output voltages levels, required number of pre-emphasis taps, and the maximum amount of equalization required for the receiver. This paper presents a software-focused solution to overcome the signal conditioning selection challenge in high data-rate programmable transceivers. There is a hardware solution also presented in the conference, “Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps–6.5 Gbps”. The Strategy for Using PELE Pre-emphasis and equalization link estimator (PELE) was created to ease the hardship of designing transceiver equalization by providing a reasonably close-to-perfect solution within a short period of time. The MATLAB tool enables a fast computation for many iterations of link simulation. As the name suggests, it is an estimator. The main focus is using PELE to zoom into a solution space for a particular customer platform, and then use HSPICE, a traditional time-domain SI simulation to reconfirm and obtain results with finer detail for analysis at circuit level. By using PELE in the design of Stratix II GX transceivers, designers were able to discover a highly efficient methodology for setting customer links. In addition, Altera worked with Mentor Graphics to integrate PELE with an EDA simulator to ease the customer burden in handling different tool sets.

- 5 -

PELE in Theory As previously mentioned, PELE is developed in MATLAB. All of the components are represented mathematically. The computation begins in the frequency domain is then converted to the frequency domain for demonstrating the results as well as comparing the time domain simulator. Platform Description Figure 1 shows a typical set up for link simulation where the transmitter resides on a line-card connected through the backplane to a receiver IC on another line-card. The eye diagram at the TX package pin is called the “near-end eye” and at the RX package pin is called the “far-end eye.” The output point of the RX cannot be seen in the entire system nor can it be measured. However, the performance combined with the clock data recovery (CDR) through bit error rate (BER) can be indirectly evaluated.

Figure 1. Link Simulation Set-Up PELE uses an S-parameter to model the environment outside of the two IC packages. The S-parameter is obtained either from the results of customer measurements or by extracting board layout information using EDA tools. The term “customer platform” is used throughout this paper to represent the S-parameter. The IC mathematically represents the transmitter and receiver in the behavior model. The package has its own S-parameter, extracted from a 3D extractor. IC Behavior Modeling Figure 2 shows the PELE testbench set up, where the contributing factor of the conventional HSPICE simulation is the input data pattern. Several protocols call for transceiver qualification by using a high-order PRBS pattern as input. If the number of bits running exceeds a thousand as the order pass PRBS7, the longer the simulation time will be. In MATLAB, the run time is also longer with higher order of PRBS, but the absolute run time compared to HSPICE is much less (minutes versus hours for PRBS7).

- 6 -

Figure 2. PELE Testbench Set-Up The TX is modeled as M-tap finite impulse response (FIR) filter with the coefficient h(k), with the output of the FIR filter described in the following equation:

y(n)=h(0)x(n) + h(1)x(n-1) + h(2)x(n-2) + ... h(N-1)x(n-N-1) This FIR is represented in Z-domain as:

H(z)=h(0)z-0 + h(1)z-1 + h(2)z-2 + ... h(N-1)z-(N-1) , or

The physical behavior of the circuit (rise/fall time, shape and size of the TX output waveform in time domain) is then modeled with a high-ordered low-pass filter as illustrated in Figures 3 and 4. These two models represent the TX in the frequency domain, then convert them to time domain for the purpose of demonstrating the performance in the form of an eye diagram.

- 7 -

Figure 3. TX Output Waveform After High-Order Low-Pass Filter

Figure 4. TX Output Waveform After High-Order Low-Pass Filter With Pre-Emphasis The RX is modeled by set of transfer functions with different gain, pole, and zero locations. The frequency response of the RX is imported from the HSPICE simulation on the actual circuit as shown in Figure 5.

- 8 -

Figure 5. Frequency Response of the Receiver Algorithm Description Since the turnaround time to obtain results from using PELE is faster than HSPICE (or other types of conventional transistor simulators), one method of searching for a solution is to cycle through the available transceiver settings, a “blind search”. Sorting through thousands of transmitter settings to find the best eye diagram using PELE for Stratix II GX devices is very time consuming and inefficient It is however much more efficient than performing the same task using traditional time-domain SI simulation. This method is used to find an existing design where all the equalization coefficients and the number of taps are pre-defined. Using PELE will provide the best eye diagram by searching these settings, as well as remove the possibility of settling into a local minimum solution. In the design cycle planning stage, SI engineers need to determine how many equalization taps to place in the circuit. In this case, PELE can automatically find the optimized solution for a given customer’s platform S-parameter. For example, to determine how many taps and coefficients are required for the transmitter, the designer can place a larger number of taps initially and verify the results by analyzing the PELE output. If the solution does not utilize a high number of taps then the design can refine that number after a few iterations. Similarly, as the board layout is modified (refer to Customer Platform in Figure 2) and new S-parameters are extracted, PELE provides the system performance results than re-running the analysis in HSPICE. Designers have considered various algorithms to speed up the PELE solution space search even further. It was found that using LMS was adequate with u and µ set appropriately in:

H(k)(n+1)=h(k)(n) + µ.u.e [1],[2]

- 9 -

However, the “blind search” method was selected as default in this generation. As the number of programmable options increased further in the next generation products, additional time savings utilizing an LMS search became more beneficial. Examining Criteria of the Best Solution The quality of an eye diagram is the criteria used to select the optimum settings of the transceiver. Using the “blind search” methodology, thousands of eye diagrams, corresponding to each pre-emphasis settings or equalization settings, are generated and stored in MATLAB as matrixes of eye height and eye width. The setting for an eye diagram that provides maximum eye width and jitter focus is chosen as the optimum solution to equalize the given customer platform. PELE Operation PELE offers four options: 1. User allows PELE to find the solution for both TX and RX in the system 2. User can set the pre-emphasis in the TX, PELE will then optimize the RX 3. User allows PELE to find the solution for TX and manually sets the RX 4. User can manually set both TX and RX and view the estimated result of the system The other parameters that are provided include the data rate, S-parameter for the customer platform and the VOD (differential voltage output). Correlation Effort Mathematical equation representation can be ideal and not accounted for completely in the physical behavior of the circuit, therefore it is critical to have the functional block model as close as possible to the transistor level. HSPICE simulation results are used to benchmark the output of PELE. As a result, device specific correlation is achieved, including near-end eye diagram correlation, shown in Figures 6 and 7, and labeled as 1 in Figure 2.

- 10 -

Figure 6. Output of TX With 1 Post Tap Setting From PELE (left) and HSPICE (right)

Figure 7. Output of TX With 2 Post Taps Setting From PELE (left) and HSPICE (right) Figure 8 demonstrates far-end eye diagram correlation, also labeled as item 2 in Figure 2.

- 11 -

Figure 8. Output of TX After XAUI Backplane in 6 Gbps From PELE (left) and HSPICE (right) Figure 9 shows the output of RX correlation, which is labeled as item 3 in Figure 2.

Figure 9. Output of RX After a Customer Backplane in 6 Gbps From PELE (left) and HSPICE (right) Figure 10 shows the output waveform of the RX after a setting is selected for the RX to equalize the customer backplane. The eye diagram is closed and similarly seen in the PELE output.

- 12 -

Figure 10. Output of RX After a Customer Backplane in 6 Gbps From PELE (left) and HSPICE (right) Engagement between EDA vendors and SI engineers give one integrated solution to SI challenges that are faced with modern high data rate transceivers. Adaptation by various SI vendors can enhance the customer experience further by offering rapid interoperability closure. PELE works well to provide a starting point for SI analysis and integrates well into a standard SI analysis environment. Since PELE uses an S-parameter model for its input; the first step is to generate an S-parameter model from the PCB layout. Figure 11 shows how an S-parameter model is extracted using Mentor Graphics’s HyperLynx. Figure 11. S-Parameter Model Extraction The next step is to invoke the configurator on either the Stratix II GX transmitter or receiver. Figure 12 shows how this is accomplished by double-clicking on the TX or RX symbol and then selecting “Configure Model.”

Step 1: Export an S-Parameter model of your channel

- 13 -

Figure 12. PELE Configurator in HyperLynx Once invoked, the configurator provides the user with the ability to perform many functions including invoking PELE and changing the Stratix II GX transmitter, receiver, and global simulation settings. This provides a fast and convenient alternative to dealing with these settings by manually editing the SPICE level netlists. The next step is to choose how PELE should approach the problem. The options include allowing PELE to determine both the optimum TX and RX settings or to lock in the settings of either the TX or RX and allow PELE to find a starting point for the other (see Figure 13). Then the designer must enter the file name of the S-parameter file that was created earlier, indicate the pin mapping of the S-parameter file, and finally initiate the analysis.

Step 2: Invoke the Configurator

- 14 -

Figure 13. Invoking PELE, and Simulating the PELE Results PELE calculates the suggested starting point, and a short time later, the configurator is updated with these settings. The user can then use these settings in a traditional, nonlinear, time-domain signal integrity analysis to determine how well PELE predicted the actual results. The user can then further fine tune the transmitter and receiver configuration in a series of simulations to converge on the optimal solution for the channel at hand, as demonstrated in Figure 14. This is performed by adjusting the configuration settings, applying those settings, initiating a simulation, and evaluating the results.

Step 5: Simulate with PELE suggested settings

Step 3: Select PELE mode and select S-Parameter model

Step 4: Invoke PELE

PELE will update the configuration selections with a suggested starting point based on the channel model characteristics.

- 15 -

Figure 14. Fine Tuning the TX and RX Settings Alternatively, PELE can be set to use the existing configurator settings for the TX, and then search for a solution space by only adjusting the RX parameters, as shown in Figure 15. Likewise, the RX parameters can be fixed and PELE will adjust the TX settings.

Figure 15. Locking Down the TX and RX Settings

Step 6: Fine-tune configuration settings as appropriate

Step 7: Apply updates

Step 7: Re-simulate and repeat as necessary

Step 8: Simulate with adjusted settings

If desired, the TX and RX settings can be locked-down, by selecting “Manual”

In this example, the user designated the TX as “Manual” and entered these settings:

PELE then determines reasonable RX Settings based on the TX settings and the channel characteristics.

- 16 -

Conclusion This paper describes a technique using optimization and DSP techniques to analyze an S-parameter model of the packages and channel, and generate a relatively reasonable result for SI engineers to begin investigating and fine-tuning a circuit to obtain the best solution. Deviation from the ideal response of the transceivers is modeled to obtain a direct correlation with the performance of the silicon. The quick turnaround time, based on fast mathematical computations, enables the IC designer to determine the amount of pre-emphasis and equalization necessary, rather than over-designing, which results in wasting board area and power. This also allows system-level designers to estimate a working solution that provides the best performance based on these calculations, rather than searching blindly for them. The algorithm is then integrated into several SI tools that allow those settings to be used as a starting point for a traditional SI time-domain analysis. This combination saves the SI engineers a significant amount of time using trial and error techniques to find a potential solution, as well as reducing the risk of settling on a sub-optimal solution. References: [1] Y. Tao, W. Bereza, R. Patel, S. Shumarayev, T. Kwasniewski: A Signal Integrity-

Based Link Performance Simulation, Custom Integrated Circuit Conference 2005. [2] W. Bereza, Y. Tao, S. Wang, T. Kwasniewski, and R. Patel: PELE: Pre-Emphasis

and Equalization Link Estimator to Address the Effects of Signal Integrity Limitation, Design Automation Conference 2006.

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific devicedesignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and servicemarks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera productsare protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of itssemiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products andservices at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or servicedescribed herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com