EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Equalization/Compensation of Transmission Media
Channel(copper or fiber)
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Optical Receiver Block Diagram
O E
LA CDREQ DMUX
≈ -18 dBm ≈ 10 mV p-p≈ 10 µA ≈ 400 mV p-p
TIA
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Copper Cable Model
Copper Cable
Where: L is the cable length a is a cable-dependent
characteristic
4-foot cable
15-foot cable
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Effect of Copper on Broadband Data
waveform eye diagram
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Adaptive Analog Equalizer for Copper
Implemented in Jazz Semiconductor SiGe BiCMOS process:• 120 GHz fT npn • 0.35 µm CMOS
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Equalizer Block Diagram
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Analog Equalizer Concept (1)
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C11 1 1
V1V2 V3
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simple channel model bandpass filter combined flat response+ peaked response
Simple linear circuit (normalized to 1Hz):
-0.5
+0.5
1s
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
V1 V2
1
C11 1 1
V1V2 V3
1-0.5
+0.5
1s
Analog Equalizer Concept (2)
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Equalized output pulses: Rise time = voltage swing/slew rate
Rise time nearly constant over different channels!
Analog Equalizer Concept (3)
V3
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Path
Vout
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
f (Hz)
Equalizer Frequency Response
Vcontrol
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
• Simulations indicate that ISI correlates strongly with FFE transition time teq.• Optimum teq is observed to be 60 ps.• Nonlinearities affect pulse shape, but not location of zero crossings.
teq = 75psPW = 86ps
teq = 60psPW = 100ps
2.4 2.5 2.6 2.7 2.8
t (ns)
-0.3
0
0.3VFFE
teq = 45psPW = 108ps
ISI & Transition Time
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Slicer
Restores full logic levels Exhibits controlled transition time
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedback Path
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Transition Time DetectorDC characteristic:
Rectification & filtering done in a single stage.
Transient Characteristic:
t
(a)
(b)
(a)
(b)
ISS
CSS
VS
V+ V-
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Integrator
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Detector + Integrator
slopedetector
slopedetector
FromSlicer
tslicer= 60ps
FromFFEtFFE
Vcontrol
+ _0 10 20 30 40 50
60
40
0
-40
20
-20
-60
t (ns)
Vcontrol (mV)
60ps
45ps
15ps
75ps
90ps
FFE transitionTime tFFE
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
+
_Kd
Kd
Keq
tslicer teqdetector
detector
feedforwardequalizer
integrator
H(s)
Vcontrol
Keq = 1.5 ps/mVKd = 2.5 mV/ps
int = 75ns
System Analysis
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Measurement Setup
Die under test
231 PRBS signalapplied to cable
EQ inputs
EQ outputs
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Measured Eye Diagrams
4-footRU256 cable
(-5 dB atten. @ 5 GHz)
15-footRU256 cable
(-15 dB atten. @ 5 GHz)
EQ input EQ output
4.0 ps rms jitter
3.9 ps rms jitter19
EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Supply voltage 3.3 V
Power Dissipation 350 mW(155 mW not including output driver)
Die Size 0.81mm X 0.87mm
Output Swing 490 mV single-ended p-p
Random Jitter 4.0 ps rms (4-foot cable)3.9 ps rms (15-foot cable)
Summary of Measured Performance
Presented at ISSCC Feb. 2004
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Equalization vs. Compensation
Equalization is accomplished by inverting the transfer function of the channel.
Compensation is accomplished only by canceling the ISI at each unit interval.
Electronic Dispersion Compensation (EDC) refers to the electronics that accomplishes compensation of copper or optical transmission media.
EDC is becoming especially critical as bit rates increase on legacy equipment (e.g., backplane, optical connectors, optical fiber).
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Pre-Cursor/Post-Cursor ISI
T
Input pulse (no ISI):
Output pulse:
0
cursor
pre-cursor ISI post-cursor ISI
T
0
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Equalization (FFE)
Idea: To cancel ISI, subtract a weighted & delayed version of the pulse:
d0
d-1
output pulse:
output pulse delayed by T:
Result with 0 pre-cursor ISI:
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Equalization (2)
T
a1
Time domain:
Frequency domain:
+
_
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Equalization (3)
T
a1
T T
a0 a2 an
N-tap FFE structure:
FFE can cancel both pre- and post-cursor distortion.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Equalization (4)
ISS
V0 V1 V2
R R
Vout +_
3-tap summing circuit:
Coefficients set by gm of each differential pair.
negative coefficient
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Feedforward Equalization (5)
Fractional spacing:
1-tap T-spaced FFE frequency response
1-tap T/2-spaced FFE frequency response
5-tap T-spaced FFE eye diagram
5-tap T/2-spaced FFE eye diagram
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Adaptation (1)
Assume original sequence Din(k) is known.Define error signal e(k) as:
^ where Dout(k) is an appropriately delayed version of Din(k).^
Steepest Descent Algorithm:
• Algorithm moves coefficients in direction of decreasing mean-square error.• Step size µ should be made sufficiently small to guarantee convergence.• Requires knowledge of properties of mean-square error; usually not available.
step size
a1
a2
optimumsetting
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
^
^
FFE output signal:
Adaptation (2)
Least mean-square (LMS) algorithm:
both signals are available on chip.
Analog version of LMS:
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Adaptation (3)
1. Training SequenceA training sequence with known properties is sent through the channel + equalizer. The equalizer output is compared to the original sequence and an error signal is generated.
2. Blind AdapationAdaptation is continually performed while system is running. Only limited properties of the signal are known. An error signal must somehow be generated without having the original sequence.
Types of adaptation:
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Adaptation (4)
FFE
^
+_
• Slicer restores logic levels and opens eye vertically.• Bit sequences at slicer input & input are identical.• Slicer has no effect on placement of zero crossing.• Slicer can be realized using CML buffers with sufficient gain and speed.
Generation of error signal:
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Decision Feedback Equalization (DFE)
T
a1
T T
a0 a2 an
FFE structure:
Noise applied to FFE input will be retained (perhaps filtered) at the output.
DFE structure:
T T T
b1b2bm
+ - - -
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Decision Feedback Equalization (2)
• Slicer is embedded in the structure; Dout is a digital signal.• Delay elements are digital -- commonly realized by DFFs.• Use of slicer suppresses input noise.• Cancels post-cursor distortion only.
T T T
b1b2bm
+- -
-
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
T T T
b1b2bm
+- -
-
Decision Feedback Equalization (3)
2/3
1/3
1
1
2/3
(desired)
1-tap example: post-cursor distortion
consistent with
• Tap weights provide a “look-up table,” canceling post-cursor distortion based on last m bits of output sequence.
• DFE can sometimes “latch up” with wrong tap weights during adaptation.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
T
a1
T T
a0 a2 an
T T T
b1b2bm
+ - - -
FFE + DFE
Combined FFE and DFE can be used to cancel both pre- and post-cursor distortion with low noise.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
Front-End Circuits for DSP-Based Receivers
from channel
Programmable Gain Amplifier (PGA):
VinPGA ADC
AGCVC
VADout [1:n]
where
Automatic Gain Control
“Linear in dB” gain characteristic gives settling time independent of input amplitude.
ADC requires strict control over its input amplitude VA.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
PGA Design
1. Differential Pair:
VC
+_
Vin+ Vin-
Iout- Iout+
ISS
For biasing in weak inversion:
2. Source Degeneration:
2RS
Vin+ Vin-
Iout- Iout+
3. Op-Amp with Feedback:
Vin
+_
Vout
+_
RS
RS
Rf
Rf
RS varied with constant dB per step.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
PGA Example (1)
Realization of RS:
2 dB steps
C.-C. Hsu, J.-T. Wu, “A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier,” JSSC, Oct. 2003, pp. 1663-1670.
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EECS 270C / Winter 2014 Prof. M. Green / UC Irvine
PGA Example (2)
gain of single diff. pair
where N = number of diff. pairs turned on
J. Cao, et al., “A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s links over backplane and multimode fiber,” ISSC 2009, pp. 370-371.
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Track & Hold Circuit
The T/H circuit is comprised of two switch-capacitor stages and an amplifier which provides gain and isolation.
Dummy switches are used to cancel channel charge injection and achieve better linearity.
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Simulation Results
T/H differential output for fin = 1.5 GHz and fs=10 GS/sec41
High-speed Comparator
High-Level Clocking:
• Improves isolation between the input and output, reducing kickback from output.
• Cascoding of the clock switches reduces the Miller effect of the input transistors.
• Reduced headroom
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Comparator/Latch Results (1)
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Metastable Behavior (1)
Metastable event
T/H output
Comp./Latch output
What is the probability of this error occurring?
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Metastable Behavior (2)
R R
CtCt
v1
+
−v2
+
−
t45
Metastable Behavior (3)
Vin (analog)
Vout (digital)
1 2 3
01
10
11
000
+e-e-Vdec +Vdec
2e2Vdec
VLSB
Vdec = minimum detectable logic levele = minimum input at t = 0 so that output
level is ≥ Vdec at t = T/2Error probability:
Including comparator gain:
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Metastable Behavior (4)
t
Recall:
For error-free operation after half-clock period:
Error probability:
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Additional high-speed latches following the comparator/latch stage reduces probability of metastable events at the output.
Latch output
Reducing Metastability Errors
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