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Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

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Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1
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Page 1: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Error Correction and LDPC decodingCMPE 691/491: DSP Hardware Implementation

Tinoosh Mohsenin

1

Page 2: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Error Correction in Communication Systems

2

Error: Given the original frame k and the received frame k’, how many corresponding bits differ? Hamming distance (Hamming, 1950). Example:

Transmitted frame: 1110011 Received frame: 1011001 Number of errors:

noise

TransmitterBinary

informationCorrected

informationframeCorrupted

framechannel Receiver

3

Page 3: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

3

Error Detection and Correction

Add extra information to the original data being transmitted. Frame = k data bits + m bits for error control: n = k + m.

Error detection: enough info to detect error. Need retransmissions.

Error correction: enough info to detect and correct error. Forward error correction (FEC).

Page 4: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Error Correction in Communication Systems

Encoder(Adding

Redundancy)Channel

Decoder(Error Detectionand Correction

Noise

Binary information

Corrected information

Encoded information

Corruptedinformationwith noise

Reed Solomon codes

Hamming codes

LDPC Introduced

Convolutional codes

BCH codes

Renewed interest in LDPC

Turbo codes

197019601950 1990 20001980

Practical implementation

of codes LDPC beats Turbo and

convolutional codes

Page 5: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Modulation

Phase-shift keying (PSK) is a digital modulation scheme that conveys data by changing, or modulating, the phase of a reference signal 

Binary Phase Shift-Keying (BPSK) Modulation phase reversal keying, or 2PSK) is the

simplest form of phase shift keying (PSK). It uses two phases which are separated by 180°

In matlab: 1-2X where X is the input signal Quadrature phase-shift keying (QPSK)

4-PSK, or 4-QAM. QPSK uses four points on the constellation diagram, equispaced around a circle. With four phases, QPSK can encode two bits per symbol, shown in the diagram with gray coding to minimize the bit error rate (BER).

5

Page 6: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Key terms

Encoder : adds redundant bits to the sender's bit stream to create a codeword. Decoder: uses the redundant bits to detect and/or correct as many bit errors

as the particular error-control code will allow. Communication Channel: the part of the communication system that

introduces errors. Ex: radio, twisted wire pair, coaxial cable, fiber optic cable, magnetic tape, optical discs, or

any other noisy medium

Additive white Gaussian noise (AWGN)

Larger noise makes the distribution wider

6

Page 7: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Important metrics

Bit error rate (BER): The probability of bit error. We want to keep this number small Ex: BER=10-4 means if we have transmitted10,000 bits, there is 1 bit error. BER is a useful indicator of system performance independent of error channel BER=Number of error bits/ total number of transmitted bits

Signal to noise ratio (SNR): quantifies how much a signal has been corrupted by noise. defined as the ratio of signal power to the noise power corrupting the signal. A ratio higher

than 1:1 indicates more signal than noise often expressed using the logarithmic decibel scale:

Important number: 3dB means

7signal power is two times noise power

Page 8: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Error Correction in Communication Systems

Goal: Attain lower BER at smaller SNR Error correction is a key component

in communication and storage applications.

Coding example: Convolutional, Turbo, and Reed-Solomon codes

What can 3 dB of coding gain buy? A satellite can send data with half the

required transmit power A cellphone can operate reliably with

half the required receive power Signal to Noise Ratio (dB)

Figure courtesy of B. Nikolic, 2003 (modified)

Bit

Err

or P

roba

bilit

y

100

10-1

10-2

10-3

10-4

0 1 2 3 4 5 6 7 8

3 dBConvolutional code

Uncoded system

noise

8

Information k-bit

channel

Codewordn-bit

Receivedword n-bit

Decoder (check parity,detect error)

Encoder(add parity)

CorrectedInformation

k-bit

Page 9: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

LDPC Codes and Their Applications

Low Density Parity Check (LDPC) codes have superior error performance 4 dB coding gain over convolutional codes

Standards and applications 10 Gigabit Ethernet (10GBASE-T) Digital Video Broadcasting

(DVB-S2, DVB-T2, DVB-C2) Next-Gen Wired Home

Networking (G.hn) WiMAX (802.16e) WiFi (802.11n) Hard disks Deep-space satellite missions

Signal to Noise Ratio (dB)

Bit

Err

or P

roba

bilit

y

100

10-1

10-2

10-3

10-4

0 1 2 3 4 5 6 7 8

4 dBConv. code

Uncoded

Figure courtesy of B. Nikolic, 2003 (modified) 9

Page 10: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Encoding Picture Example

H.ViT=0

1 0 1 1 1 0 1 1 0 0 0 0 … 1 1 1 1 0 0 0 1 1 1 1 10 1 0 0 1 0 0 0 1 0 1 1 … 0 1 1 0 0 1 0 0 0 1 1 00 1 0 1 0 0 0 1 1 1 1 1 … 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 … 0 1 0 0 1 1 1 0 0 1 0 0

… ...

V =

1 0 0 0 0 0 0 0 0 0 . . .1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 00 1 0 0 0 0 0 0 0 0 . . .1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 . . .0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 . . .0 0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1

… ...

H=

Parity Image

V=

Binary multiplication called syndrome check

Page 11: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Decoding Picture Example

20 40 60 80 100 120 140 160 180 200

50

100

150

200

250

20 40 60 80 100 120 140 160 180 200

50

100

150

200

250

50 100 150 200

50

100

150

200

250

20 40 60 80 100 120 140 160 180 200

50

100

150

200

250

Iterative message passing decoding

Receivernoise

Iteration 1

Transmitter

Iteration 5 Iteration 15 Iteration 16

channel

Ethernet cable,

Wireless,

or Hard disk

Page 12: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

LDPC Codes—Parity Check Matrix

Defined by a large binary matrix, called a parity check matrix or H matrix Each row is defined by a parity equation The number of columns is the code length

Example: 6x 12 H matrix for a12-bit LDPC code No. of columns=12 (i.e. Receivedword (V) = 12 bit) No. of rows= 6 No. of ones per row=3 (row weight) No. of ones per col= 2 (column weight)

12

100001010

010100001

001001100

001100010

100010001

10010100

H =

C1

V3 V4 V8V1 V2 V5 V6 V7 V9

C2

C3

C4

C5

C6

001

010

010

100

001

100

V11V10 V12

0

Page 13: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

LDPC Codes—Tanner Graph Interconnect representation of H matrix

Two sets of nodes: Check nodes and Variable nodes Each row of the matrix is represented by a Check node Each column of matrix is represented by a Variable node

A message passing method is used between nodes to correct errors

(1) Initialization with Receivedword(2) Messages passing until correct Example: V3 to C1, V4 to C1, V8 to C1, V10 to C1 C2 to V1, C5 to V1

13

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12Variable nodes

Receivedword from channel

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12Variable nodes

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

The same for other nodes: message passing along the connections

Page 14: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Message Passing: Variable node processing

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

λ is the original received information from the channel14

α: message from check to variable node

β: message from variable to check node

jijhj

j

ij

Z

'1,' '

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

ijjij Z

Page 15: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Message Passing: Check node processing (MinSum)

Sfactorsign ijjjhjjjhj

ijMSijijij

'

',1,'',1,'' min

''

15

Sign Magnitude

After check node processing, the next

iteration starts with another variable node processing

(begins a new iteration)

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V6 V7 V8 V9 V10 V11 V12V6

Check nodes

Variable nodes

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

Page 16: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Code Estimation

Based on your modulation scheme (here BPSK) estimate the transmitted bits

16

V̂V̂

Z

Page 17: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Syndrome Check

Compute syndrome

Ex:

17

H.ViT=0 (Binary multiplication)

If syndrome =0, terminate decoding

Else, continue another iteration

^

Page 18: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Example

Encoded information V= [1 0 1 0 1 0 1 0 1 1 1 1]

18

BPSK modulated= [-1 1 -1 1 -1 1 -1 1 -1 -1 -1 -1] λ (Received data from channel)= [ -9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8]

Estimated code= V= 1 0 1 0 1 0 0 0 1 1 1 1^

Information k-bit

channel

Codeword (V) n-bit

Receivedword(λ) n-bit

Decoder (iterative MinSum)

Encoder

CorrectedInformation

n-bitBPSK modulation

Page 19: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Ex: Variable node processing (iteration 1)

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

19

0

-9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8

12 15

0

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

1Zλ=

111,' '

ihj ij

Page 20: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Ex: Check node processing (Iteration 1)

20

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

1)1)(1)(1()(

}5.2,6.1,6.3{||

13

13

Sign

Min

=-9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8

)(

||

14

14

Sign

)(

||

18

18

Sign

)(

||

110

110

Sign

1Sfactor Here assume

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V6 V7 V8 V9 V10 V11 V12V6

Page 21: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Ex: Code Estimation (Iteration 1)

21

^V

Z

= 1 0 1 0 1 0 0 0 1 1 1 1

Z=λ = [ -9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8]

^V

Page 22: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Ex: Syndrome Check (iteration 1)

Compute syndrome

H.ViT=0 (Binary multiplication)^

22

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

ii

hhjji

SyndromeSyndromSum

vXORSyndromeijij 0|

)(

Sumsyndrome=2 Not ZERO => Error, continue decoding

1 01010001111

x

0 011100

Page 23: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Second iteration In variable node processing, compute β, α and Z based on the algorithm

23

Z= [-12.1 7.1 -4.5 7.7 -7.2 4.4 -4.2 7.2 -10.0 -7.7 -8.9 -8.1]

[ 1 0 1 0 1 0 1 0 1 1 1 1 ]^V=

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

-1.4 -1.6

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

λ= -9.1 4.9 -3.2 3.6 -1.4 3.1 0.3 1.6 -6.1 -2.5 -7.8 -6.8λ=

Page 24: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Ex: Syndrome Check (iteration 2)

Compute syndrome

H.ViT=0 (Binary multiplication)^

24

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

ii

hhjji

SyndromeSyndromSum

vXORSyndromeijij 0|

)(

Sumsyndrome= ZERO => corrected code Terminate Decoding

1 01010101111

x

0 000000

Page 25: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Full-Parallel Decoding

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Every check node and variable node is mapped to a processor

All processors directly connected based on the Tanner graph Very High throughput No large memory storage elements

(e.g. SRAMs) High routing congestion Large delay, area, and power caused

by long global wires

25

Chk1

Chk2

Chk 5

Var1

Var2

Var3

Var 12

Chk1

Chk2

Chk 5

Var1

Var2

Var3

Var 12

init: all α = 0Chk

1Chk

2Chk 6

Var1

Var2

Var3

Var 12

λ from channel

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Var1

Var2

Var3

Var 12

Chk1

Chk2

Chk 6

Var1

Var2

Var3

Var 12

Chk1

Chk2

Chk 6

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Var1

Var2

Var3

Var 12

Chk1

Chk2

Chk 6

Variable nodes

Page 26: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Full-Parallel LDPC Decoder Examples

For all data in the plot: Same automatic place & route flow is used CPU: Quad Core, Intel Xeon 3.0GHz

Ex 1: 1024-bit decoder, [JSSC 2002] 52.5 mm2, 50% logic utilization, 160 nm CMOS

Ex 2: 2048 bit decoder, [ISCAS 2009] 18.2 mm2, 25% logic utilization, 30 MHz,

65 nm CMOS CPU time for place & route>10 days

105

106

1070

100

200

300

Number of wire connections

CP

U t

ime

(h

ou

rs)

512 Chk & 1024 Var

Proc.

384 Chk & 2048

Var Proc.

Page 27: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Serial Decoder Example

C1 C2 C3 C4 C5 C6

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12

Check nodes

Variable nodes

Mem

Row Col

Mem

Row Col

Mem

Row Col

(2)(2) compute compute V1V1and storeand store

V2V2 V3V3

V4V4 V5V5 V6V6

V7V7 V8V8 V9V9

V10V10 V11V11 V12V12

(1) initialize memory(clear contents)

(3)(3) …now …nowcompute compute C1C1and storeand store

C2C2 C3C3

C4C4 C5C5 C6C6

Page 28: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Decoding Architectures

Partial parallel decoders Multiple processing units

and shared memories Throughput: 100 Mbps-Gbps Requires Large memory

(depending on the size) Requires Efficient Control and

scheduling Var Var Var Var

Mem Mem Mem Mem

Mem Mem Mem Mem

Mem Mem Mem Mem

Chk

Chk

100001010

010100001

001010100

001100010

100010001

10001100

H

001

010

010

100

001

100

0

Page 29: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Reported LDPC Decoder ASICs

2000 2002 2004 2006 2008 201010

1

102

103

104

105

Year

Th

rou

gh

pu

t (M

bp

s)

Partial-parallel DecoderFull-parallel Decoder

10GBASE-T

802.16e

DVB-S2

802.11n

802.11a/g

Page 30: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Throughput Across Fabrication Technologies

Existing ASIC implementations without early termination Full-parallel decoders have the highest throughput

659013016018010

1

102

103

104

CMOS Technology (nm)

Th

rou

gh

pu

t (M

bp

s)

Partial-parallel DecoderFull-parallel Decoder

Page 31: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Energy per Decoded Bit in Different Technologies

Existing ASIC implementations without early termination Full-parallel decoders have the lowest energy dissipation

659013016018010

-1

100

101

102

CMOS Technology (nm)

En

erg

y p

er

bit

(nJ/

bit)

Partial-parallel DecoderFull-parallel Decoder

Page 32: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Circuit Area in Different Technologies

Full-parallel decoders have the largest area due to the high routing congestion and low logic utilization

659013016018010

0

101

102

103

CMOS Technology (nm)

Are

a o

f De

cod

er

Ch

ip (

mm

2 )

Partial-parallel DecoderFull-parallel Decoder

Page 33: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Key optimization factors

Architectural optimization Parallelism Memory

Data path wordwidth (fixedpoint format)

33

Check Node + + +_β βiα

λ αiλ

αii=1

λ +

Variable Node

clk

Wc

αii=1

Wc

α1...αWc

Page 34: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Architectural optimization

34 Z. Zhang JSSC 2010

Page 35: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

BER performance versus quantization format

35 SNR(dB)

Page 36: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Check Node Processor

Min1

Min2

β1

βWr/Spn | βWr/Spn|

IndexMin1β2

| αWr/Spn |

| α1 |βn–1

βn

βWr/Spn – 1

| β2 |

| βn–1 |

| βn |

|βWr/Spn – 1|

L = log2(Wr)

Comp

Comp

Comp

Comp

Comp

Comp

Sign (β1)

Sign (αWr/Spn)Sign (βWr/Spn)

Sign (α1)Sign Logic

Mag Logic

Page 37: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

37

Page 38: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Variable Node Processor

Based on the variable update equation The same as the

original MinSum and SPA algorithms

Variable node hardware complexity is mainly reduced via wordwidth reduction

jijhj

ij

ij

'1,' '

+

+

+3

λi λi + αj SM

to 2's

2's to SM

2's to SM

βwc

SM to 2's

j=1:wc

β1

α1

αwc

+

+

++

+

+

-

- SAT

SAT

86

5

8

7

7

7

seven 5-bitinputs

Page 39: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

39

Page 40: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Partial parallel decoder example

40

Page 41: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

802.11ad LDPC code

41

Page 42: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

42

100001001

010100010

001010100

001100010

100010001

10001100

H

001

010

100

100

001

010

0

Page 43: Error Correction and LDPC decoding CMPE 691/491: DSP Hardware Implementation Tinoosh Mohsenin 1.

Transmission scenario

43


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