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1 Micron Confidential | 2012 Micron Technology, Inc. |
2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Microns production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
2 2012 Micron Technology, Inc. |
Embedded Systems Conference 2012
Todd Legler
March 2012
Choosing the DRAM with Complex System Considerations
3 2012 Micron Technology, Inc. |
Choosing the right DRAM
History/DRAM evolution trend
Trade-offs to consider
Performance
Power
Density
Schedule / Time to Market / Sweet spot
Product life targets
Modules vs. components
Future DRAM trends
April 3, 2012
4 2012 Micron Technology, Inc. |
WW DRAM Revenue
April 12
Source: Industry Data Gartner; Micron - Internal Forecast
WW DRAM Revenue
Server 10% AIM
6%
Consumer 10%
Mobile 10%
N&S 3%
Personal Systems,
62% Wireless,
13%
Consumer, 8%
Server, 8%
Networking & Storage,
2%
AIMM, 7%
Based on $34B Gartner estimate for CY2011
Data processing is the dominant DRAM application.
Driver of capex, design, features
The accuracy of numbers outside the data processing/mobile communication application is sometimes questionable
5 2012 Micron Technology, Inc. |
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Volume DRAM Technology Transitions
April 12
Source: Micron Business Development
DRAM % Equivalents
1Gb DDR2
1Gb DDR3
2Gb DDR3
4Gb DDR3
8Gb DDR4
4Gb DDR4
2Gb DDR2
2010 2011 2012 2013 2014 2015 2016
High End -1333
1.35V/1.5V
-1333
1.35V
-1600
1.35V
-1600
1.35V
-1600/-1866
1.35V/1.20V
-1866
1.2V
-2133
1.2V
Main Stream -1333
1.35V/1.5V
-1333
1.35V
-1600
1.35V
-1600/-1866
1.35V/1.20V
-1866/-2133
1.35V/1.20V
-2133/-2400
1.2V
-2400
1.2V
Technology DDR3 DDR3 DDR3 DDR3/DDR4 DDR3/DDR4 DDR4 DDR4
Premium Speed
-1333 -1600 -1866 -1866/-2133 -2400 -2667 -2667
DRAM sweet spot migrates over time *DDR4 - subject to change as JEDEC formalizes hopefully later this year
6 2012 Micron Technology, Inc. |
Future DRAM Trends
Density/features/bandwidth continues to be
driven by PC/Server
Some screening (IT) and specialized products
for Networking & graphics
DDR4 & LPDDR3 are just around the corner
As the consumer world migrates to more mobile
platforms, commodity DRAM converges with mobile
DRAM power savings features
DDR4 adoption led by computing apps needing
improved power savings with increased bandwidth
LPDDR3 adoption leading performance on handheld,
power sensitive applications
Choosing the right DRAM depends on prioritizing your design care-abouts
Technology
DDR DDR2 DDR3 DDR4 LPDDR2 LPDDR3
Price (today)
Availability
Power
Bandwidth
Density
Schedule (today) Infrastructure maturity
Longevity
7 2012 Micron Technology, Inc. |
DRAM Selection As a minimum, try to understand the following in order to judge what
DRAM is appropriate for the application/design
What is the application? Is it a design upgrade or new design?
Proto/Production timeframe & expected life support needs
What type of controller.based on Intel/Arm/??
Which DRAM technology(ies) are supported or planned by the controller
How many MB/GB are needed by the app?
How much bandwidth (GB/sec) is needed by the app?
What is the memory bus width? x32, x64?
How much of a concern is power? Battery life?
Are there any preferred packages, troublesome parameters, concerns?
Does the customer require upgrade path (higher density later)?
April 12
8 2012 Micron Technology, Inc. | April 12
DDR DDR2 DDR3
DDR4
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010E 2011E 2012E 2013E 2014E
DDR4
DDR3
DDR2
DDR
SDRAM
FP/EDO
DRAM Technology Trend
Source: iSuppli, Mkt research
SDR
DDR
DDR2
DDR3
DDR4
50% 50% 50%
bits
Technology cadence is roughly 4 years Technology becomes mainstream ( 50% bits) roughly 2 years after production start
*DDR4 - subject to change as JEDEC formalizes hopefully later this year
9 2012 Micron Technology, Inc. |
DRAM Density Trend
April 12
Source: iSuppli 3Q10
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
2010E 2011E 2012E 2013 E 2014E
4Gb
2Gb
1Gb
512Mb
256Mb
4Gb
2Gb
1Gb
512Mb
1Gb & 2Gb will be dominant densities in 2011 due to popularity of 1GB/2GB/4GB modules 1Gb & 2Gb driven by DDR2 & DDR3 4Gb driven by DDR3 & DDR4
bits
*DDR4 - subject to change as JEDEC formalizes hopefully later this year
10 2012 Micron Technology, Inc. |
System Considerations Addressing
April 12
Designs should route for all densities/configurations they will
want to support
This will avoid redesign and increases design flexibility
4Gb DDR3 (x4/x8) requires
Address A15 (ball J7) to be routed.
This is not required by the 2Gb device
11 Micron Confidential | 2012 Micron Technology, Inc. |
32-bit bus with DDR3
x8
32-bit Bus
x8
x8
x8
x8
x8
x8
x8
1Gb DDR3 components
1GB (8Gb) Buffer 512MB (4Gb) Buffer
32-bit Bus
x8 x8 x8 x8
2Gb DDR3 components
x16 x16
32-bit Bus
4Gb DDR3 components
x16
x16
x16
x16
2Gb DDR3 components
32-bit Bus
8Gb DDR3 components
32-bit Bus
x32
x8
32-bit Bus
x8
x8
x8
x8
x8
x8
x8
512Mb DDR3 components
32-bit Bus
x8 x8 x8 x8
1Gb DDR3 components
x16 x16
32-bit Bus
2Gb DDR3 components
x16
x16
x16
x16
1Gb DDR3 components
32-bit Bus
4Gb DDR3 components
32-bit Bus
x32
Good availability Price/bit > 2Gb Too many chips
512Mb DDR3 not available
Good availability Price/bit > 2Gb Best solution 1Gb
Good availability Price/bit > 2Gb 2-load design
Good availability Minimum chip
x32 not available
Good availability Cheapest 2Gb solution
Good availability 2-load design
Available in 2H11 Price/bit in 2012 Minimum chip
Not Available DDR3 DDR4 density x32 DDR4 TBD
12 2012 Micron Technology, Inc. |
Speed Density Power Comparison Freq. Range (MHz)
Bus Width (per device)
Max. Bandwidth (burst rate)
Transfer rate per pin
Density Row Cycle Time (tRC)
Max Power
SDRAM 100-200 x4, x8, x16, x32
400 MB/s 100-200Mb/s 64Mb - 512Mb
66ns 1W
DDR1 100-200 x4, x8, x16 800 MB/s 200-400Mb/s 128Mb-1Gb 60ns 1W
DDR2 200-400 x4, x8, x16 1.6 GB/s 400-800Mb/s 256Mb-2Gb 55ns 700mW
DDR3 400-1066 x4, x8, x16 3.2 GB/s 800-1600Mb/s 1Gb, 2Gb 48ns 500mW
DDR3L 400-800 x4, x8, x16 3.2 GB/s 800-1600Mb/s 1Gb, 2Gb 48ns 440mW
DDR4 667-1600 x4, x8, x16, x32
12.8 GB/s 1333-3200Mb/s
4-8Gb TBD
13 2012 Micron Technology, Inc. | April 12
DDR4 vs. DDR3 Power Numbers DDR4 outperforms DDR3 and DDR3L in power consumption
0.0
5.0
10.0
15.0
20.0
25.0
5 10 15 20
5.2
10.4
15.6
20.8
GB
Power Budget (W)
Memory Capacity
DDR3 DDR3L DDR4
Power consumption (mW)
Data rate per Watt (Gbps/W)
14 2012 Micron Technology, Inc. | April 12
DRAM Technology Comparison
DDR3 DDR4 GDDR5
Voltage 1.5V/1.35V 1.2V 1.5V/1.35V
Strobe Bi-directional
Differential
Bi-directional
Differential
Free Running
Differential WRITE
Clock
Strobe Config Per Byte Per Byte Per Word
READ Data Capture Strobe based Strobe based Clock Data Recovery
Data Termination VddQ/2 VddQ VddQ
Add/Cmd
Termination VddQ/2 VddQ/2 VddQ
Burst Length BC4, 8 BC4, 8 8
Bank Grouping No 4 - Bank Groups 4 - Bank Groups
On Chip Error
Detection
No Command/Address
Parity
CRC for Data bus CRC for Data bus
Configuration x4, x8, x16 x4, x8, x16 x16 / x32
Package 78 ball / 96 ball FBGA 78 ball / 96 ball FBGA 170 Ball FBGA
Data Rate
(Mbps/pin) 800 2133 1600 3200+ 4000 7000
Component Density 1Gb - 8Gb 2Gb - 16Gb 512Mb-2Gb
Stacking Options DDP, QDP up to 8H (128Gb
stack); single load No
DDR4 combines features from DDR3 & GDDR5 Best of both Worlds
Power Cost Performance *DDR4 - subject to change as JEDEC formalizes hopefully later this year
15 2012 Micron Technology, Inc. |
DRAM Feature Matrix
LPDDR1 LPDDR2-S4B LPDDR3 DDR2 DDR3 /DDR3L DDR4
Die Density Up to 2Gb Up to 8Gb Up to 32Gb Up to 2Gb Up to 8Gb Up to 16Gb (128Gb 8H)
Prefetch Size 2n 4n 8n 4n 8n 8n
Core Voltage (Vdd) 1.8
1.2V
1.8V WL supply req.
1.2V
1.8V WL supply req.
1.8V
1.55V
1.5V
1.35V (L)
1.2V
Separate WL supply 2.5V
I/O Voltage 1.8V, 1.2V 1.2V 1.2V Same as VDD Same as VDD Same as VDD
Max Clock Freq./Data
rate 200Mhz/DDR400 533MHz/DDR1066 800MHz/DDR1600 533MHz/DDR1066
933MHz/DDR1866
1066MHz/DDR2133 (L) 1600MHz+/DDR3200+
Burst Lengths 2, 4, 8, 16 4, 8, 16 8 4, 8 BC4, 8 BC4, 8
Configurations x16, x32 x16, x32 x16, x32 x4, x8, x16 x4, x8, x16 x4, x8, x16, x32
Address/ Command
Signals 22 pins 14 pins
(Muxd command address)
14 pins
(Muxd command
address)
25 pins 27 pins 29 pins
(partial muxd)
Address/ Command
Data Rate
SDR
(rising edge of clock
only)
DDR
(both rising and falling
edges of clock)
DDR
(both rising and falling
edges of clock)
SDR
(rising edge of clock
only)
SDR
(rising edge of clock
only)
SDR
(rising edge of clock only)
On Die Temperature
Sensor Yes Yes Yes No Optional (Lm) TBD
PASR full, half, quarter-
array
optional partial-bank
modes for
1/8th and 1/16th
full, half, quarter-array
with individual bank and
segment masking for
partial-bank modes
individual bank and
segment masking for
partial-bank modes
No No full, , half, ,
1/8 array, and none
Drive Strength
25-ohm (full)
37-ohm (3/4)*
55-ohm (half)
80-ohm (quarter)*
*JEDEC optional
34-ohm
40-ohm
48-ohm
60-ohm
80-ohm
120-ohm
ZQ calibration for +/-10%
accuracy
34-ohm
40-ohm
48-ohm
ZQ calibration for +/-
10% accuracy
18-ohm (full)
35-ohm (half)
34-ohm
40-ohm
ZQ calibration for +/-
10% accuracy
34-ohm
40-ohm
TBD-ohm
ZQ calibration for
+/-10% accuracy
Per Bank Refresh No
Yes
(8-bank devices only) Yes No No
Fine Granularity Refresh
(1x, 2x, 4x)
Output Driver LVCMOS_18 HSUL_12 HSUL_12 SSTL_18 SSTL_15 POD_12
DPD Yes Yes Yes No No No
DLL/ODT No/No No/No No/Yes Yes/Yes Yes/Yes Yes/Yes
Package Options POP, MCP, discrete POP, MCP, discrete POP, MCP, discrete Discrete Discrete Discrete
Temperature Grades AIT (-40C to 85C)
AAT (-40C to 105C)
AIT (-40C to 85C)
AAT (-40C to 105C)
AIT (-40C to 85C)
AAT (-40C to 105C)
AIT (-40 to 95C)
AAT (-40C to 105C)
AIT (-40 to 95C)
AAT (-40C to 105C)
TBD
TBD
*DDR4 - subject to change as JEDEC formalizes hopefully later this year
16 2012 Micron Technology, Inc. |
Component Organization
April 12
Choosing a component organization highly depends on
Width Advantage Disadvantage Typical applications
x4 Chip kill support High density sys support
Requires many components for wide bus applications
High density server applications
x8 ECC Most common config
May require more components for wide bus apps
Desktop, laptops, servers, modules
x16 Provides balance for low density, low cost, with a non-ECC configuration
No ECC support Desktop, Laptop, STB, low-capacity handhelds
x32 Minimum chip solution Die size higher Price Availability
Mobile platforms
Controller loading
System bandwidth
System capacity requirements
ECC requirements
Board space
17 2012 Micron Technology, Inc. |
DRAM Component vs. Module Selection
April 12
As a minimum, we should try to understand the following in order to judge what
DRAM is appropriate for the application/design
Does a design need flexibility of capacity requirements?
Does the customer require upgrade path (higher density later)?
What is the application? Is it a design upgrade or new design?
Is the design point-to-point design between controller?
Advantages of loose component design
Signal integrity: may offer higher bandwidth capability
Shorter height
Advantages of module design
Flexible capacity
Possible board space
18 2012 Micron Technology, Inc. |
Module Options
Basic selection criteria:
Form factor
Height or width restrictions
Registered or unregistered
Loading considerations
ECC or no ECC
Reliability requirements
Density / Capacity
Number of module ranks (CS lines)
Speed
19 2012 Micron Technology, Inc. |
DDR2 Module Form Factors
April 12
Length (mm)
Height (mm)
Pins Capacity Data Main Apps
UDIMM 133.35 30 240 512MB-4GB
(2GB)
X64/
x72 PC / IPC
RDIMM 133.35 30 240 512MB-8GB
(2-4GB) x72 Servers, Routers
VLP RDIMM 133.35 17.9 240 512MB-8GB
(4GB) X72 Routers/switch, server
SODIMM 67.6 30 200 1GB-4GB (2GB)
X64 Laptops
SORDIMM 67.6 30 200 1GB-4GB (2GB) X72 ATCA Blades
FBDIMM 67.6 30 240 512MB-8GB
(4-8GB) X72 Servers
Mini RDIMM 82 30 244 512MB-4GB X72 Networking
VLP Mini RDIMM 82 17.9 244 512MB-4GB x72 Networking
VLP Mini UDIMM 82 17.9 244 2GB x72 Networking
All Voltages = 1.8V, data rate = 667-800MT/s
20 2012 Micron Technology, Inc. |
DDR3 Module Form Factors
April 12
Length (mm)
Height (mm)
Pins Capacity Data Voltage Main App
UDIMM 133.35 30 240 1-4GB
4GB
X64/
x72
1.35V/ 1.5V
PC / IPC
RDIMM 133.35 30 240 1-16GB
(2-8GB) x72
1.35V/ 1.5V
Servers
VLP RDIMM 133.35 18.75 240 1-16GB (4GB) X72 1.35V/ 1.5V
Servers, Routers
VLP UDIMM* 67.6 30 204 1GB-4GB (2GB)
X72 1.35V/ 1.5V
Server/Storage
SODIMM 67.6 30 204 1GB-4GB (2GB)
X64 1.5V Laptops
72b SOUDIMM* 67.6 30 204 2GB-8GB (4GB)
X72 1.35V Server / ATCA
platforms
Mini RDIMM 82 30 244 2-4GB X72 1.5V Networking
Mini UDIMM 82 30 244 2-4GB X72 1.5V Networking
VLP Mini UDIMM 82 17.9 244 2GB x72 1.5V Networking
* New Module Form Factors VLP = Very Low Profile
21 2012 Micron Technology, Inc. |
Standard and Mobile DDR differences
No DLL for Mobile (used in std DDR to align CLK with DQS)
~10mA active current savings
Allows for easier clock stop and clock frequency change
Initialization differences
Basically due to Mobile DRAM use of deep power down
Clocking differences
No DLL on mobile. Therefore, data fires from 1st rising edge of CK and arrives on bus tAC later. On std DDR, data appears on 2nd rising edge of CLK after read command.
I/O Differences
Mobile use LVCMOS (minimal DC pwr consumption, but hi voltage swings)
Std DDR uses SSTL_2 (Vih an dVil are 150mV around Vref of VddQ/2)
22 2012 Micron Technology, Inc. |
Mobile Feature Set
Partial Array Self-Refresh (PASR)
For power savings, PASR allows the user to control the amount of
memory to be refreshed
Can refresh full array, 1/2 array, 1/4 array, 1/8 array, and 1/16 array
Data will be retained only in portions of memory that are selected to be
refreshed. Data in other sections will be lost
PASR is enabled by setting bits 0-2 in EMR
Temperature Compensated Self-Refresh (TCSR)
On-die temp. sensor that controls the refresh interval based on
temperature. Allows for lower power consumption at lower temperatures
Early mobile designs used EMR bits 3 & 4 in lieu of a temp sensor, no
longer necessary (ignored)
Available on all Mobile DRAMs, some DDR3Lm and likely a standard
feature for DDR4
April 12
23 2012 Micron Technology, Inc. |
Mobile Feature Set
Adjustable Drive Strength (DS)
Selectable based on the loading of the memory bus
Four settings: full, , ,
Selectable using bits 5, 6 & 7 of EMR
Deep Power-Down (DPD)
Ultra-low-power mode utilized in applications where system power is
maintained and data retention is not required
Cuts the power to the array and decreases leakage current
After exiting DPD mode, initialization sequence is required
April 12
24 2012 Micron Technology, Inc. |
Temperature Compensated Self Refresh (TCSR)
April 12
Controlled by on-die temperature sensor
Only applicable during Self-Refresh mode
TCSR Available for all Mobile DRAMs & some DDR3
Example above specific to DDR3Lm
0
1
2
3
4
5
6
7
8
9
10
11
40 45 50 55 60 65 70 75 80 85 90 95
Idd
6 (
mA
)
Temperature (C)
Idd6 Self Refresh vs. Temperature
IDD6
IDD6ET
IDD6TC
2X SR
1X SR
1X SR
X SR
30%
20%
30%
25 2012 Micron Technology, Inc. |
LPDRAM Overview
Densities available from Micron
64Mb, 128Mb, 256Mb, 512Mb LP-SDRAM
128Mb, 256Mb, 512Mb, 1Gb, 2Gb LP-DDR SDRAM
Packages
FBGA, KGD, PoP, MCP (w/NAND Flash)
Configurations
x16, x32
Speed (clock frequency, CL=3)
133MHz, 166MHz* (SDR)
133MHz, 166MHz, 185MHz, 200MHz (DDR)
Voltage
1.8V core and I/O
1.8V core and 1.2V IO
Operating ranges
-0C to +70C commercial temp
-40C to +85C industrial temp (IT)
-40C to +105C automotive temp (AT)
April 12
LP DDR2
Key Mobile Features
VDD1 = 1.8V (needed to achieve high frequency timing)
VDD2 =
1.8V (S2A device)
1.35V (S4A device)
1.2V (S2B, S4B devices)
VDDQ/VDDCA = 1.2V
VREF (separate for CLK & DQS)
Temperature Compensated Self-Refresh (TCSR)
Partial Array Self Refresh (PASR) New modes!
Deep Power Down (DPD)
Selectable Output Drive Strength (34, 40, 48, 60, 80)
Programmable burst lengths: 4, 8, 16
10 C/A (Command/Address Pins)
CS, CKE, CK, CK#, DQs, DQS/DQS#
Differential bi-directional DQS scheme
Technological Advancements: 4n-Prefetch on high-end (S4) devices
Allows for 2x speed improvement
Note: 2n-prefetch will remain on low-end (S2) devices
8 Bank Architecture for 1Gb and higher densities (S4)
Note: S2 devices will support 8-bank for 4Gb and 8Gb
DDR Address and Command for pin count reduction
26 2012 Micron Technology, Inc. |
Summary
April 12
Microns DRAM Portfolio offers
Legacy SDRAM through cost/performance leading DDR3 offerings
Discrete and module DRAM solutions
LPDRAM for simplified low power applications
Automotive and industrial qualified solutions
There are many system consideration for selecting a DRAM
27 Micron Confidential | 2012 Micron Technology, Inc. |
29 2012 Micron Technology, Inc. |
Appendix
April 12
30 2012 Micron Technology, Inc. |
Memory Comparison
4/3/2012
DDR2 GDDR3 DDR3 RLDRAM2
Voltage 1.8V/1.8V 1.8V/1.8V 1.5V/1.5V 1.5/1.5/1.8
Interface SSTL1.8 POD 1.8 SSTL1.5 HSTL
StrobeBi-Directional
Differential
Uni-directional
Single Ended
Bi-Directional
Differential
READ and WRITE
Clocks
Termination ODT to Vtt DQs only ODT to Vcc ODT to Vtt DQs only ODT to Vtt DQs only
Burst Length 4 and 8 4 and 8 8 2,4, and 8
Burst Type Sequential/Interleave Sequential Sequential/Interleave Sequential
Additive Latency 0, 1, 2, 3 and 4 NS CL-1, CL-2 NA
READ Latency 3,4, and 5 5,6,7,8, and 9 5,6,7,8,9,10,11 3, 4, 6, 8
WRITE Latency RL-1 1,2,3, and 5 5,6,7,8, RL + 1
Out-Put Drive 18ohms OCD Control40ohms Externally
Calibrated
36 ohms Externally
Calibrated
25-60 ohms Externally
Calibrated
Configuration x4, x8, x16 x32 x4, x8, x16 x9, x18, x36
Package 84 ball FBGA 136 ball FBGA 96 ball FBGA
Data Rate 800 Mbs 1.6 Gbs 1.6Gbs 1067 Mbs
tRC 54ns 43ns 50ns 15ns
30
31 2012 Micron Technology, Inc. |
DDR2 to DDR3 Comparison - Standard Features
4/3/2012
Features/Options DDR2 DDR3 Comments
Pin-out/Package
60-ball; x4, x8
84-ball; x16
FBGA only
78-ball; x4, x8
96-ball; x16
FBGA only
Independent pin-out for
x4/x8 and x16 (simplifies
module design)
Voltage 1.8V
1.8V I/O
1.5V
1.5V I/O
Reduces memory system
power demand
Densities 256Mb-4Gb 512Mb8Gb
Highdensity components
enable large capacity memory
subsystems
Internal Banks 4 (256,512Mb)
8 (1Gb,2Gb,4Gb)
8 (512Mb, 1Gb,
2Gb, 4Gb, 8Gb)
Larger density per monolithic
package, 8-banks is standard
Prefetch
(MIN READ burst)
4-bits
(2 clocks)
8-bits
(4 clocks)
Reduced core speed
dependency for better yield
tCK DLL enabled 125MHz to 400MHz 300MHz to 800MHz Support higher data rates
Micron Confidential
31
32 2012 Micron Technology, Inc. |
DDR2 to DDR3 Comparison - Standard Features
4/3/2012
Features/Options DDR2 DDR3 Comments
Burst length BL4, BL8 BC4, BL8 BC4 provides relief from some BL8
requirements
Burst type Fixed, via LMR
(1) Fixed, via MRS
(2) OTF, on-the-
fly
OTF allows switching between BC4
and BL8 without MRS command
Speed (data pin)
400, 533,
667, 800
Mb/s
800, 1066,
1333, 1600 Mb/s Migration to higherspeed I/O
Additive Latency
{AL}
(Posted CAS)
AL options
(0,1,2,3,4)
AL options
0, CL-1, CL-2
Mainly used in server applications
to improve command bus efficiency
READ Latency AL + CL
CL = 3,4,5,6
AL + CL
CL = 5,6,7,8,9,10,
800(-25E) 5-5-5 1333(-15F) 8-8-8
800(-25) 6-6-6 1333(-15E) 9-9-9
1066(-187E) 7-7-7 1600(-125E) 9-9-9
1066(-187) 8-8-8 1600(-125) 10-10-
10
WRITE Latency RL - 1 AL + CWL
CWL = 5,6,7,8
Reduces Latency combinations, one
latency per tCK range 32
33 2012 Micron Technology, Inc. |
DDR2 to DDR3 Comparison - Standard Features
4/3/2012
Features/Options DDR2 DDR3 Comments
Data Strobes Single-ended or
Differential
Differential
Only Reduce data strobe crosstalk
Data Bus
Termination Rtt
on-die (ODT)
opt. on MB
on-die (ODT)
opt. on MB
Optimized for higher data
rates
Rtt Values 50, 75, 150 ohm 120, 60, 40, 30, 20 ohm
Support higher data rates
Rtt Allowed Read, Writes,
standby Writes, standby
DDR3 does not allow during
Reads
Dynamic ODT none 120, 60 ohm Support 2-slots; Writes only
DQ Driver
Impedance 18 ohm 34 ohm
Optimized for 2 slot and
pt-to-pt systems
Driver / ODT
Calibration none
External
Resistor
Improves accuracy over
voltage and temperature
Micron Confidential
33
34 2012 Micron Technology, Inc. |
DDR2 to DDR3 Comparison - Standard Features
4/3/2012
Features/Options DDR2 DDR3 Comments
MPR
{Multi-Purpose
Register}
none Four registers 2
Defined, 2 RFU
Provides specialty
readouts
Write Leveling none DQS captures CK, DQ
drives out CKs state
De-skews fly-by layout
used by modules
RESET# none Dedicated input Disable outputs,
Resets DRAM
Modules
240-pin UDIMM,
RDIMM, FBDIMM;
200-pin SODIMM
240-pin UDIMM;
RDIMM and FBDIMM
TBD;
204-pin SODIMM
Similar dimensions as
DDR2
Micron Confidential
34
35 2012 Micron Technology, Inc. |
DDR2 to DDR3 Comparison - Optional Features
4/3/2012
Features/Options DDR2 DDR3 Comments
ASR (Automatic Self
Refresh) none Optional
Automatically adjust
refresh rate during Self
Refresh mode
tCK DLL disabled Undefined
(optional)
128KHz to 125MHz
(optional)
Provides some guidance
for DLL disabled mode, if
supported
ODTS, via MPR
(On Die Temp Sensor) none
2 readout points
(3 states 1X, 2X, >2X
refresh rate), Optional
ODTS to trip at Refresh
points, with 2C grace
margin. 85C, 95C
35
36 2012 Micron Technology, Inc. |
Idd6 (mA)
Micron DDR3Lm
DDR3L:
DDR3(L) specs account for a long IDD6 tail in the distribution at 85C max
DDR3Lm:
Same die as standard DDR3Lm, with:
Tighter IDD6 spec , TCSR enabled @
1.35V
TCSR is optional feature on DDR3L
Mode Register 2 changes required
Statistical correlation to relate 85C max to
45C and 85C typical
Only max values are tested in production
Availability
42nm 2Gb & 4Gb now
30nm 2Gb & 4Gb samples now, MP 2Q12
Example of 4Gb (30nm) Specification
What is it? Normal IDD6 Distribution at 85C
DDR3Lm Max 85
DDR3L Max 85
Alternative for Systems Needing to Improve Standby Power with Cost Efficient PC DRAM
Room temp self refresh 45C Typ.
Elev. temp self refresh
85C Typ.
Elev. temp self refresh
85C Max
DDR3L (mA)
N/A N/A 22
42nm DDR3Lm
(mA) 6 10 12
30nm DDR3Lm
(mA) 3.7 6 7.5
37 2012 Micron Technology, Inc. |
Micron DDR3Lm Required Mode Register 2 Change
April 3, 2012
The AUTO SELF REFRESH (ASR) function is required for DDR3Lm as it included TCSR
(Temperature Control Self Refresh) when the ASR [M6] bit is enabled.
When ASR [M6] is disabled (default), the self refresh rate is assumed to be at the
normal 85C limit (1X refresh rate)
When ASR [M6] is enabled and TC is less than 45C, the TCSR feature will
substantially reduce the self refresh current by reducing the self refresh rate to 1/2X
38 2012 Micron Technology, Inc. |
0
1
2
3
4
5
6
7
8
9
10
11
40 45 50 55 60 65 70 75 80 85 90 95
Idd
6 (
mA
)
Temperature (C)
Idd6 Self Refresh vs. Temperature
IDD6
IDD6ET
IDD6TC
DDR3Lm Self Refresh vs. Temp.
April 3, 2012
2X SR
1X SR
1X SR
X SR
30%
20%
30%
39 2012 Micron Technology, Inc. |
Summary Power Comparison x16 SDRAM Devices
Tuesday, April 03, 2012
Main Memory System = 2 x 32b Channels, 2GB Total Populated with x16 SDRAM Devices = (4)(4Gb) = 2GB
Memory Technology
Data Rate = 1866 Data Rate = 2133
Per DRAM (mW)
Main Memory Total (mW)
Per DRAM (mW)
Main Memory Total (mW)
DDR3 171.8 687.2 190.8 763.2
DDR3L 153.1 612.4 165 660
DDR4 109.9 439.6 122.1 488.4
40 2012 Micron Technology, Inc. |
Micron LPDDR & LPSDR Overview
April 12
Densities available from Micron
64Mb, 128Mb, 256Mb, 512Mb LP-SDRAM
128Mb, 256Mb, 512Mb, 1Gb, 2Gb LP-DDR SDRAM
Packages
FBGA, KGD, PoP, MCP (w/NAND Flash)
Configurations
x16, x32
Speed (clock frequency, CL=3)
133MHz, 166MHz* (SDR)
133MHz, 166MHz, 185MHz, 200MHz (DDR)
Voltage
1.8V core and I/O
1.8V core and 1.2V IO
Operating ranges
-0C to +70C commercial temp
-40C to +85C industrial temp (IT)
-40C to +105C automotive temp (AT)
41 2012 Micron Technology, Inc. |
LPDDR2 Advantages
Double Data Rate Address & Command inputs
Signal re-use helps to reduce pin count
Important since a differential DQS pair (i.e. DQS + DQS# per byte) is now required for higher
frequency operation; also, a Vref input is required for improved signal margin
Higher densities achievable with no increase to number of address pins
LPDDR 1Gb (x16) Requires 14 Address Pins
LPDDR2 has a total of 10 Address/Command pins that can address up to 8Gb
Higher frequency operation
Up to 533MHz (DDR-1066) supported in specification.
Improved Partial Array Self-Refresh (PASR)
New scheme is more flexible, allowing both bank and segment masking for 8-bank devices
Per-bank refresh functionality for improved scheduling
Low power consumption
Expectation is that LPDDR2 devices will consume the same amount of power or less compared
to LPDDR devices at a given frequency
8-Banks for 1Gb and higher on high-end (LPDDR2-S4) devices
Improved performance when interleaving banks and performing concurrent operations
April 12