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• Client Locations
Professional Services Only
No Product Sales! Ted Dangelmayer
www.dangelmayer.com
Cheryl Tulkoff, DfR Solutions
www.dfrsolutions.com
ESD Damage – The Surprisingly Dominant
Failure Mechanism!
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Outline
• Introductions
• ESD – The Surprisingly Dominant Failure Mechanism
• ESD vs. EOS
• Technology Roadmap Information
• ESD Models – Brief Background & Overview
• Model (CDM), Electrical Overstress (EOS) differentiation
• Board & Assembly Level Models
• EOS Diagnosis & Misdiagnosis – Case Studies
• Damage Prevention Techniques
• Design Solutions
• Manufacturing Solutions
Copyright © 2010 Dangelmayer Associates & DfR Solutions 3
• We use Physics-of-Failure (PoF) and Best Practices expertise to provide knowledge- based strategic quality and reliability solutions to the electronics industry
• Technology Insertion
• Design
• Manufacturing and Supplier Selection
• Product Validation and Accelerated Testing
• Root-Cause Failure Analysis & Forensics Engineering
• Unique combination of expert consultants and state-of-the-art laboratory facilities
Who is DfR Solutions?
Copyright © 2010 Dangelmayer Associates & DfR Solutions
DfR Activities
1995 2005 2015
0.1
1.0
10
100
1000
Year produced
Mean
Service
life, yrs.Computers
laptop/palm
cell phones
Airplanes
Telecom
Medical
0.5 m 0.25 m 130 nm 65 nm 25 nm
Technology
Reliability
Gap
1995 2005 2015
0.1
1.0
10
100
1000
Year produced
Mean
Service
life, yrs.Computers
laptop/palm
cell phones
Airplanes
Telecom
Medical
0.5 m 0.25 m 130 nm 65 nm 25 nm
Technology
Reliability
Gap
Technology Insertion Design Reviews
Supply Chain / Manufacturing Root-Cause
Analysis
Product
Testing
Pb-Free
Transition
Copyright © 2010 Dangelmayer Associates & DfR Solutions 5
Knowledge and Education (Website)
• Let your staff learn
all day / every day
E-LEARNING
• Scholarly articles
• Technical white papers
• Case studies
• Reliability calculators
• Online presentations
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Cheryl Tulkoff’s Bio
• Over 20 years in
Electronics
• IBM, Cypress Semiconductor, National Instruments, DfR
• SRAM and PLD Fab (silicon level). Printed Circuit Board Fabrication, Assembly, Test & Failure Analysis. Reliability Testing and Management.
• ISO audit trained, ASQ CRE, Senior ASQ & IEEE Member
• Random facts:
• Rambling Wreck from Georgia Tech
• 12 year old son David, Husband Mike, Chocolate lab Buddy
• Marathoner/Distance Runner – Ran my 1st Boston in 2009 in 3:15!
• Triathlete – Sprint, Olympic, and Half. Ironman finisher in CDA, Idaho in June ‘10
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Dangelmayer Associates (DA) Mission Statement
ESD Professional Services
We work in partnership with our clients to leverage our
expertise and integrity for their prosperity!
Our goal is for our clients to achieve ESD self-sufficiency
through use of our proven quality systems, disciplined
processes and guidance. We achieve this goal with the
only team that has both
globally recognized technical expertise and
operational manufacturing experience.
Copyright © 2010 Dangelmayer Associates & DfR Solutions
The DA ESD Dream Team
• Lou DeChiaro, Ph.D.
Director Physics • Foremost ESD Authority On
• Device FMA & EOS/ESD Differentiation
• Optoelectronics – Lasers etc. • Device CDM/HBM Design
Protection • Circuit Board Design
• System Design Hardening • Mathematical Modeling
• Min-Chung Jon, Ph.D.
Director Materials Science • Resolved Industry Wide Materials Issues
• Ginger Hansel, BS; BSEET; MBA
Director Manufacturing Programs
• Former Motorola Global ESD Program Mgr • Certified iNARTE Engineer
• Larry Fromm, BSEE, MBA, CQM, PE
Director Manufacturing Programs
• Former HP & Finisar Global ESD Program Mgr.
• Certified iNARTE Engineer
• Arnie Steinman, MSEE Business Development Director • Foremost Ionization Authority
• Certified iNARTE Eng. & ESDA Program Manager
• Carl Newberg, MSE, PE Director S20.20 Programs • Certified iNARTE Eng. & ESDA Program Manager • ESDA S20.20 Instructor • ISO 9000 Lead Auditor
• Vicki Dangelmayer, BS, MS Business Development Vice President
Ted Dangelmayer, BSEE
President/CEO
Terry Welsher, Ph.D.
Senior Vice President
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Customer Base
Copyright © 2010 Dangelmayer Associates & DfR Solutions
• EPM:
• ESD Program Management:
A Total EPM Quality System
• EPM Performance Benchmarking™
• Measurement of Relative Compliance to
Current Best Practices
• CDM – Charged Device Model
• HBM – Human Body Model
• MM – “Meaningless Model”
• CBE – Charged Board Event
• CDE – Charged Cable Event
• EOS – Electrical Overstress
• IC Damage due to Electrical Over Voltage or Current
ESD Definitions
Copyright © 2010 Dangelmayer Associates & DfR Solutions
ESD Failures
• ESD Failure Information is mostly available at the device
level
• The “easiest to capture” data is from semiconductor “back-
end” assembly
• Proper assignment of failure cause requiries good FA and
root cause analysis (RCA)
• Good FA and RCA often lacking especially downstream
• ESD can easily be misdiagnosed as “EOS”
• ESD failures in higher level assemblies are unreported –
corrective actions not taken!
Copyright © 2010 Dangelmayer Associates & DfR Solutions
What is Significance of ESD? Typical IC Device Defect Analysis
0
50
100
150
200
250
300
350
NTF EOS FAB Asmbly Test ESD
~50% - ESD(CDE/CBE)
~20% - ESD
100% - ESD
Copyright © 2010 Dangelmayer Associates & DfR Solutions
ESD Damage:
The Surprisingly Dominant Failure Mechanism!
After EOS Misdiagnosis Adjustment:
ESD is #2 Cause of IC Failure!
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Human Body Model
When the air breaks
down between the
human’s finger and
an IC pin, charge is
suddenly
transferred from the
person via the
grounded pin of the
IC to ground.
HBM
Charged Person Device
Charge “Flow” Ground
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Charged Device Model
Conductive Surface
CDM Video
Device Contact Resistance
Capacitance of
Device
Charge
“Flow” Q
Ground
“99% of ESD Failures are CDM!”
Andrew Olney, Analog Devices, Quality Director & Industry Council
Copyright © 2010 Dangelmayer Associates & DfR Solutions
HBM And CDM Waveforms (500v)
0 1 2 3 4 5 6 7 8 9 10 11
0
1
2
3
4
5
6
7
8
Cu
rren
t (A
)
Time (ns)
CDM
HBM (200 ns )
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Industry Council Roadmap - 2009
Industry Council WPII 2009
Copyright © 2010 Dangelmayer Associates & DfR Solutions
CDM Threshold Dependencies
Ref: Industry Council WPII 2009
Larger Device Package Size
Higher
Operating
Speeds
Copyright © 2010 Dangelmayer Associates & DfR Solutions
ESD Failures beyond “device level”
• Charged Board Event (CBE)
• Charged Cable Event
• System-Level
• Hard failures (device damage)
• Recoverable malfunction (transient latch-up)
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Charged Board Event (CBE)
Photograph courtesy: Andrew Olney, Quality Director, Analog Devices
Copyright © 2010 Dangelmayer Associates & DfR Solutions Courtesy: Andrew Olney, Quality Director, Analog Devices
CBE ESD Damage - A New Discovery!
Most FA Experts Misdiagnose as EOS!!!!
Up to 50% of EOS Failures are CBE ESD! (2008)
CDM Device Damage CBE (ESD)
Device Damage on Circuit Board
Copyright © 2010 Dangelmayer Associates & DfR Solutions
FICBM vs. FICDM Discharge Waveforms
for DSP with a 250V Charge Voltage
-2
0
2
4
6
8
10
0.0
0
0.2
5
0.5
0
0.7
5
1.0
0
1.2
5
1.5
0
Time (nanoseconds)
Pe
ak
Cu
rre
nt
(Am
ps
) GND test pad FICBM
GND pin FICDM
CBE vs. CDM Discharge
Waveform Comparison
(250 V)
Courtesy: Andrew Olney, Quality Director, Analog Devices
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Faceplate Field- Induced CBE Failure
Established Code - New Faceplate Supplier
40% Failure Rate - 1.5KV CDM Threshold
Ref: ESD Program Management, 2nd edition, pp59-61
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Cable Discharge Events (CDE)
25
Charge on cables can induce a
discharge to equipment causing
damage or malfunctions
Copyright © 2010 Dangelmayer Associates & DfR Solutions
CDE in Assembly
p26
Plastic bags triboelectrically
charge cable as they are
removed
Copyright © 2010 Dangelmayer Associates & DfR Solutions
CDE in Assembly
p27
Detector confirms that CDE occurred
when cable was inserted into
assembly
Copyright © 2010 Dangelmayer Associates & DfR Solutions 28
CDE Tester Design
10 MΩ Ethernet Cable (Charge Line)
Relay
Bank
PC
Relay
Controller
Test
Board
Ground Plane
Short
Ethernet
Cable
To Earth
Ground
DUT
High Voltage
DC Power
Supply
Courtesy of Texas Instruments
Copyright © 2010 Dangelmayer Associates & DfR Solutions
ANSI/ESD S20.20 Scope:
This document applies to activities that manufacture,
process, assemble, install, package, label, service,
test, inspect, transport or otherwise handle electrical
or electronic parts, assemblies and equipment
susceptible to damage by electrostatic discharges
greater than or equal to 100 volts HBM.
Note: While the scope of the document specifically addresses
100 volts HBM, the principles applied are an essential foundation
for CDM mitigation.
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Best Industry
Manufacturing Standard
ANSI/ESDA S20.20
Scope: HBM >100V
Thus:
S20.20 Customization
is Essential for :
Class 0, CBE & CDM
Industry Standards
Lag Technology
5 to 10 years
Copyright © 2010 Dangelmayer Associates & DfR Solutions
General Considerations
• Maintain All ESD Elements at Same Potential
• Common Point Ground
• Equipotential Bonding
• Minimize Static Voltages on People and Product
• Remove Unnecessary Insulators
• Evaluate Need for Ionization
• Approved Materials
• Application Appropriate
• Transportation within and Outside EPA
• Proper Containers or Packaging
Copyright © 2010 Dangelmayer Associates & DfR Solutions
O
Electrostatic
Protected Area
(EPA)
• Maintain All ESD Elements at Same Potential
• Minimize Static Voltages on People and Product
• Approved Materials
• Transportation within and Outside EPA
Copyright © 2010 Dangelmayer Associates & DfR Solutions
CDM Mitigation Two Strategies – Which One is S20.20?
Lower device voltage or higher surface resistance in the
discharge path can reduce discharge current.
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Two CDM Control Strategies
1. Minimize
Voltage on
or Near
Product
• Define Maximum Allowable Voltage
• No Unnecessary Static Generators
• Manage Essential Static Generators
• Ionization Where Needed
• 12” Rule
2. Minimize
Discharge
Current
• Minimize Metal - Metal Contact
• Use Dissipative Materials At
Point Of Contact
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Device Failure at System Level?
• OEMs have increasing concerns about ESD
failures due to system level stresses
• Wireless
• Laptops, PDA, Smart Phones
• Automotive
• Internet infrastructure
• In response, system-level standards are
being applied (not always correctly)
• Components are tested while powered
while traditional protection is designed for
power-off conditions
Copyright © 2010 Dangelmayer Associates & DfR Solutions
The Industry’s Challenge
The system-level ESD standard (IEC
61000-4-2)
significantly increases amps (2 to 30)
and response speed
(10 to 0.7nanoseconds)
Portable electronics increase
environmental ESD threats
ESD damage is a lifetime product liability
The chart above compares the old
2000V Human Body Model for an ESD
event (gold line at bottom) with the new
IEC 61000-4-2 HMB 8000V Level 4
ESD event.
Copyright © 2010 Dangelmayer Associates & DfR Solutions 38
Set-Up for ESD Gun Zapping of a
Device
Antenna Port to
be pulsed
Component
under Test
Ground Cable Antenna Port to
be pulsed
Component
under Test
Ground Cable
Photo courtesy of Nate Peachey, RFMD
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Impact of Scaling on ESD
• Mobile computing is wide open to ESD damage
• Each IC shrink reduces the oxide thickness and requires more
ESD protection for which there is no room on the shrunk IC
Smaller IC geometries
Higher frequencies
Escalating #’s of signal lines
Reduced board space
Decreasing capacitance budgets
for ESD protection
Reduced budgets for ESD
protection on chip & on PCB
Combined with
Copyright © 2010 Dangelmayer Associates & DfR Solutions
How Will System-Level ESD
Protection Be Provided?
• Device-level protection can not provide adequate ESD for
portable electronics
• Actually never did!
• Previously, many problems were solved through
physical design + additional specified protection
elements (e.g., USB2.0, RS-232)
• New circuit features and RF applications are increasing the
complexity to both ESD and System Level protection
• OEMs are attempting to drive responsibility for protection
to the device level – expensive option!
• A “Co-design” approach is needed (see Industry Council
White Paper 3)
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Comparing HBM and IEC
IEC vs. HBM
0
0.5
1
1.5
2
2.5
0 5 10 15 20
IEC Level (kV)
HB
M L
evel (k
V)
High HBM does not guarantee good system
level performance!
Copyright © 2010 Dangelmayer Associates & DfR Solutions
System on a Chip Bluetooth
Digital, Analog, and RF on the same chip require three different ESD
protection strategies
Interactions through the different ground planes require complex
ESD bus architecture
» Reliable ESD design is very difficult unless coupling between the modules is comprehended
Copyright © 2010 Dangelmayer Associates & DfR Solutions
ESD Sensitive Areas of a Mobile Phone
SMT Devices - USB Connector Array
Microprocessor connector array
USB Connector Array
Copyright © 2010 Dangelmayer Associates & DfR Solutions
What Do You Need to Do?
• ESD Protection is necessary at the IC, component package and system level
• Different approaches are necessitated to achieve reliable protection
• Designing for ESD impacts both the product design but also the manufacturing process controls
• What are the technologies available to assure a reliable ESD protected
Product
At the IC level At the component package level
At the system level
What are the testing methodologies available to ascertain protection levels
Capacitive Discharge
Square Wave pulsers
Copyright © 2010 Dangelmayer Associates & DfR Solutions 46
Design Practices for ESD
• Know the ESD rating for each part, and select parts (where possible) for the best ESD rating • Identify all ESD Sensitive Parts on drawings
• Mark Locations of ESD Sensitive parts on the Board with the ESD symbol
• Consider the entire System (Design) as ESD Sensitive
• Use ESD Protection on all susceptible parts (not just System I/Os)
• Box or System I/O
• ESD Rating < Class 2 IEC (4000V) MANDATORY
• Internal Components (not exposed to outside connectors)
• ESD Rating <= Class 1 ANSI (0-999V) MANDATORY
• ESD Rating < Class 2 ANSI (2000V) WHEREVER POSSIBLE
Copyright © 2010 Dangelmayer Associates & DfR Solutions 47
ESD Design Practices (cont.)
• High Speed, RF and GaAs parts will be particularly sensitive to ESD
• GaAs Parts are typically rated as Class 0 (<250V) or Class 1A (<500V) – ONLY THE BEST PROTECTION DESIGN AND HANDLING PROCEDURES WILL PREVENT DAMAGE TO THESE PARTS!
• Place ESD sensitive components and traces to avoid locations where the board may be handled
• Consider ESD as well as RF shielding
• Where possible install protective devices before ESD sensitive parts
• Avoid Coupled ESD events – Do not route traces to ESD sensitive parts near lines connected to the outside world
Copyright © 2010 Dangelmayer Associates & DfR Solutions 48
ESD Design Practices (cont.)
• Perform Circuit analysis to insure effectiveness of ESD protection (Class 2 ANSI [2000V] for internal, IEC level 2 [4000V] for I/O)
• Test Boards and Systems for Internal and I/O ESD tolerance
• ESD Protection devices must be connected to a good ground to accommodate up to 30A ESD spikes.
• If upset of operating circuits is to be avoided, a separate Earth ground should be used
Copyright © 2010 Dangelmayer Associates & DfR Solutions 49
ESD Sensitive Parts (Pin Sensitivity)
• Any pin of a discrete ESD sensitive part (FET, Transistor, etc) may need protection (if not connected to a supply)
• Input pins
• Can be sensitive since they have little or no built-in ESD protection
• Especially on high speed devices like GaAs ICs or discretes,
• Pins other than inputs (on an ESD sensitive part)
• Can also be sensitive because an ESD pulse can affect internal voltage levels
• Any improperly terminated or unprotected pin can be a conduit for ESD
• Supply pins
• Provide reference bias connections
• Should not need additional protection (as long as they are connected to the power supply)
• Outputs of logical or functional parts designed with active (usually buffered) output stages
• May have clamping diode protection to the supplies and may not need additional protection – check the part ESD rating
Copyright © 2010 Dangelmayer Associates & DfR Solutions 50
Evaluate Potential ESD
• If ESD sensitive parts are used in design, the circuitry
connected to device pins should be evaluated
• Insure that it provides “attenuation” to prevent voltage
in excess of the parts ESD rating from developing in
case the pin or connected traces are contacted during
board handling or system assembly.
• Often the recommended circuit components for
operation of the part will provide adequate ESD
protection.
• This should be verified by analysis or simulation and
extra protection added as required to limit the voltage
seen at the part.
• Assumptions for analysis/simulation
• 2000V,1.5K, 100pf for Internal circuits
• 4000V, 330 Ohms, 150pf for I/Os
Copyright © 2010 Dangelmayer Associates & DfR Solutions 51
ESD Protective Device Options
• Passive Networks
• Capacitors – Simple, Low cost
• Band-pass filters – Somewhat more complex, good ESD protection
• For lower speed devices • Schottky Diodes – Simple, but capacitance loads HF
circuits
• Diode Clamping Arrays – Good for LF circuits and outputs
• For higher speed devices (requiring low capacitance)
• Low capacity protection diodes (<1 pf) – Robust, Good HF compromise
• Polymer ESD (PESD) Protection devices (<0.25 pf) • Excellent HF characteristics, small size 0402, 0603
• PESDs have limited Pulse life, good parts withstand 100 to 1000 strikes
• Operating voltage typically 5V, available to 12V, Trigger Voltage 100, 150V
Copyright © 2010 Dangelmayer Associates & DfR Solutions 52
Simple Capacitive Protection • Use to provide ESD protection on bypassed pins for ESD sensitive
devices, or at Supply input connections
• Make sure capacitance (C2) is significantly larger than the Human Body
Model (>> 150pf) to minimize developed voltage (approx 28 times or 4000pf
for protection of a Device with an ESD sensitivity of 150V)
• May add a Resistor to bleed off charge (from C2)
• Use 200V rated Cap (for C2)
Human
Body
Model
Protection Cap (C2)
Copyright © 2010 Dangelmayer Associates & DfR Solutions 53
Filters
• Band-pass filters can be used for higher
frequency applications and can be effective for
RF system inputs
• Very Robust circuit with good protection
Band-pass Filter 850-2GHz, 50 Ohm Impedance
C1,C2,C3 rated at 100V
Copyright © 2010 Dangelmayer Associates & DfR Solutions 54
Protection with Clamping Diodes
Protection Diode Array (CM1213-01)
Protected
Output ESD Source
ESD at output is clamped at approximately 14V with 4000V ESD hit through
330 Ohm resistance
Copyright © 2010 Dangelmayer Associates & DfR Solutions
PESD (Polymer ESD) plus Inductor
• The Inductor shunts lower frequency energy to ground, removing stress from the PESD.
• Provides better protection than the PESD alone and extends life of the PESD
• The PESD can be used alone for wider bandwidth operation
P
E
S
D
PESD, Trigger
Voltage =150V IEC HBM
Copyright © 2010 Dangelmayer Associates & DfR Solutions 56
Summary of ESD Design Guidelines
• Design ESD Protection for External (System) I/Os to
IEC HBM Class 2 (4000V, 150pf, 330 Ohm) Including:
• RF or signal inputs
• Control and System I/Os that DO NOT have built in
protection to the required limit
• Design ESD Protection for Internal ESD sensitive
parts to meet ANSI 20.20 Class 2 (2000V)
• Know the ESD rating of every part used
• Select parts (where possible) to meet ANSI 20.20 ESD
level Class 2 or better (2000V)
• Parts rated less than Class 2 should have additional
protection circuitry added to protect the board during
handling
Copyright © 2010 Dangelmayer Associates & DfR Solutions 57
ESD Design Guidelines (cont.)
• For External (System) Inputs use Robust protection:
• Band pass filter
• PESD plus Inductor (for Severe condition use PESD + Filter)
• For Internal ESD Sensitive pins use:
• Single bypass Cap (where possible)
• Filter if needed
• PESD or PESD plus Inductor
• Any Pin of an ESD sensitive part may be at Risk If It is NOT:
• Connected to a supply plane
• Adequately decoupled to GND (~4000pf @200V)
• Protected by a “filter” network (simulate for an ESD hit)
• External (System) Output or I/O
• Use low capacitance Clamping diodes (1pf)
• PESD if required for speed (.25pf)
Copyright © 2010 Dangelmayer Associates & DfR Solutions 59
Component Failure Mechanisms:
ESD
• Two primary failure mechanisms:
• Electric field-induced
• Silicon dioxide breakdown ~ 7e8 V/m
• 60Å oxide destroyed at ~ 4.2V
• Shorts gate permanently
• Fields could push carriers into insulators
• May just degrade performance
• Thermal destruction
• Any resistance in path subject to local intense heating
• Contacts, vias, and junctions
• Weakest link goes first
• May also produce “walking wounded”
• Increased leakage
• Increased resistance
• Softened junctions
• All protection techniques fail eventually
• Class A,B, & C specifications are 1kV, 2kV, & 4kV, respectively
Copyright © 2010 Dangelmayer Associates & DfR Solutions 60
Component Failure Mechanisms: ESD
• Protection
• Embedded circuits, shunts
• Design guidelines
• Heat generated proportional to field x
current density
• Maximum at cylindrical junctions
• Heat travels at Si/SiO2 interface
• 10X difference in thermal conductivity
• Al melts at much lower temp than Si
• Uniform layout is crucial – avoid current
crowding
• Avoid “snaking” gates
• As many contacts as feasible
• Space contacts from junction edges
• Wider metal better
• Guard-ring any junctions
Copyright © 2010 Dangelmayer Associates & DfR Solutions 61
Component Failure Mechanisms: ESD
Examples
SEM of P/N junction Source: Frank, EDFAS, 2004
SEM: HBM test on NFET Source: Putnam et al., EDFAS, 2004
SEM of metal line damage Source: Putnam et al., EDFAS, 2004
Light emission of latchup in logic
circuitry Source: Frank, EDFAS, 2004
SEM of silicide shorts in SOI device Source: Prejean et al., EDFAS, 2004 SEM & AFM of lateral ESD on line
Source: Colvin et al., EDFAS, 2004
Copyright © 2010 Dangelmayer Associates & DfR Solutions 62
Scanning Electron Microscopy
Sample rastered with an
electron beam
Emitted electrons sorted by
delay and quantity
Copyright © 2010 Dangelmayer Associates & DfR Solutions 63
Scanning Electron Microscopy
Secondary electron detection yields topographic information
Backscattered electron detection also used for topography and
elemental analysis
Copyright © 2010 Dangelmayer Associates & DfR Solutions 64
Secondary Ion Mass Spectroscopy
(SIMS)
• Two types:
• Static (low current, low
surface perturbation)
• Dynamic (high surface
perturbation; depth
profiling)
• Highest resolution of
surface techniques
• Excellent for assessing
doping concentrations
and multi-layer structures
Quadrupole
dynamic SIMS
Laser diode
failure analysis
Source: Mount et al.,
Microelectronics Failure Analysis, 2004
Copyright © 2010 Dangelmayer Associates & DfR Solutions 65
Focused Ion Beam (FIB) Microscopy
• Similar to SEM, except that Ga ions
are used instead of electrons
• Selective material removal with Ga
ion beam
• Excellent for micro- cross sections,
electrical circuit isolation, and TEM
sample preparation
FIB cross-section of line
Sample removal for high
resolution TEM
Source: Hooghan, Microelectronics
Failure Analysis, 2004
Copyright © 2010 Dangelmayer Associates & DfR Solutions 66
Electron Beam Techniques
• Techniques utilize SEM
with electrical vacuum
feed-through
• Electron beam-induced
current (EBIC)
• Fermi transitions
• Si defects
• Resistive contrast imaging
(RCI)
• Buried and open conductors
• Passivated ICs
• Charge-induced voltage
alteration (CIVA)
• Open conductors
• Passivated and depassivated ICs
Schematic of RCI
CIVA image showing location of open conductor
Source: Cole, Sandia National Labs, 2004
Copyright © 2010 Dangelmayer Associates & DfR Solutions 67
Optical Beam Techniques
Source: Cole, Sandia National Labs, 2004
• Techniques utilize SOM (scanning
optical microscope) and lasers
• Optical beam-induced current
(OBIC)
• Fermi level mapping
• Light-induced voltage alteration
(LIVA)
• Visible laser on front, IR on back
• IC defects, logic states, ESD
• Optical beam-induced resistance
change (OBIRCH) and thermally-
induced voltage alteration (TIVA)
• IR > 1.1 um (> band gap of Si)
• Electrical shorts
• Seebeck effect imaging (SEI)
• Opens
Schematic of
OBIC
LIVA and
reflected image of
microcontroller
TIVA and
reflected image of SRAM
Copyright © 2010 Dangelmayer Associates & DfR Solutions
Questions
Contact information:
Terry Welsher
978 282 8888
www.dangelmayer.com
Contact information:
Cheryl Tulkoff
512 913 8624
www.dfrsolutions.com