ESE 570: Digital Integrated Circuits and VLSI …ese570/spring2016/handouts/...ESE 570: Digital...

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics

Penn ESE 570 Spring 2016 – Khanna

Lecture Outline

!  Review: Symmetric CMOS Inverter Design !  Inverter Power !  Dynamic Characteristics

"  Delay

2 Penn ESE 570 Spring 2016 – Khanna

3

Kenneth R. Laker, University of

Pennsylvania, updated 12Feb15

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n

Review: CMOS Inverter: Visual VTC


4

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n

Review: CMOS Inverter: Visual VTC


5



If Vth is set to ideal case:

If, also

ideal Vth

k R symetric= 1

Important design Eq. for CMOS inverter VTC.

Review: CMOS Inverter: Design/Sizing

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

Vth =12VDD

kR =VDD +VT 0 p −VthVth −VT 0n

"

#$

%

&'

2

kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n

"

#$

%

&'

2

=1 2VDD +VT 0 p1 2VDD −VT 0n

"

#$

%

&'

2

If VT0n= -VT0p= -VT0 (symmetric CMOS)

kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n

"

#$

%

&'

2

=1 2VDD +VT 01 2VDD +VT 0

"

#$

%

&'

2

=1 1= µnWn

µpWp

⇒Wp

Wn

=µn

µp


Review: Noise Margin Example

6



Compute the noise margins for a symmetric CMOS inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V and VT0n = - VT0p = 1 V.

NMH = NML = 2.5 V > VDD/2

RECALL (with VDD = 5 V) 1.

2.

1.

Ideal NM =>

1. NMH, NML > VDD/4 = 1.25 V

NMH = NML = 2.125


Inverter Power


Power

!  P = I×V

!  Tricky part: "  Understanding I "  (pairing with correct V)


Static Current

!  P = Istatic×VDD


Switching Currents

!  Dynamic current flow:

!  If both transistor on: "  Current path from Vdd

to Gnd "  Short circuit current


Currents Summary

!  I changes over time !  At least two components

"  Istatic – no switching "  Iswitch – when switching

"  Idyn and Isc


Currents Summary

!  I changes over time !  At least two components

"  Istatic – no switching "  Iswitch – when switching

"  Idyn and Isc

12

VRAMP

CLK

φ

ramp_enable


Switching

Dynamic Power


Switching Currents

!  Iswitch(t) = Isc(t) + Idyn(t)

!  I(t) = Istatic(t)+Iswitch(t)

14

Isc

Istatic

Idyn


Charging

!  Idyn(t) "  Ids = f(Vds,Vgs) "  and Vgs, Vds changing

15

IDS =kn22 VGS −VT( )VDS −VDS2"# $%

IDS =kn2VGS −VT( )2


Switching Energy – focus on Idyn(t)

16

Isc

Istatic

Idyn


Switching Energy – focus on Idyn(t)

E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫

17

Idyn


Switching Energy

18

!  Do we know what this is?

Idyn

Idyn (t)dt∫



Switching Energy

19


Idyn

Q = Idyn (t)dt∫



Switching Energy

20


!  What is Q? Idyn

Q = Idyn (t)dt∫



Switching Energy

21



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫


Switching Energy

22



Q = Idyn (t)dt∫


€

Q = CV = I(t)dt∫

€

E = CVdd2

Capacitor charging energy


Switching Power

!  Every time output switches 0#1 pay: "  E = CV2

!  Pdyn = (# 0#1 trans) × CV2 / time

!  # 0#1 trans = ½ # of transitions

!  Pdyn = (# trans) × ½CV2 / time


Switching

24

Short Circuit Power


Short Circuit Power

!  Between VTN and Vdd - VTP

"  Both N and P devices conducting

!  Roughly:

25

Isc


Peak Current

!  Ipeak around Vdd/2 "  If |VTN|=|VTP| and sized equal rise/fall

26



Peak Current


27

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *



Peak Current


28

€

I(t)dt∫ ≈ Ipeak × tsc ×12%

& ' (

) *

€

E =Vdd × Ipeak × tsc ×12#

$ % &

' (



Dynamic Characteristics


Inverter Delay

!  Caused by charging and discharging the capacitive load "  What is the load?


Inverter Delay


Inverter Delay


Inverter Delay

33

Cload = C#dbn + C#

dbp + C#gdn + C#

gdp + Cint + Cgb

Cgb = Cgbn+ Cgbp


Inverter Delay

34

Cload ≈ C#dbn + C#

dbp + Cint + Cgb

Usually Cdb >> Cgd Csb >> Cgs


35

Cload ≈ Cdbn + Cdbp + Cint + nCgb

n = fan-out ≥ 1

Inverter Delay


Propogation Delay Definitions

36

VDD

0 t

VDD

0

V50% = VDD/2 Penn ESE 570 Spring 2016 – Khanna


37

t




Rise/Fall Times


MOS Inverter Dynamic Performance

!  ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays

!  DESIGN: For given specs for the propagation delays and Cload*,

determine the MOS inverter schematic

40

METHODS: 1. Average Current Model

Assume Vin ideal

τ PHL ≈ CloadΔVHLIavg,HL

=CloadVOH −V50%Iavg,HL

τ PLH ≈ CloadΔVLHIavg,LH

=CloadV50% −VOLIavg,LH






41

METHODS: 2. Differential Equation Model

Assume Vin ideal

iC =CloaddVoutdt

⇒ dt∫ =CloaddVoutiC

∫dt ≈ τ PHL or τ PLH






42

METHODS: 3. 1st Order RC delay Model

Assume Vin ideal

τ PHL ≈ 0.69 ⋅Cload ⋅Rnτ PLH ≈ 0.69 ⋅Cload ⋅Rp


Method 1

Average Current Model


Calculation of Propagation Delays

44







45







46






Calculation of Rise/Fall Times

47

τ fall ≈ CloadΔV90%−10%Iavg,90%−10%

=CloadV90% −V10%Iavg,90%−10%

τ rise ≈ CloadΔV10%−90%Iavg,10%−90%

=CloadV90% −V10%Iavg,10%−90%





=CloadV90% −V10%Iavg,90%−10%


=CloadV90% −V10%Iavg,10%−90%




=CloadV90% −V10%Iavg,90%−10%


=CloadV90% −V10%Iavg,10%−90%

Method 2

Differential Equation Model


Calculating Propagation Delays

51

Two Cases 1. Vin abruptly rises => Vout falls => 2. Vin abruptly falls => Vout rises =>

Assume Vin is an ideal step-input

iDP - iDn

τ PHLτ PLH


Case 1: Vin Abruptly Rises - τPHL





54

≈

≈



55

≈

≈



56

V out= V DD− V T0n

≈

≈


57

V th− VT0p

V th− VT0n

V th

V th V DD

-1

-1

V ILV IH

Vout = Vin - VT0p

Vout = Vin - VT0n

-VT0n

Recall: CMOS Inverter: Visual VTC



58


≈

CloaddVoutdt

≈ −iDn

dt =Cload−dVoutiDn

τ PHL = dtt=t0

t=t50%∫ =Cload−1iDn

$

%&

'

()

Vout=VDD

Vout=VDD /2∫ dVout

τ PHL =Cload−1iDn

$

%&

'

()

VDD

VDD−VT 0n∫ dVout +Cload−1iDn

$

%&

'

()

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50% Penn ESE 570 Spring 2016 – Khanna


59



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

saturation: iDn =kn2(Vin −VT 0n )

2

τ PHL,sat =Cload−1

kn2(VDD −VT 0n )

2

"

#

$$$

%

&

'''

VDD

VDD−VT 0n∫ dVout

τ PHL,sat =−Cload

kn2(VDD −VT 0n )

2dVoutVDD

VDD−VT 0n∫

τ PHL,sat =2CloadVT 0n

kn (VDD −VT 0n )2



60



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear

linear: iDn =kn2(Vin −VT 0n )Vout −V

2out( )

τ PHL,lin =Cload−1

kn22(VDD −VT 0n )Vout −V

2out( )

"

#

$$$

%

&

'''

VDD−VT 0n

VDD /2∫ dVout

τ PHL,lin =2Cload

kn

−12(VDD −VT 0n )Vout −V

2out( )

"

#$$

%

&''VDD−VT 0n

VDD /2∫ dVout

τ PHL,lin =2Cload

kn⋅

−12(VDD −VT 0n )

ln Vout2(VDD −VT 0n )−Vout( )

"

#$$

%

&''Vout=VDD−VT 0n

Vout=VDD /2



61

τ PHL,lin =2Cload

kn⋅

−12(VDD −VT 0n )

ln Vout2(VDD −VT 0n )−Vout( )

#

$%%

&

'((Vout=VDD−VT 0n

Vout=VDD /2

τ PHL,lin =Cload

kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2

VDD 2#

$%

&

'(



62



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2

τ PHL = 2CloadVT 0n

kn (VDD −VT 0n )2 +Cload


VDD 2"

#$

%

&'

τ PHL,lin =Cload


VDD 2"

#$

%

&'



63



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2 τ PHL,lin =

Cload


VDD 2"

#$

%

&'




VDD 2"

#$

%

&'



64



"

#$

%

&'

VDD


"

#$

%

&'

VDD−VT 0n

VDD /2∫ dVout

t0#t1 t1#t50%

saturation linear


kn (VDD −VT 0n )2




VDD 2"

#$

%

&'

τ PHL,lin =Cload


VDD 2"

#$

%

&'

τ PHL =Cload ⋅1

kn (VDD −VT 0n )2VT 0n

(VDD −VT 0n )+ ln 2(VDD −VT 0n )

VDD 2−1

#

$%

&

'(

)

*+

,

-.

Rn


65

Recall from static CMOS Inverter:

(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:

τ PHL =Cload ⋅1

kn (VDD −VT 0n )2VT 0n

(VDD −VT 0n )+ ln 2(VDD −VT 0n )

VDD 2−1

#

$%

&

'(

)

*+

,

-.

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

kR =VDD +VT 0 p −VthVth −VT 0n

"

#$

%

&'

2



Idea

!  Ptot = Pstatic + Pdyn+ Psc

"  Can’t ignore Static Power (aka. Leakage power)

!  Propogation Delay "  Average Current Model "  Differential Equation Model "  1st Order Model


Admin

!  HW 4 due Thursday, 2/18 "  If you submit online and in-class only the online one will

be graded.

!  Tania Office Hours on Wednesday 2-4pm

!  Journal Thursday "  Gregory Fredeman, et. al., A 14 nm 1.1 Mb Embedded

DRAM Macro With 1 ns Access, pp 230 - 239


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